Xilinx VC709 board user guide

【实例简介】
关于Xilinx vc709板子的介绍,VC709支持pcie 2.0 x8, 8G DDR x2
Date Version Revision 12/04/2014 1.4 Added MT28GU01GAAA1EGC-oSiT part number for the BPI parallel NOr flash memory component to Table l-1, Linear BPI Flash Memory, and References Added a note to Table 1-1. Updated User SMa Clock (UsEr SMa clock_ p and USER_SMA_CLOCK_N), Jitter-Attenuated Clock, I2C Bus, and Power Management Updated part number in Figure 1-4. Updated Figure 1-11 to correct net nanes Added I/O Standard information to Table 1-4, Table 1-5, Table 1-6, Table 1-8, Table 1-14 Table 1-19, and Table 1-20. Added PCler)edge connector information after Table 1-12 Updated description for XADC_GPIo_3, 2, 1, O in Table 1-25. Updated Table A-3 and added Figure A-3. Updated VC709 Board XDC Listing. Updated References UG887(v1.4)December 4, 2014 Www.xilinx.com VC709 Evaluation board C709 Evaluation board Www.xilinx.com UG887(v1.4December 4, 2014 Table of Contents Revision History Chapter 1: VC709 Evaluation Board Features Overview Additional information 7 VC709 Board Features Feature Descriptions Virtex-7 XC7VX690T-2FFG1761C fPGa .,12 Dual DDR3 Memory SODiMMs 14 Linear bPi Flash Memory 22 USB TAG 26 Clock Generatio Memory Clock (sysclk-_233_P and SYsclK-_233_N) FPGA EMCC Clock GTH Transceivers PCIE Endpoint connectivity 38 SFP/SFP+ Module connectors 43 USB-to-UART Bridge 46 12C Bus Status leds User I/o Switches 52 VITA 57.1 FMC1 HPC Connector(Partially Populated) 垂, .........54 Power Management FMC_VADJ Voltage 6 Ⅹ ADC Analog-to- Digital Converter.…… 64 Configuration Options ...66 Appendix A: Default Switch and Jumper Settings GPIO DIP Switch SW2 ...,,69 Configuration DIP Switch SWll Default Jumper Settings 71 Appendix B: ViTA 57.1 FMC Connector Pinouts Appendix C: Master Constraints File Listing VC709 Board XDC Listing 75 Appendix D: Board Setup Installing the vc709 Board in a Pc chassis ,番垂 97 VC709 Evaluation board Www.xilinx.com Send feedback UG887(v1.4)December 4, 2014 &A XILINX Appendix E: Board Specifications Dimensions Environmental emperature 9e Humidity Operating Voltag Appendix F: Additional Resources Xilinx resources Solution centers References Appendix G: Regulatory and Compliance Information Declaration of conformit Directives 103 Standards .103 Electromagnetic Compatibility .103 arking Send feedback Www.xilinx.com VC709 Evaluation board UG887(v1.4December 4, 2014 &A XILINX Chapter 1 VC709 Evaluation board features Overview The vC709 evaluation board for the Virtexe-7 FPGa provides a hardware environment for developing and evaluating designs targeting the Virtex-7 XC7VX690T-2FFG1761C FPGA The vc709 board provides features common to many embedded processing systems, including dual DDR3 small outline dual-inline memory module (soDIMM) memories,an 8-lane PCI Express@ interface, general purpose l/O, and a UART interface. Other features can be added by using mezzanine cards attached to the vita-57 FPGa mezzanine connector(FMC)provided on the board. A high pin count (HPC) FMC is provided. See VC709 Board Features for a complete list of features. The details for each feature are described in Feature Descriptions, page 10 Additional information See Appendix F, Additional Resources for references to documents, files, and resources relevant to the vc709 board VC709 Board features Virtex-Z XC7VX690T-2FFG176IC FPGA 2X 4 GB 1600MTs DDR3 memory SoDimm 128 MB linear byte-wide peripheral interface(BPI)flash memory USB TAG through Digilent module Clock generation Fixed 200 Mhz lvds oscillator Fixed 233.33 MHz LVDS oscillator I-C programmable Lvds oscillator SMA connectors SMA connectors for GTH transceiver clocking GTH transceivers FMC HPC connector(eight transceivers) SMA connectors(one pair for MGT_REFCLK PCI Express(eight lanes) 4 X Small form-factor pluggable plus( SFP+)connectors PCI Express endpoint connectivity Genl 8-lane(x VC709 Evaluation board Www.xilinx.com Send feedback UG887(v1.4)December 4, 2014 Chapter 1: Vc709 Evaluation Board Features &A XILINX Gen2 8-lane(x8 4X SFP+ connectors ·USB-to- UART bridge I2C bus ·I2CMUX IC EEPROM(1 KB) USER IC programmable Lvds oscillator ·2XDDR3 SODIMM socket FMC HPC cOnnector 4 X SFP+ connector 1C programmable jitter-attenuating precision clock multiplier Status leds 12VDC power on ti controlled power good Linear power good FPGA INIT FPGA DONE User I/C User LEDs(eight GPIO) User pushbuttons(five directional CPU reset pushbutton User DIP switch(8-pole GPIO) Switche Power on/off slide switch FPGA PROG B pushbutton Configuration mode dip switch vita 57. 1 FMC HPC connector Power management PMBus voltage and current monitoring through TI power controllers XADC header Configuration options Linear BPl flash memory USB JTAG Digilent) configuration port Send feedback www.xilinx.com VC709 Evaluation board UG887(v1.4December 4, 2014 &A XILINX vervet The vC709 board block diagram is shown in Figure 1-1 Caution! The vC709 board can be damaged by electrostatic discharge(ESD). Follow standard ESd prevention measures when handling the board 4 GB DDR3 Memory 4 GB DDR3 Memory (SODIMM) HPC FMC Connector SODIMM) Differe 128 MB Linear BPl GTH Flash Memory XADC Header S|5324C Virtex/ FPGA Clock Recovery XC7VX690-2FFG1761C User Switches 8-lane PCI Express Buttons. and LEDs Edge Connector 1 KB EEPROM DIP Switch sw11 JTAG Interface USB-to-UART Con Micro-B USB 4X SFP+ Cage 12C Bus Switch Flash addr Bridge Connector UG887c101C12113 Figure 1-1: VC709 Board Block Diagram VC709 Evaluation board Www.xilinx.com Send feedback UG887(v1.4)December 4, 2014 Chapter 1: Vc709 Evaluation Board Features &A XILINX Feature Descriptions Figure 1-2 shows the vC709 board Each numbered feature that is referenced in Figure 1-2 is described in Table 1-1 and following sections Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the board 00) Round callout references a component oo square callout references a component on the back side of the board VIRTEX i(6 (25) XXILINX 5M2312=038 邮E15 4 26)26 点 ● 口四 中曾岛 (28) Figure 1-2: VC709 Board Component Locations Table 1-1: VC709 Board Component Descriptions Schematic Reference 0381499 Callout Designator Component Description Notes Page Number U1 Virtex-7 FPGAXCTVX690T-2FFG1761C with XC7VX690T-2FFG1761C cooling fan J3 Two DDR3 SODIMM memories(4 GB each) Micron MTSKTF51264HZ-1G9E1 10, 14 Micron PC28FO0AG18FE/ U3 BPI parallel NOR flash memory (1 Gb) 24 MT28GUO1GAAAlEGC-OSIT U26 USB JTAG interface(micro-B USB connector) Digilent USB JTAG module 5 System clock, 200 MHz, LVDS (back side ofSiTime U51 3 board) SIT9102-243N25E200.0000 6 I-C programmable user clock LvdS U34 156.250 MHz default frequency (back side of Silicon Labs board SI570BAB0000544DG(2C0x5D) 10 Send feedback www.xilinx.com VC709 Evaluation board UG887(v1.4December 4, 2014 【实例截图】
【核心代码】