实例介绍
【实例简介】
MIPS二进制指令集格式参考。里面详细列举了MIPS指令集的各条指令，以及对应的二进制格式。
6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f BGEZ- Branch on greater than or equal to zero Description: Branches if the register is greater than or equal to zero Operation: if Ss>=0 advance _pc(offsct<<2); clsc advance _pc(4) Syntax bgez Ss, offsct Encoding: 0000 0lss sss0 0001 iiii iiiiiiii iiii BGEZAL-- Branch on greater than or equal to zero and link Description: Branches if the register is greater than or equal to zero and saves the return address in $31 Operation: if Ss>=0$31=PC+8(or nPC +4); advance_ pc(offset < 2 ); else advance_pc(4); x卩∞ al Ss,offset Encoding: 0000 olss sssl 0001 iiii iiiiiiii iiii BGTZ-- Branch on greater than zero Description: Branches if the register is greater than zero Operation: ifSs>0 advance_pc(offset<< 2): else advance_pc(4); Syntax: betz Ss, offset Encoding: 0001 llss sss0 0000 iiii iiiiiiii iiii BLEZ-- Branch on less than or equal to zero Description: Branches if the register is less than or equal to zero eration:if Ss<=0 advance_ _pc(offset<< 2); else advance_pc(4); Syntax blez ss, offset Encoding 0001 l0ss sss0 0000 iiii iiiiiiii iiii BLTZ-- Branch on less than zero Description: Branches if the register is less than zero Operation: ifSs <0 advance_ pc(offset < 2); else advance_pc(4); Syntax bltz Ss. offset Encoding: 0000 olss sss0 0000 iiii iiii iii: iiii BLTZAL - Branch on less than zero and link Description: Branches if the register is less than zero and saves the return address in $31 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 3/10 6/8/12 https:/mail-attachment.gcogleusercortent.com/attachment/ui=2&ik=f6f6bf1b2a&view=att&th=137cb4f Croll. Us5Pe-f8fornPe-14, advance pc fofisct< 2)), cisc advance_(4i).ill yntax Encoding 0000 01ss sss100001111 111111111111 BNE- Branch on not equal Description: Branches if the two registers are not equal peration:if Ss !=St advance pc(offset << 2); else advance_ pc (4) Syntax:bne Ss, St, offset Encoding 000101 ss sSS七t七υ tiili lll iil辶立iii Di ilae Description: Divides Ss by St and stores the quotient in Slo and the remainder in ShI Operation: LO=Ss/St; SHI=SS %St; advance_pc(4); yntax div Ss, St Encoding:0000 00ss ssst tt=t 0000 0000 0001 1010 DIVU-- Divide unsigned Description: Divides Ss by st and stores the quotient in Slo and the remainder in Shi Operation: LO=Ss/St; SHI=Ss %St; advance_pc(4) Sⅵmtax di Ivu ss Encoding: 0000 oOss ssst ttet0000000000011011 J--Jump Description: Jumps to the calculated address Operation:PC=nPC;nPC=(PC&0×000( arget<≤2 Syntax: target Encoding: 0000 10ii iiiiiiiiiiiiiiii iiiiiiii JAL --Jump and link Description: Jumps to the calculated address and stores the return address in S31 Operation: s31=PC +8(or nPC 4): PC=nPC; nPC=(PC &0x 0000000)I( target <<21 Sⅵmtax: ial target coal g 000011 ⊥ 1111111111111i111ii https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 4/10 6/8/12 https://mail-attachment.gcogleusercortentcom/attachment/ui=2&k=f6f6bfb2a&view=att&th=137cb1f- JR--Jump register Description: Jump to the address contained in register Ss Operation: PC=nPC; nPC=Ss; Syntax Ss Encoding:000000sss88000000000000000001000 LB-- Load byte Description A byte is loaded into a register from the specified address Operation:St=- MEM[Ss offset]; advance_pc(4); Syntax: b St, offset(Ss) Encoding 1000 00ss ssst ttet iiii iiii iii. iiii LUI - Load upper immediate Description: The immediate value is shifted left 16 bits and stored in the register. The lwer 16 bits are zeroes Operation: t=(imm << 16); advance pc(4) Syntax: hui St, imm Encoding:0011 11 t ttst iii lili li1- 1111 LW-- Load word Description A word is loaded into a register from the specified address eration:St= MEM[Ss offset]; advance_ pc(4); Syntax lw St, offset(Ss) Encoding 1000 llss ssst ttt iiii iiiiiiii iiii MFHI -- Move from HI Description: The contents of register HI are moved to the specified register Operation: Sd=SHI; advance_pc(4); Syntax mfhi sd ncoding:|000000dcd000001000 MFLO -Move from Lo Description: The contents of register LO are moved to the specified register https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 5/10 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f Operation: Sd=SLO; advance_pc(4); Syntax: mflo sd Encoding:|0000000d0000000010 MULT--Multiply Description: Multiplies Ss by St and stores the result in SLO Operation: LO=Ss* St; advance_pc(4); Syntax mult Ss. St ncoding:|00000ss9s6ttt000000001000 MULTU-- Multiply unsigned Description: Multip lies Ss by St and stores the result in SLO. Operation: LO=Ss* St; advance_pc(4); Syntax: mutu s t encoding:|700。888ttt00000001001 NOOP -no operation Description: Performs no operation Operation: advance_pc(4) Syntax: noop ncoding:|00000000000000000000000000000000 Note: The encoding for a NOOP represents the instruction SLL $O, $O, 0 which has no side effects. In fact, nearly every instruction that has SO as its destination register will have no side effect and can thus be considered a NooP instruction OR- Bitwise or Description: Bitwise logical ors two registers and stores the result in a register Operation: d=Ss St; advance_pc(4); Syntax: or Sd, Ss, St Encoding: 0000 00ss ssst ttct dddd d000 0010 0101 ORI- Bitwise or immediate https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/ 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/ui=2&:k=f6f6bfb2a&view=att&th=137cb1f- Description: Bitwise ors a register and an immediate value and stores the result in a register Operation: t=Ss imm; advance_pc(4); Syntax: ori St, SS, imm Encoding: 0011 olss ssst ttct iiii iiii iiii iii SB- Store byte Description: The least significant byte of st is stored at the specified address Operation: MEMISS+ offset]=(Oxff St); advance_pc (4); Syntax: sb St, offset(Ss) Encoding: 1010 00ss ssst ttet iiiiiiiiiiii iiii SLL -Shift left logical Descrpton shifts a register value left by the shift amount listed in the instruction and places the result in a third register. Zeroes are shifted in. Operation:Sd=St<< h; advance_pc(4) Syntax slID, St, h Encoding 0000 00ss ssst tttt dddc dhhh hh00 0000 SLLV -Shift left logical variable Description. / Shifts a register value let by the value in a second register and places the result in a third register. Zeroes are shifted in Operation: Sd=St<<Ss; advance pc(4); Syntax: slly Sd,St,Ss Encoding: 0000 0Oss ssst tt=t dddd d-----00 0100 SLT-Set on less than ( signed) Description: If Ss is less than St, Sd is set to one. It gets zero otherwise Operation: if Ss<St Sd==1; advance_pc(4); else Sd=0; advance_pc(4) Syntax: sIt d. ss. St Encoding:0000 oss ssst ttet dddd d000 0010 1010 SLTI - Set on less than immediate (signed Description: If ss is less than immediate, St is set to one. It gets zero otherwise Operation:if Ss <imm St-1; advance pc(4); else St-0; advance pc(4); https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/8/12 https:/mail-attachment.gcogleusercortent.com/attachment/ui=2&ik=f6f6bf1b2a&view=att&th=137cb4f Syntax: sIti St. Ss. imm Encoding: 0010 10ss ssst ttet iiii iiii iiii iiii stiu - Set on less than im mediate unsigned Description: If Ss is less than the unsigned immediate, St is set to one. It gets zero otherwise. Operation:if Ss< imm St=1; advance_pc(4); else St=0; advance_pc(4); Sⅵntax stiu St, Ss, imm Encoding: 0010 11ss ssst ttt iiiiiiiiiiiiiiii SLTU - Set on less than unsigned Description: If Ss is less than St, Sd is set to one. It gets zero otherwise. Operation:if Ss<StSd-1; advance_pc(4); else Sd-0; advance_pc(4); Syntax sItu sd ,Ss,St Encoding: 0000 00ss ssst ttet ddda d000 0010 1011 SRA -Shift right arithmetic Descrption, Shifts a register value right by the shift amount(shamt)and places the value in the destination register. The sign bit is shifted in peration:sd=St>> h; advance _pc(4); Syntax: sra Sd, St, h Encoding 鸣g 000000-- t ttt ddda dhh hh00 0011 SRL-- hift right logical lDescritoni /Shifts a register value right by the shift amount(shamt)and places the value in the destination register. Zeroes are shifted in. Operation: Sd=St>> h; advance_pc(4); Syntax: rlsD, St, h Encoding:0000 00-----t ttt dddd dhhh hh00 0010 SRLV -Shift right logical variable Descrption. //Shifts a register value right by the amount specified in $s and places the value in the destination register. Zeroes are shifted in Operation:Sd=St>>Ss; advance _pc(4) Syntax. srlv Sd, St, Ss https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/ui=2&:k=f6f6bfb2a&view=att&th=137cb1f- Encoding 0000 00ss ssst tt=t dddc do00 0000 0110 SUB - Subtract Description: Subtracts two registers and stores the result in a register Operation:Sd-Ss-St; advance pc(4) syntax sub Sd, Ss, St Encoding: 0000 00ss ssst ttet dddd d000 0010 0010 SUBU- Subtract unsigned Description: Subtracts two registers and stores the result in a register Operation: sd=Ss-St; advance_pc(4); Syntax: subu Sd, Ss, St Encoding:0000 00ss ssst ttet dddd d00000100011 SW-Store word Description: The contents of St is stored at the specified address. Operation: MEM[SS offset]=St; advance_pc(4) ymx卜wst。oess Encoding: 1010 llss ssst ttct iiii iiii iiiiiiii SYSCALL System call Description: Generates a software interrupt Operation: advance pc(4) Syntax sysco l Encoding: 0000 00 001100 The syscall instruction is described in more detail on the system Calls page XOR- Bitwise exclusive or Description: Exclusive ors two registers and stores the result in a registe Operation: Sd=Ss St; advance_pc(4); Syntax: xor Sd, Ss, St Encoding:0000 00ss ssst ttt dddd d-----100110 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 9/10 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f XORI-- Bitwise exclusive or immediate Description: Bitwise excusive ors a register and an immediate value and stores the result in a register Operation: st=SsA imm; advance_pc(4); Syntax xor St, Ss. imm Encoding: 0011 10ss ssst ttt iiii iiiiiiii iiii Updated on September 10,1998 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 【实例截图】
【核心代码】
MIPS二进制指令集格式参考。里面详细列举了MIPS指令集的各条指令，以及对应的二进制格式。
6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f BGEZ- Branch on greater than or equal to zero Description: Branches if the register is greater than or equal to zero Operation: if Ss>=0 advance _pc(offsct<<2); clsc advance _pc(4) Syntax bgez Ss, offsct Encoding: 0000 0lss sss0 0001 iiii iiiiiiii iiii BGEZAL-- Branch on greater than or equal to zero and link Description: Branches if the register is greater than or equal to zero and saves the return address in $31 Operation: if Ss>=0$31=PC+8(or nPC +4); advance_ pc(offset < 2 ); else advance_pc(4); x卩∞ al Ss,offset Encoding: 0000 olss sssl 0001 iiii iiiiiiii iiii BGTZ-- Branch on greater than zero Description: Branches if the register is greater than zero Operation: ifSs>0 advance_pc(offset<< 2): else advance_pc(4); Syntax: betz Ss, offset Encoding: 0001 llss sss0 0000 iiii iiiiiiii iiii BLEZ-- Branch on less than or equal to zero Description: Branches if the register is less than or equal to zero eration:if Ss<=0 advance_ _pc(offset<< 2); else advance_pc(4); Syntax blez ss, offset Encoding 0001 l0ss sss0 0000 iiii iiiiiiii iiii BLTZ-- Branch on less than zero Description: Branches if the register is less than zero Operation: ifSs <0 advance_ pc(offset < 2); else advance_pc(4); Syntax bltz Ss. offset Encoding: 0000 olss sss0 0000 iiii iiii iii: iiii BLTZAL - Branch on less than zero and link Description: Branches if the register is less than zero and saves the return address in $31 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 3/10 6/8/12 https:/mail-attachment.gcogleusercortent.com/attachment/ui=2&ik=f6f6bf1b2a&view=att&th=137cb4f Croll. Us5Pe-f8fornPe-14, advance pc fofisct< 2)), cisc advance_(4i).ill yntax Encoding 0000 01ss sss100001111 111111111111 BNE- Branch on not equal Description: Branches if the two registers are not equal peration:if Ss !=St advance pc(offset << 2); else advance_ pc (4) Syntax:bne Ss, St, offset Encoding 000101 ss sSS七t七υ tiili lll iil辶立iii Di ilae Description: Divides Ss by St and stores the quotient in Slo and the remainder in ShI Operation: LO=Ss/St; SHI=SS %St; advance_pc(4); yntax div Ss, St Encoding:0000 00ss ssst tt=t 0000 0000 0001 1010 DIVU-- Divide unsigned Description: Divides Ss by st and stores the quotient in Slo and the remainder in Shi Operation: LO=Ss/St; SHI=Ss %St; advance_pc(4) Sⅵmtax di Ivu ss Encoding: 0000 oOss ssst ttet0000000000011011 J--Jump Description: Jumps to the calculated address Operation:PC=nPC;nPC=(PC&0×000( arget<≤2 Syntax: target Encoding: 0000 10ii iiiiiiiiiiiiiiii iiiiiiii JAL --Jump and link Description: Jumps to the calculated address and stores the return address in S31 Operation: s31=PC +8(or nPC 4): PC=nPC; nPC=(PC &0x 0000000)I( target <<21 Sⅵmtax: ial target coal g 000011 ⊥ 1111111111111i111ii https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 4/10 6/8/12 https://mail-attachment.gcogleusercortentcom/attachment/ui=2&k=f6f6bfb2a&view=att&th=137cb1f- JR--Jump register Description: Jump to the address contained in register Ss Operation: PC=nPC; nPC=Ss; Syntax Ss Encoding:000000sss88000000000000000001000 LB-- Load byte Description A byte is loaded into a register from the specified address Operation:St=- MEM[Ss offset]; advance_pc(4); Syntax: b St, offset(Ss) Encoding 1000 00ss ssst ttet iiii iiii iii. iiii LUI - Load upper immediate Description: The immediate value is shifted left 16 bits and stored in the register. The lwer 16 bits are zeroes Operation: t=(imm << 16); advance pc(4) Syntax: hui St, imm Encoding:0011 11 t ttst iii lili li1- 1111 LW-- Load word Description A word is loaded into a register from the specified address eration:St= MEM[Ss offset]; advance_ pc(4); Syntax lw St, offset(Ss) Encoding 1000 llss ssst ttt iiii iiiiiiii iiii MFHI -- Move from HI Description: The contents of register HI are moved to the specified register Operation: Sd=SHI; advance_pc(4); Syntax mfhi sd ncoding:|000000dcd000001000 MFLO -Move from Lo Description: The contents of register LO are moved to the specified register https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 5/10 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f Operation: Sd=SLO; advance_pc(4); Syntax: mflo sd Encoding:|0000000d0000000010 MULT--Multiply Description: Multiplies Ss by St and stores the result in SLO Operation: LO=Ss* St; advance_pc(4); Syntax mult Ss. St ncoding:|00000ss9s6ttt000000001000 MULTU-- Multiply unsigned Description: Multip lies Ss by St and stores the result in SLO. Operation: LO=Ss* St; advance_pc(4); Syntax: mutu s t encoding:|700。888ttt00000001001 NOOP -no operation Description: Performs no operation Operation: advance_pc(4) Syntax: noop ncoding:|00000000000000000000000000000000 Note: The encoding for a NOOP represents the instruction SLL $O, $O, 0 which has no side effects. In fact, nearly every instruction that has SO as its destination register will have no side effect and can thus be considered a NooP instruction OR- Bitwise or Description: Bitwise logical ors two registers and stores the result in a register Operation: d=Ss St; advance_pc(4); Syntax: or Sd, Ss, St Encoding: 0000 00ss ssst ttct dddd d000 0010 0101 ORI- Bitwise or immediate https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/ 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/ui=2&:k=f6f6bfb2a&view=att&th=137cb1f- Description: Bitwise ors a register and an immediate value and stores the result in a register Operation: t=Ss imm; advance_pc(4); Syntax: ori St, SS, imm Encoding: 0011 olss ssst ttct iiii iiii iiii iii SB- Store byte Description: The least significant byte of st is stored at the specified address Operation: MEMISS+ offset]=(Oxff St); advance_pc (4); Syntax: sb St, offset(Ss) Encoding: 1010 00ss ssst ttet iiiiiiiiiiii iiii SLL -Shift left logical Descrpton shifts a register value left by the shift amount listed in the instruction and places the result in a third register. Zeroes are shifted in. Operation:Sd=St<< h; advance_pc(4) Syntax slID, St, h Encoding 0000 00ss ssst tttt dddc dhhh hh00 0000 SLLV -Shift left logical variable Description. / Shifts a register value let by the value in a second register and places the result in a third register. Zeroes are shifted in Operation: Sd=St<<Ss; advance pc(4); Syntax: slly Sd,St,Ss Encoding: 0000 0Oss ssst tt=t dddd d-----00 0100 SLT-Set on less than ( signed) Description: If Ss is less than St, Sd is set to one. It gets zero otherwise Operation: if Ss<St Sd==1; advance_pc(4); else Sd=0; advance_pc(4) Syntax: sIt d. ss. St Encoding:0000 oss ssst ttet dddd d000 0010 1010 SLTI - Set on less than immediate (signed Description: If ss is less than immediate, St is set to one. It gets zero otherwise Operation:if Ss <imm St-1; advance pc(4); else St-0; advance pc(4); https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/8/12 https:/mail-attachment.gcogleusercortent.com/attachment/ui=2&ik=f6f6bf1b2a&view=att&th=137cb4f Syntax: sIti St. Ss. imm Encoding: 0010 10ss ssst ttet iiii iiii iiii iiii stiu - Set on less than im mediate unsigned Description: If Ss is less than the unsigned immediate, St is set to one. It gets zero otherwise. Operation:if Ss< imm St=1; advance_pc(4); else St=0; advance_pc(4); Sⅵntax stiu St, Ss, imm Encoding: 0010 11ss ssst ttt iiiiiiiiiiiiiiii SLTU - Set on less than unsigned Description: If Ss is less than St, Sd is set to one. It gets zero otherwise. Operation:if Ss<StSd-1; advance_pc(4); else Sd-0; advance_pc(4); Syntax sItu sd ,Ss,St Encoding: 0000 00ss ssst ttet ddda d000 0010 1011 SRA -Shift right arithmetic Descrption, Shifts a register value right by the shift amount(shamt)and places the value in the destination register. The sign bit is shifted in peration:sd=St>> h; advance _pc(4); Syntax: sra Sd, St, h Encoding 鸣g 000000-- t ttt ddda dhh hh00 0011 SRL-- hift right logical lDescritoni /Shifts a register value right by the shift amount(shamt)and places the value in the destination register. Zeroes are shifted in. Operation: Sd=St>> h; advance_pc(4); Syntax: rlsD, St, h Encoding:0000 00-----t ttt dddd dhhh hh00 0010 SRLV -Shift right logical variable Descrption. //Shifts a register value right by the amount specified in $s and places the value in the destination register. Zeroes are shifted in Operation:Sd=St>>Ss; advance _pc(4) Syntax. srlv Sd, St, Ss https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/ui=2&:k=f6f6bfb2a&view=att&th=137cb1f- Encoding 0000 00ss ssst tt=t dddc do00 0000 0110 SUB - Subtract Description: Subtracts two registers and stores the result in a register Operation:Sd-Ss-St; advance pc(4) syntax sub Sd, Ss, St Encoding: 0000 00ss ssst ttet dddd d000 0010 0010 SUBU- Subtract unsigned Description: Subtracts two registers and stores the result in a register Operation: sd=Ss-St; advance_pc(4); Syntax: subu Sd, Ss, St Encoding:0000 00ss ssst ttet dddd d00000100011 SW-Store word Description: The contents of St is stored at the specified address. Operation: MEM[SS offset]=St; advance_pc(4) ymx卜wst。oess Encoding: 1010 llss ssst ttct iiii iiii iiiiiiii SYSCALL System call Description: Generates a software interrupt Operation: advance pc(4) Syntax sysco l Encoding: 0000 00 001100 The syscall instruction is described in more detail on the system Calls page XOR- Bitwise exclusive or Description: Exclusive ors two registers and stores the result in a registe Operation: Sd=Ss St; advance_pc(4); Syntax: xor Sd, Ss, St Encoding:0000 00ss ssst ttt dddd d-----100110 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 9/10 6/8/12 https://mail-attachment.gcogleusercortent.com/attachment/?uj=2&k=f6f6bfb2a&view=att&th=137cb1f XORI-- Bitwise exclusive or immediate Description: Bitwise excusive ors a register and an immediate value and stores the result in a register Operation: st=SsA imm; advance_pc(4); Syntax xor St, Ss. imm Encoding: 0011 10ss ssst ttt iiii iiiiiiii iiii Updated on September 10,1998 https://mail-attachment.googleusercontent.com/attachment/?ui=2&ik=f6f6bf4b2a&view=att&th=137cb4f 【实例截图】
【核心代码】
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