Serial ATA Revision 3.0标准

【实例简介】
SATA 3.0标准规范，底层研究需要；
TABLE OF CONTENTS 1 Revision History… 1 23 1.1 Revision 2.5(Ratification Date October 27, 2005) 23 1.2 Revision 2. 6(Ratification Date February 15, 2007) 23 1.3 Revision 3. 0(Ratification Date: June 2, 2009) cope 1-画面面 5 3 Normative references 3.1 Approved references 27 3.2 References under development 29 3.3 Other references Definitions abbreviations and conventions .31 4.1 Definitions and abbreviations 31 4.1.1 Active port 4.1.2ATA( AT Attachment)…… 4.1.3 ATAPI(AT Attachment Packet Interface) device 31 4.1.4 BER(bit error rate) 4.1.5 bitrate 4.1.6 bit synchronization 4.1.7 burst 1面面 4.1.8byte.. 4.1.9 character 33333 4.1.10 character alignment. 4.1.11 character slipping 3 4.1.12 Click Connect .32 4.1.13cLTF( Closed Loop Transfer Function)…… 32 41.14 code violation .32 41.15 comma character 32 4.1.16 comma sequence 32 4.1.17 command aborted 32 4.1.18 command completion 32 4.1.19 command packet 32 4.1.20 concentrator 33 4.1.21 Control Block registers 33 41.22 control character 33 4.1.23 control port 33 41.24 control variable 33 4.1.25 CRC (Cyclic Redundancy Check) 33 4,126 data character 33 4.1.27 data signal source 33 4.1.28 device .33 4.1.29 device port 3 4.1.30 DCB DC block) 33 4.1.31 differential signal 34 4. 1.32 DJ (deterministic jitter- peak to peak) .::.a. 34 4.1.33 DMa(direct memory access) 34 4.134 Dword 34 4.1.35 Dword synchronization 34 4.1.36EMl( Electromagnetic Interference)…… .34 4.1.37 encoded character .34 4.1.38 endpoint device 34 4.1.39 elasticity buffer 34 41.40 ESATA 34 4.1.41Fbaud .35 4.1.42 FER (frame error rate aaa;a;a;a;aaaaaaa;a;aaaaaaaaa 35 Serial ATA revision 3.0 Gold revision page 3 of 663 4.1. 43 First-party dma data phase 35 4.1.44 First-party dMa access 35 4.1. 45 FIS (Frame Information Structure) 35 4.1. frame 35 4.1.47Gen1 35 4.1.48Gen1i 35 4.149Gen1m 4.1.50Gen1x 35 4.1.51Gen2 35 4.1.52Gen2 国面 35 4.1.53Gen2m 35 4.1.54Gen2x… .36 4.1.55Gen3 36 4.1.56Gen3i 36 4.1.57 HBA(Host Bus Adapter) 36 4.1.58HBws( High Bandwidth Scope)……… 36 4.1.59HFTP( High Frequency Test Pattern)…… 36 4.1.60 hot plug ..36 4.1.61 host port .36 4.1.62 inactive port…… 36 4.1.63 interrupt pending 36 4.1. 64 immediate NcQ command 37 4.1.65 ISl (inter-symbol interference) 37 4.1.66 JMD (jitter measuring device) 37 4.1.67 JTF (Jitter Transfer Function) 37 4.1.68junk 37 4.1.69 LBA (Logical Block Address) 37 4.1.70 LBP(Lone Bit Pattern 37 4.1.71 LED( Light Emitting Diode) 4.1.72 legacy mode 38 4.1.73 legal character 38 4. 1.74 LFSR ( Linear Feedback Shift Register) .38 4.1.75 LFTP (low frequency test pattern) 38 4.1. 76 LL(laboratory load) 38 4.1.77 LSS (laboratory sourced signal or lab-sourced signal) 38 4.1.78 MFTP(mid frequency test pattern) 38 4.1.79 NCQ streaming command 38 4.1.80 NCQ Non-streaming command 38 4. 1.81 OOB(Out-of-Band signaling) 38 4.1.82 OS-aware hot plug 39 4.1.83 OS-aware hot removal 39 4.1.84 Phy offline 39 4.1.85 Plo(programmed input/output) 39 4.1.86 port address 39 4.1. 87 PRD (Physical Region Descriptor) 39 4.1.88 primitive 39 4.1.89 protocol-based port selection 39 4.1.90 quiescent power condition 39 4. 1.91 RJ (random jitter) 39 4.192 sector 39 4.1.93 SEMB (Serial ATA Enclosure Management Bridge)...............40 4. 1.94 SEP (Storage Enclosure Processor) 40 4.1.95 Shadow Register Block registers 40 4.1.96 side-band port selection 40 41.97 SMART 40 4.1.98 SSC (spread spectrum clocking) 40 Serial ATA revision 3.0 Gold revision page 4 of 663 4.1.99 surprise hot plug 40 4.1. 100 surprise hot removal 40 4.1.101 SYNC Escape 40 4.1. 102 TDR(time domain reflectometer 40 4.1.103TIA( timing interval analyzer)……… 41 4.1.104 TJ(total jitter) 4.1.105 Ul (unit interval) 4.1.106 unrecoverable errol 444 4.1.107 UUT (unit under test) 41 4.1.108 VNA (vector network analyzer) 国面 41 4.1. 109 warm plug 41 4.1.110Word 41 4.1.111 XSATA 4.1.112 zero crossing…………… 4.2 Conventions 444 4.2.1 Precedence 面B面画 42 4.2.2 Keywords 42 4.2.3 Numbering 43 42.4 Dimensions .43 4.2.5 Signal conventions 43 4.2.6 State machine conventions 44 4.2.7 Byte, word and Dword Relationships 44 5 General overview , ,,, 47 5.1 Architecture 国面国BB国E面 48 52 Usage models… 49 5.2.1 Internal 1 meter Cabled Host to device 52 5.2.2 Short Backplane to Device 53 5.2.3 Long Backplane to Device 54 5.24 Internal 4-lane Cabled Disk arrays 55 5. 2.5 System-to-System Interconnects-Data Center Applications (XSATA) .57 5.2.6 System-to-System Interconnects -EXternal Desktop Applications(eSATA).. 59 Proprietary Serial ATA Disk Arrays 60 5.2.8 Serial ata and sas .60 5. 2. 9 Potential EXternal SATA Incompatibility Issues 5. 2. 10 Mobile Applications 5.2.11 Port Multiplier Example Applications 666 6 Cables and connectors 6.1 Internal cables and connectors .. 6.1.1 nternal Single Lane Description 67 6.1.2 Connector locations 70 6.1.3 Mating interfaces 79 6. 1. 4 Signal cable receptacle connector .83 6.1.5 Signal host plug connector 85 6.1.6 Backplane connector 88 6.1.7 Power cable receptacle connector 91 6.1.8 Internal single lane cable 93 6 Connector labeling 94 6.1.10 Connector and cable assembly requirements and test procedures 94 6.1.11 Internal Multilane cables 98 6.1.12 Mini sata Internal multilane .104 6.2 Internal micro sata Connector for 1. 8 HDD 6.2.1 Usage model .111 6.2.2 General description 111 6.2.3 Connector location 6.2.4 Mating interfaces 114 6.3 Internal slim line cables and connectors .120 Serial ATA revision 3.0 Gold revision page 5 of 663 6.3.1 Usage Models… 120 6.3.2 General description .121 6.3.3 Connector location and keep out zones 12 6.3.4 Mating interfaces 125 6.3.5 Backplane connector configuration and blind- mating tolerance.………….136 63.6 Connector labeling….… 137 6.3.7 Connector and cable assembly requirements and test procedures 137 6.4 Internal LIf-sSAta Connector for 1. 8 HDD 138 64.1 General description 138 6.4.2 Connector locations 国面 139 6.4.3 Mating interfaces 141 Figure 87 defines the interface dimensions for the internal LIF-Sata embedded type connector with both signal and power segments 141 Figure 88 defines the interface dimensions for the internal llF-sata device surface mounting type connector.……… 143 6.4.4 Internal LIF-sSATA pin signal definition and contact mating sequence 145 6.4.5 Housing and contact electrical requirement 146 6.5 External cables and connectors .147 6.5.1 External Single Lane.………… 147 6.5.2 External multilane 157 6.5.3 Mini sata external multilane 6.6 Cable and Connector Electrical Specifications 165 6.6.1 Serial atA Cable 165 66.2 Cable/ Connector Test Methodology.….….….… 166 6.7 Power Segment Pin P11 Definition(Optional) 174 6.7.1 Device Activity Signal .175 6.7.2 Staggered Spin-up Disable Control 177 6.8 Precharge and Device Presence Detection 179 6.8.1 Device Requirements 179 6.8.2 Receptacle Precharge(Informative) .179 resence Detection(Informative).................... 180 Ph y Laye 183 7. 1 Descriptions of phy electrical specifications 183 7.1.1 List of services 83 7.1.2 Low Level Electronics Block Diagrams(Informative) 184 7.1.3 Compliance Testing 191 7.1.4 Link performance 192 7.2 Electrical Specifications. ............................................................................................192 7. 2. 1 Physical Layer Requirements Tables 193 7.2.2 Phy Layer Requirements Details 211 7.2.3 Loopback 227 7.2.4 Test Pattern Requirements 230 7.2.5 Hot Plug considerations 247 7.2.6 Mated Connector pair definition 250 7. 2.7 Compliance Interconnect Channels(Gen1x, Gen 2X, Gen 3i) 251 7.2.8 Impedance Calibration(Optional) 254 7.3 Jitter 255 7.3.1 Jitter definition 256 7.3.2 Reference Clock Definition .256 7.3.3 Spread Spectrum Clocking 258 7.3.4 Jitter Budget 260 7.4 Measurements 260 7.4.1 Frame Error Rate Testing 261 7.4.2 Measurement of Differential Voltage Amplitudes (Gen1, Gen2)........ 264 7.4.3 Measurement of Differential Voltage Amplitudes (Gen 3i) 275 74.4 Rise and fall times 276 Serial ATA revision 3.0 Gold revision page 6 of 663 7.4.5 Transmitter Amplitude .278 7.4.6 Receive Amplitude .279 7.4.7 Long Term Frequency Accuracy 283 7.4.8 Jitter measurements 284 7.4.9 Transmit Jitter(Gen1i, Gen2], Gen1m, Gen2m, Gen1x, and Gen2x).....287 7.4. 10 Transmit Jitter(Gen3i) 289 7.4.11 Receiver Tolerance(Gen li, Gen2i, Gen 1m, Gen2m, Gen1x, and Gen2x)... 290 7.4.12 Receiver Tolerance(Gen3i) 292 7.4.13 Return Loss and Impedance balance .294 74.14 SSC Profile∴ 国面 298 7, 4.15 Intra-Pair Skew 298 7.4.16 Sequencing Transient Voltage .300 7.4.17 AC Coupling Capacitor 301 7. 4.18 TX Amplitude Imbalance .301 7, 4.19 TX Rise/Fall Imbalance 301 7. 4.20 TX AC Common Mode Voltage(Gen 2i, Gen 2m) 302 7. 4.21 TX AC Common Mode Voltage(Gen 3i) .302 74.22 Oob Common mode delta 302 74.23 OoB Differential delta .303 7.4.24 Squelch Detector Tests .303 7.4.25 OOB Signaling Tests .304 7.4.26 TDR Differential Impedance(Gen 1i/ Gen 1 m) .305 7.4.27 TDR Single-Ended Impedance(Gen 1i/Gen1m 74.28 DC Coupled Common Mode Voltage(Gen1i/Gen1m)………307 7. 4.29 AC Coupled Common Mode Voltage(Genli/Gen1m) 308 7. 4.30 Sequencing Transient Voltage-Laboratory Load(Gen3i) .309 7.5 Interface States 309 7.5. 1 Out Of Band signaler 309 7.5.2 dle Bus condition .317 7.6 Elasticity Buffer Management 317 8 OOB and Phy power states 319 8.1 Interface Power states 319 8.2 Asynchronous Signal Recovery(Optional) 319 8.2.1 Unsolicited Comint Usage(Informative) .319 8.3 OOB and Signature FIS return(Informative) 320 8.4 Power-On Sequence State Machine 320 8.4.1 Host phy Initialization state Machine 320 8.4.2 Device phy Initialization state machine 325 84.3 Speed Negotiation…… 329 9 Link Layer…… 335 9.1 Overview .335 9.1.1 Frame Transmission 335 9. 1.2 Frame Reception 335 9.2 Encoding Method 335 9.2.1 Notation and conventions 336 9.2.2 Character Code 337 9.2.3 Transmission Summary 345 9.2.4 Reception Summary .346 9.3 Transmission Overview 1EB面 348 94 Primitives∴ 348 9.4.1 Overview 348 9.4.2 Primitive Descriptions...... 349 Primitive Encoding 350 9.4. 4 DMAT Primitive 351 9.4.5 CONTp Primitive .35 94.6AL|GN。 Primitive 354 Serial ATA revision 3.0 Gold revision page 7 of 663 9.4.7 Flow Control Signaling Latency 354 9.4.8 EXamples of Primitive Usage(Informative) 356 9.5 CRC and Scrambling 358 9.5.1 Relationship Between Scrambling of FIs Data and Repeated Primitives 358 9.5.2 Relationship Between Scrambling and CRC 358 9.5. 3 Scrambling Disable(Informative) 359 9.6 Link Layer State Machine 359 9.6.1 Terms Used in link layer transition tables 359 9.6.2 Link Idle State Diagram 360 9.6.3 Link Transmit State Diagram 国面 363 9.6.4 Link Receive State Diagram 370 9.6.5 Link power Mode State Diagram.…… aaidiiiiididdidiai 376 10 Transport Layer 381 10.1 Overview 38 10.1.1 Fis construction 381 10.1.2 FIS decomposition………… 38 10.2 Frame Information Structure(FIs) .381 10.2.1 Overview 381 10.2.2 Payload content..…………………………382 10.3 FIs Types 382 10.3.1 FIs Type values 382 10.3.2 CR Errors on data fises .383 10.3.3 All FIS types 383 10.3.4 Register-Host to Device 384 10.3.5 Register-Device to Host 386 10.3.6 Set device Bits-Device to host 387 10.3.7 DMA Activate- Device to Host 388 10.3.8 DMA Setup-Device to Host or Host to Device(Bidirectional) 389 10.3.9 BIST Activate-Bidirectional 392 10.3.10 PlO Setup- Device to Host .395 10.3.11 Data- Host to Device or Device to Host (Bidirectional) 397 10.4 Host transport states .399 10.4.1 Host transport idle state diagram 399 10.4.2 Host Transport transmit command Fis diagram 402 10.4.3 Host Transport transmit control FIs diagram……… ..:..:: 403 10.4.4 Host Transport transmit dMa Setup -Device to Host or Host to device FIs state diagram 404 10.4.5 Host Transport transmit bIST Activate Fls.....................405 10.4.6 Host Transport decomposes Register FIs diagram 406 10.4.7 Host Transport decomposes a Set Device Bits Fis state diagram ...................407 10.4.8 Host Transport decomposes a dMA Activate Fis diagram 408 10.4.9 Host Transport decomposes a plo setup fis state diagram 10.4.10 Host T ransport decomposes a DMA Setup FIs state diagram 414 10.4.11 Host transport decomposes a bIST Activate FIs state diagram 415 10.5 Device transport states 416 10.5.1 Device transport idle state diagram 416 10.5.2 Device Transport sends Register- Device to Host state diagram 417 10.5.3 Device Transport sends Set Device Bits FIs state diagram 418 10.5.4 Device Transport transmit PlO Setup- Device to Host FIS state diagram.. 419 10.5.5 Device Transport transmit DMA Activate FIs state diagram .420 10.5.6 Device Transport transmit DMA Setup- Device to Host FIs state diagram..42 10.5.7 Device Transport transmit data- device to Host fis diagram 422 10.5.8 Device T ransport transmit BIST Activate Fis diagram………. 423 10.5. 9 Device Transport decomposes Register- Host to Device state diagram 425 10.5.10 Device Transport decomposes Data(Host to Device)FIs state diagram 426 10.5.11 Device Transport decomposes DMA Setup- Host to Device state diagram.. 427 Serial ATA revision 3.0 Gold revision page 8 of 663 10.5.12 Device Transport decomposes a BIST Activate FIS state diagra .428 11 Device Command Layer protocol 429 Power-on and comreset protocol 面面国面届主 429 11.2 Device Idle protocol 432 11.3 Software reset protocol 437 11.4 EXECUTE DEVICE DIAGNOSTIC command protocol 440 11.5 DEVICE RESET command protocol ..442 11.6 Non-data command protocol 11.7P| o data- in command protoco儿.… 442 443 1.8 PlO data-out command protocol .445 11.9 DMa data in command protocol .446 11.10 DMa data out command protocol 1,,国 .447 11.11 PACKET protoco 448 11.12 READ DMA QUEUED command protoco 454 11.13 WRITE DMA QUEUED command protocol 456 11.14 FPDMA QUEUED command protocol .458 12 Host Command Layer protocol 12.1 FPDMA QUEUED command protocol 465 465 13 Application Layer……… 471 13.1 Parallel ata emulation .471 13.1.1 Software reset 471 13.1.2 Master- only emulation…… .472 13.1.3 Master/Slave emulation(optional) 473 13.2 IDENTIFY(PACKET)DEVICE 国面E国面EB面画 国面国BB国E面 479 13.2.1 DENTIFY DEVICE 479 13.2.2 DENTIFY PACKET DEVICE 487 13.2.3 Determining Support for Serial ATA Features.... 491 13.3 SET FEATURES 492 13.3.1 Enable/Disable Non-Zero Offsets in DMA Setup .492 13.3.2 Enable/Disable DMA Setup FIS Auto-Activate Optimization .492 13.3.3Enable/disabledevice-initiatedinterfacepowerstatetransitionswwwww.493 13.3. 4 Enable/Disable Guaranteed in-Order Data Delivery 493 13.3.5 Enable/Disable asynchronous Notification 493 13.3.6 Enable/Disable Software Settings preservation 493 13.3.7 Enable/disable device automatic Partial to slumber transitions 93 13.4 Device Configuration Overlay. 494 13.4.1 Device Configuration Overlay Identify 494 1342 Device Configuration Overlay Set…… 495 13.5 Software Settings Preservation(Optional) 497 13.5.1 Warm Reboot Considerations(Informative) 498 13.6 Native Command Queuing(Optional) 498 13.6.1 Definition 499 13.6.2 Intermixing Non- Native Queued Commands and Native Queued commands. 503 13.6.3 Command definitions .504 13.6. First-party DMA HBA Support(Informative) 522 13.7 SATA Logs 523 13.7.1 Log Address Definitions 523 13.7.2 General Purpose Log Directory(ooh 523 13.7.3 Queued Error Log(10h) 524 13.7. 4 Phy Event Counters Log(11h) 526 13. 7.5 NCQ Queue Management Log(12h) 526 13.8 Asynchronous Notification(Optional) baaaaaaaa84 527 13.8.1 Set device bits fis notification bit .527 13.8.2 Notification mechanism 527 13.8.3 State Diagram for Asynchronous Notification 527 13.8. 4 ATAPI Notification .528 Serial ATA revision 3.0 Gold revision page 9 of 663 13. 9 Phy Event Counters(Optional) 528 13. 9.1 Counter reset mechanisms .529 139.2 Counter Identifiers 529 13.9.3 Phy Event Counters Log(11h) 532 13. 10 Staggered Spin-up(Optional) ∴533 13.11 Non-512 Byte Sector Size(Informative) 533 13.12 Defect Management (Informative) 534 13.12.1 Overview(Informative .534 13.12.2 Typical Serial ATA Reliability Metrics(Informative) 534 13.12.3 An Overview of Serial ATA Defect Management(Informative) 534 13. 12.4 Continuous Background Defect Scanning(Informative) 535 13. 12.5 Self-Monitoring, Analysis and Reporting Technology(Informative) .535 13.13 Enclosure Services/Management (Optional) 536 13.13.1 Overview .536 13.132 Topology…… 536 13. 13.3 Limitations 面B面画 Ii0000 0 538 13.13.4 Definition .538 13.13.5 SES and saf-te extensions 544 13.13.6 Enclosure services hardware Interface ∴550 13.14 HDD Activity Indication(Optional) 551 13.14. 1 HDD Activity Emulation of Desktop Behavior..... 55 13. 14.2 Activity/Status Indication Reference(Informative) 552 13.15 Port multiplier discovery and enumeration ,,, 555 13.15.1 Power-up………..….….…..…. 555 13.15.2 Resets 556 13.15.3 Software Initialization Sequences(Informative) 557 13. 15.4 Port Multiplier Discovery and Device Enumeration(Informative) 557 13.16 Automatic Partial to slumber transitions .559 14 Host adapter register interface 560 14.1 Status and Control Registers 560 14.1.1 STatus register 561 4.1.2 SError register 6 14.1.3 COntrol register 563 14.1.4 SActive register 564 14.1.5 SNotification register(Optional 565 15 Error handling 567 15.1 Architecture 567 15.2 Phy error handling overview 568 15.2.1 Error detection 568 15.2.2 Error control actions 569 152.3 Error reporting… .570 15.3 Link layer error handling overview 570 15.3.1 Error detection .570 15.3.2 Error control actions ∴570 15.3.3 Error reporting 571 15.4 Transport layer error handling overview 571 15.4.1 Error detection 572 15. 4.2 Error control actions 572 15.4.3 Error reporting .573 15.5 Application layer error handling overview 574 15.5.1 Error detection 574 15.5.2 Error control actions 574 16 Port Multiplier………………… 577 16.1 Introduction .577 16.2 Overview 577 16.3 Definition 578 Serial ATA revision 3.0 Gold revision page 10 of 663 【实例截图】
【核心代码】