SM750 Datasheet_v1.6_20150320

【实例简介】
SM750是SiliconMotion一款带 PCI Express接口的2D多媒体移动显示处理器，封装BGA 265，提供视频加速和2D加速功能。SM750支持范围广泛的I/O，含有模拟RGB和数字LCD面板接口、两个缩放视频接口和脉宽调制（PWM）。SM750提供额外的GPIO接口用于连接各种外围设备。2D引擎包括一个前端色彩空间转化器，提供4:1至1:8硬件缩放。视频引擎支持8位、16位或者32位像素双路视频输出（双显示器），并在每路视频提供3色硬件光标。LCD视频输出支持后台YUV色彩空间转换并支持4:1至1:212比例缩。还包括一个缩放视频捕捉（ZV）端口，可通过额外的电路进行MPE
SiiconMotion SM750 Datasheet Table of contents General Description 1.1 Overview 1.2 Pins 5577 1.2.1 Pin Descriptions 1.2.2 Package Information 12 1.3 Internal block description 13 1.3. 1 PCI Express /nterface... 13 1.3. 2 Display Memory Interface 17 13. 3 Zoom video port .20 1.3. 4 2D Engine 20 1.3.5 Video Displa 21 1.3.6 LCD Panel 26 1.3. 7 Analog RGB(Analog LCD or CRT 1.3.8GPo 1.3. 9 Strap Pin 1.3.10 DMA Controller 31 1.3. 11 Interrupt Controller 1.3.12 Clock Control 1.3.13 Power Management. .34 1.3.14 MMO Space..… 1.4 Standard Vga 36 1. 4.1 Video blos rom interface 1.4.2 Legacy VGA Support. VGA Register ,画t 2.1 Functional overview 37 2.2 VGA Registers .37 2.2. 1 Register Descriptions 2.3 Standard VGA Register................... 2. 4 EXtended VGA Registers System Configuration…,,,,,,,,,,…,……, 70 3.1 Functional overview 70 3.2 Register descriptions 70 3.2. 1 Contiguration 1 Register Descriptions 71 3.2.2 Power Management Register Descriptions 90 3.2. 3 Configuration 2 Register Descriptions 94 PCI Configuration Space…,,…,………,…,…,…,…,…,…,…,…,…,…,…,…,……,101 Register Descripti Drawing Engine ∴115 5.1 Functional overview 115 5.2 Programmers model 115 5.3 Register Descriptions…...,,,… 6.3. 1 2D Drawing Engine Registers 118 5.3.2 Color Space Conversion Registers …133 Display Contro|er.…,…,…, 141 6.1 Programmer's Model :::::: 6.2 Register Descriptions... 142 6.21 Primary Graphics Control Registers….,…… 146 6.2.2 Video Control Registers 157 6.2.3 Video Alpha Contro/ Registers 165 6. 2. 4 Primary Display Cursor Control Registers ,71 6.2.5 Alpha Control Registers.. 174 6.2.6 Secondary Display graphics Contro/ Registers.... 179 6.2.7 Secondary Display Cursor Control Registers 4187 6.2.8 Palette RAM Registe 190 GPIO 194 7.1 Functional overview 194 Revision 1.6 Table of contents SiiconMotion SM750 Datasheet 7.1.1 GP/O Interface 194 7.2 Programmer's Model 7.3 Register Descriptions 7.3. 1 GP/O Register Descriptions 196 12c| nterface…… 207 8.1 Functional overvi 8.2 Register Descriptions 208 9 ZV Port …212 9.1 Functional overview 21 9.1.1 ZV Port Overview 212 9. 1.2 Video Capture Unit Overview 212 9.2 Programmer's model.…..… 1 9.3 Register Descriptions 214 9.3.1 ZV Port 0 Registers 9.3.2 ZV Port 1 Registers. 220 10. DMA Controller(DMAC) 226 10.1 Functional overview 226 10.2 Register Descriptions 228 11. PWM Specification 231 11.1 Functional overview 231 11.1.7 Delay Counter with Interrupt...,…,… 231 11.1.2 Internal Timer with Interrupt 231 11.1.3 Externa/ Pulse 231 11.2 Register Descriptions... 232 12. Specifications.… 236 12.1 Soldering profile 236 12.2 DC Characteristics 237 12.3 AC Timing 12.3. 1 PC/ Express Timing 239 12.3. 2 Display Controller Timing 239 12.3.3 ZV Port Timing 241 13. Packaging Information………,…,……,…,……,…,…,…………,……………………242 13.1 Packaging ..... 13.2 Top Marking 243 14. Product Ordering Information………,…,…,…,…,,…,…,…,………,…,…,………,……,…………,245 Revision 1.6 Table of contents SiiconMotion SM750 Datasheet General Description Overview The SM750 is a PCI Express 2D multimedia mobile display controller device, packaged in a 265- pin BGA. Designed to complement needs for the embedded industry, it provides video and 2D capability. To help reduce system costs, it supports a wide variety of l/O, including analog RGB and digital LCD Panel interfaces, two Zoom Video interfaces, and Pulse width Modulation (PWM). There are additional GPIo bits that can be used to interface to external devices as well The 2D engine includes a front-end color space conversion with 4: 1 and 1: 8 scaling support. The video engine supports two different video outputs(Dual Monitor) at 8-bit, 1 6-bit, or 32-bit per pixel and a 3-color hardware cursor per video output. The LCD panel video pipe supports a back-end YUV color space conversion with 4: 1 and 1: 212 scaling. A Zoom Video(zv)port s also included to interface to external circuitry for MPEG decode or TV input SSP1 PWM Header Zy PORT H eade VGA BIOS Analog (SSPO) CRT LYNX EXPRESS DDR SDRAM sM750 LCD MD31:可 DDR SDRAM PANEL (ND63: 321 (sl164 PCI EXPRESS BUS(x1) Figure 1: System Block Diagram Revision 1.6 5 1. General Description SiiconMotion SM750 Datasheet Features Benefits High Performance and Power Managed 2D Desktop level 2D performance within the power budget of a low power consumption Multiple Display Support Under Major OSs. Applications available at the same time across multiple display devices (CRT1+CRT2, LCD1+LCD2, CRT+LCD) Single chip implementation ideal for various system form factors Dual Digital LCD Support Independent display support for digital LCD displays Dual 18-bit digital LCD outputs Adaptive power Management Reduces average power consumption when in With dynamic functional block power down operation mode and clock control Multiple Independent Hardware Video Independent full screen motion video for Windows separate displays 128-bit Single Clock Cycle Drawing Engine No compromise 2D graphics performance for various system form factors High Performance DDR Memory Interface Delivers up to 1.3GB/s bandwidth with 32-bit memory interface and 2.6GB/s bandwidth with 64-bit memory interface to support multiple display functions and display outputs PCI Express 1.1 x1 Lane Support Provides interface capability for today' s most popular Pc graphic busses Digital LCD Panel Support up to 1920X1440 Supports all panel requirements for various system form factors Dual 300 MHz 24-bit RAMDACs Supports resolutions up to 1920x 1440 for CRT display Supports dual Crt outputs 7 Video Display Layers Provides 7 layers of display frame includes graphics, videos, alphas, and cursors General Purpose l/O Provides programmable l/o for customize applicatio Dual zoom video port Provides support for camera, TV tuner input, or video output from various video decoders Hardware Support LCD Landscape or Portrait Portrait view for desktop publishing,word Rotation processing applications ACPI Compliant Meets WHQL certification requirements Software Support for Microsoft Windows XP, Complete OS software support 2003. 2008. Vista Windows 7 windows ce and various linux Revision 1.6 1. General Description SiiconMotion SM750 Datasheet 12 Pins 1.2.1 Pin Descriptions he following table provides brief description of each bGa ball of the sM750 Signal names with following are active"LoW signals, whereas signal names without following are active HIGH signals. also the following abbreviations are used for pin type I-Input signal O-Output signal 10-Input or Output signal Internal pull-downs for TEST[2: 0] and GPlo31: 0] pads are all 85K-ohm resistors IOL Signal Name Pin Number Type Pad Description Host Interface(8) TX+ TX- A8,B8 DO Differential Out SM750 PCle differential transmit pair RX+.RⅩ A10.B10 Differential In SM750 PCle differential receive paIr REFCLK+ A12,B12 Differential In PCle reference clock REFCLK differential pair REXT D11 MOS 3.3V TBD Required to connect to a 191ohm pull-down resistor RST# C13 CMOS 3.3V PCle fundamental reset Clock Interface (11) PLL AGND B14,B17 PLL analog ground PLL DGND B15,B16 0 PLL digital ground PLLPWR A14 3.3V PLLA analog power PL LLPWR DA A15 3.3V PlLa digital power PLLPWR BC A19 3.3V PLLB and PLLC analog power PLLPWR DBC A18 3.3V PLLB and Pllc digital powe TESTCLK C14 CMO 3.3V For testing purposes XTALIN A17 CMOS 3.3V TBD 14.31818 MHz crystal input connection XTALOUT A16 CMOS 3.3V TBD 14.31818 MHz crystal output connection Test Interface(3) Test mode selection TEST[2: 0 M17.L17.L18 CMOS.3V TBD TEST[2: 0]have weak internal lull-down resistors Revision 1.6 1. General Description SiiconMotion SM750 Datasheet IOL Signal name Pin number Type Pad Description ma Memory Interface (104) BA[1:0 J3.J4 CMOS 2.5V ddR bank address CMoS 25V TBD DDR column address stro CKE CMOS 2.5V TBD DDR clock enable CS# K3 CMOS 2.5V TBD DDR chip select 3,R1,G2 DQM[7:0]# E2,V8,C4, CMOS 2.5V ddR data mask 6,C6 W3.T1.G1 DQs[7:0] E1.W8.c3 CMOS 2.5V TBD ddR data strobe W6,D6 P2,P3,P4, N1,N2,N3 MA12:0 N4,M1,M2, MOs 25V DDR address bus M3,M4,L3, L4 W9,v9,U9, T9. U8. t8 B1,A1,B2 A2,B3,A3 MD[31:0] B4,A4,W7, CMOS 2.5 TBD DDR data bus [31: 0 V7,U7,U6 T6,v5,U5 T5.D5.c5 B5,A5,B6, A6.D7,C7 WV5,W4,V4, U4,W1,W2, V1.V2.U1 U2,U3.T2, T3,T4,R2 MD6332] R3,H2.H3 CMOS 2.5 TBD DDR data bus[63: 32] F1.F2.F3 E4.E3.D4. D3,D1.D2, C1.C2 MVREF[1: 0 P1,H1 1.25V DDR voltage reference RAS#E CMOS 25V BD DDR row address strobe SCK+ SCK K1,L1 CMOS 2.5V TBD ddR differential clock WE# L2 CMOS 2.5V TBd DDR write enable Revision 1.6 1. General Description SiiconMotion SM750 Datasheet IOL Signal name Pin number Type Pad Description ma Flat Panel Interface( 31) BIAS T18 CMOS 3.3V Flat panel voltage bias enable U17,T16, U16.V16 T15,U15, V15.W15. U14,∨14 FP[23:0 U13.V1 CMOS 3.3V TBD Flat panel data bus [23: 01 W13,T12, U12,V12 W12,U11 V11.W11 T10,U10 FP DISP R17 CMOS 3.3V Flat panel display enable FP HSYNC M18 CMOS.3V Flat panel horizontal sync EP VSYNC N18 CMOS 3.3V TBD Flat panel vertical sync FPCLK 6 FPEN T17 o0000 CMoS 3.3V Flat panel pixel clock CMOS 3.3V TBD Flat panel enable VDEN CMOS 33V b Flat panel Vdd enable CRTO Interface(6) BO W19 Analog CRT blue output CRT HSYNC 7 o000 CMOS 3 TBD CRTO horizontal sync CRT VSYNC W17 CMOS 3.3V CRTO vertical sync Go V19 Analog CRTO green output IREFO R19 alog CRTO REF output RO U19 Analog CRTO red output CRT1 Interface(4) B1 N19 Analog CRT1 blue output G1 M19 Analog CRT1 green output IREF 1 J19 CRT1 REF output R1 L19 Analo CRT1 red output Video port Interface 3) VP CLK H19 CMOS 3.3V TBD Video port clock ∨ P HREF F19 CMOS 33V TBD Video port horizontal reference VP VSYNC G19 CMOS 3.3V TBD Video port vertical sync Revision 1.6 1. General Description SiiconMotion SM750 Datasheet Signal Name Pin Number Type IOL Pad Description ma GPIo Interface(32 )-All 32 GP/o pins have weak internal pull-down resistors C18.c17 GP|O[7:0 B19,B18, CMOS 3.3V TBD D16,C16 GPIO[7: 0]/Video Port D[7: 0 D15.C15 F16.E19 GP|o[15:8] E18E17 TBD GPIO[15: 8]/Video Port D19,D18, CMoS 3.3V D[15:8]/FD31:24 GPIO16 F17 CMOS 3.3V BD GPI016/CLKIN/FDSCLK1 GP|o[19:17 G17,G16,F18O CMOS33V GPo[19:17/PwM[20] GPIO20 G18 O CMOS 3.3V TBD GPIO20/SSPO TXD GPIO21 H17 CMOS 3.3V TBD GPIO21/SSPO RXD GPI022 H18 /O CMOS 3.3V TBD GPIO22/SSPO SFOUT GPIO23 J16 mos 3.3V GPI023/SSPO SFIN GPIO24 J17 O CMOS 3.3V TBD GP1O24/ SSPO CLK GPIO25 J18 70 CMOS 3.3V TBD iPI025/SSP1 TXD/FD32 GPIO26 K17 CMos 3.3V GPI026/SSP1 RXD/FD33 GPIO27 L16 CMOS 3.3V GPI027/SSP1 SFOUT/ FD34 GPIO28 N16 CMOS 3.3V GP1O28/ SSP1 SFIN/ FD35 GPIO29 N17 CMOS 3.3V TBD GPI029/ SSP1 CLK GPIO30 P16 CMOS 3.3V TBD GPIO30/IC SCL GPIO31 P17 CMoS 3.3V TBD GP1O31/IC SDA Power and Ground(63) AVDDO W18 12V DACO Analog Power, 1.2V AVDD1 P19 1.2V DAC1 Analog power, 1.2V AVDD T19 3.3V DACO Analog power, 3.3V AVDD3 K19 3.3V DAC1 Analog Power, 3.3v ASSO V18 OV DACO Analog Ground for DDO DAC1 Analog ground for AVSS1 P18 OV AVDD AVSS2 R18 OV DACO Analog Ground for AVDD AVSS3 K18 DAC1 Analog ground for AVDD3 Revision 1.6 10 1. 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【核心代码】