xilinx zynq-7020 官方数据手册

【实例简介】
xilinx zynq7020 软件编程以及硬件开发官方原版最全必备资料。
Date Version Revision 08/08/2012 1.2 Reorganized, clarif ied, and expanded Chapter 19 to include programming models (Cont d)(added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in Chapter 25. Updated table 26-4 in Chapter 26. clarified section 27.3 I/0 Signals in Chapter 27. Added section 28. 1.2 Notices in Chapter 28 Clarified Mapping Summary and updated Table 29-1, Table 29-3, and Table 29-5 in Chapter 29. Added section 30. 1.3 Notices in Chapter 30. Updated data sheet references in section A.3.1 Zynq-7000 AP SoC Documents of Appendix A Updated register database in sections B3 Module Summary through B 34 USB Controller (usb)in Appendix B 10/30/2012 1.3 Changed product name from Extensible Processing Platform(EPP)to All Programmable SoC(AP SoC)throughout document. Added Table 1-1. Added 2.1.1 Notices, 2.4 PS-PL Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in Table 2-2., VREF Source Considerations, updated Table 2-2, and added warning to 2.5.7 MIO Pin Electrical Parameters. Added Initialization of Ll Caches, 3.2.4 Memory Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown by Way Sequence and 3. 9 CPU Initialization Sequence. Added Zynq-7000 AP SoC 7z010 CLG225 Device Notice and expanded table 4-7. updated and expanded tables in 6.3.4 Quad-SPI Boot through 6.3. 13 Post BootROM State, reworked 6.3.6 Debug Status, and added 6.3.13 Post BootROM State and AXI and DMA Done Status Interrupts Reworked Table 7-4. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and Reset. Reorganized and expanded chapter 9, dMa Controller. Added 10.1.3 Notices expanded 10.1.6 Iy0 Signals, added 10.6. 11 DRAM Write Latency Restriction. 10.8. 1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes Added 12.2.4 I/O Mode Considerations and updated 12.3.5 RX/TX FIFO Response to I/O Command sequences Reworked 16.3.3 I/o Configuration added 16.4 ieee 1588 Time Stamping and 16.6.7 Mio Pin Considerations. Added 18.2.7 CANo-to-Can1 Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1 Added Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UARTO-to-UART1 Connection and 19.2. 10 Status and Interrupts, expanded 19.2. 11 Modem Control reworked 19.3 Programming Guide and 19.4.2 Resets Added 20 2.7 12CO-to-12C1 Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and reorganized content of Chapter 21, Programmable Logic Description. Added 25.7.1 Clock Throttle Expanded 26.4.1 PL General Purpose User Resets. Updated register database in sections B 3 Module Summary through B 34 USB Controller(usb) in Appendix B 11/16/2012 1.4 Changed second bullet under NAND Flash Interface from"Up to a 4 GB device"to"Up to a 1 gb device"in Chapter 11, Static Memory Controller Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 Date Version Revision 03/07/2013 1.5 Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application Processing Unit, Chapter 4, System Addresses, and Chapter ct Clarified section 6. 1 Introduction and other sections and added ps Independent jTAG Non-Secure Boot section in Chapter 6, boot and Configuration Made mir clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller, Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in Chapter 12, Quad-SPI Flash Controller Made minor clarifications to Chapter 13, SD/SDIO Controller Made major clarifications/updates to Chapter 14, General Purpose I/O(GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controller. Made minor clarifications to Chapter 16, gigabit ethernet Controller Reworked and expanded Chapter 17 SPI Controller. Made minor clarifications to Chapter 18, CAN Controller, and Chapter 19, UART Controller Made major clarifications/updates to Chapter 20, I2C Controller (added new sections, 20.3 Programmer's Guide, 20.4 System Functions, and 20.5 I/O Interface). Made minor clarifications to chapter 21 Programmable Logic Description and added new sections 21. 1.2 PL Resources by Device Type and 21.1.3 Notices Made minor clarifications to Chapter 22, Programmable Logic Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and expanded Chapter 24, Power Management Made minor clarifications to Chapter 25. Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28, System Test and Debug, and Chapter 29, On-Chip Memory(oCM). Reworked and expanded Chapter 30, XADC Interface Made minor clarifications to Chapter 31, PCI Express Reworked and expanded Chapter 32, Device Secure Boot. Updated Appendix a, Additional Resources. Updated register database in sections B3 Module Summary through B 34 USB Controller(usb)in Appendix B 06/28/2013 1.6 Added icons where applicable. Enhanced first sentence under Quad -SPI Controller in c Clarified first paragraph, added step 2, and clarified step 5 in section 2. 4 PS-PL Voltage Level Shifter Enables. Changed"drive strength"to"slew rate"in section 2.5.7 MIO Pin Electrical Parameters. Added second sentence and updated Table 2-11 in section 2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals. Corrected Note 4 in Table 4-1 and table 4-2. made minor clarifications and added new rsa authentication time section to Chapter 6, Boot and Configuration Made minor clarifications to sections 7.2.2 CPU Private Peripheral Interrupts(PPI)and 7.2.3 Shared Peripheral Interrupts (SPI), and updated Table 7-4 and Table 7-5. Clarified first row in Table 9-12. Added tip to section 10.4.3 Aging Counter, added sentence to Write Leveling, and step 2 in section 10.9.2 Changing Clock Frequencies, and moved section 10.9.6 DDR Power Reduction from Chapter 24, Power Management to this chapter. Added tip to section 11.2.2 Clocks. Added Table 12-8. Added mmc331 standard in formation to section 13.1 Introduction Added step 6 to section 14.3.1 Start-up Sequence, added section 14.3.5 GPIO as Wake-up Event, added second paragraph to 14.4.1 Clocks. Added section 16.7 Known Issues Added note to 17.4.2 Clocks. Changed value of 107 mb to 140 Mb in second sentence under section 21.4 Configuration. Added values for the 7z100 device in Table 21-2 Clarified first paragraph in section 24.2.2 PL Power-down Control and updated Table 24-2. Added note to section 25.6. 1 USB Clocks, clarified second paragraph in section 25. 10.4 PLLs, and added sentence to steps 2 and 3 in Software-Controlled PLL Update section Changed"RESET_REASON"to REBOOT_ STATUS in section 26.2.3 System Software Reset, added section 26.5 Register Overview, deleted first two rows from Table 26-2 and modified last paragraph in section 26.5.1 Persistent Registers. Clarified section 29.1 Introduction, added three paragraphs to Starvation Scenarios section, and added 29. 2.5 Address Mapping heading Corrected spelling of"MCTRL" to"MCTL"in sections 30.4 Programming Guide for the PS-XADC Interface and 307.2 resets Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback 4 UG585(1.10) February23,2015 Date Version Revision 06/28/2013 1.6 Added section 31.5 Root Complex Use Case. Added FIPS standards and clarified section ( Cont' d)32. 1.2 Features, updated configuration file and secure boot process steps in Figure 32-1, added boot time penalty to Power on Reset section, changed"Secure Boot heading to "Secure FSBL Decryption",changed"ROM code"to"OCM ROM Memory"in Figure 32-2 and"ROM to"OCM ROM" in Table 32-3, updated sections 32 2.7 Boot Image and Bitstream Decryption and Authentication, 32. 2.8 HMAC Signature 32 2.9 AES Key Management, 32.3.1 Non-Secure Boot State, 32.3.4 Boot Partition Search, and 32.3.7 Secure Boot Modes of Operation(deleted Table 32-4, Non-secure Boot Options"). Updated register database in sections B3 Module Summary through B34 USB Controller(usb) in Appendix B 02/11/2014 1.7 document(denoted with change bars). Added section 3. 10 Implementation-Detiney F Added 7z015 device, updated device notices and made minor clarifications throughout Configurations. Added sections 5.7 Loopback and 5.8 Exclusive AXI Accesses Reworked Chapter 6, Boot and Configuration. Added section 7. 2. 4 Interrupt Sensitivity, Targeting and Handling. Added sections 8.4.6 Clock Input Option for SWDT and 8.5.6 Clock Input Option for Counter/Timer. Updated section 10.7 Register Overview. Added section 11.7 NOR Flash Bandwidth. Added sections AXI Read Command Processing and 12.2.7 Supported Memory Read and Write Commands. Added section 16.1.4 Clock Domains and reworked section 16.7 Known Issues(previously titled "Limitations Updated section 21.1.2 PL Resources by Device Type and added section 21.3.4 GTP Low-Power Serial Transceivers. Added Peripheral clock gating subsection. Updated Table 26-1 and Table 26-4 Updated register database in sections B 3 Module Summary through B 34 USB Controller(usb)in Appendix b 09116/2014 1.8 Added position information for available device and package combinations for the signals associated with each GT serial transceiver channel to sections 21.3. 3 GTX LoW-Power Serial Transceivers and 213.4 GTP Low-Power Serial Transceivers 09/19/2014 1.8.1 Removed erroneous banner from Chapter 21, Programmable Logic Description Corrected send feedback button clarity issue in footers 11/17/2014 1.9 Added 7z035 device, updated device notices, and made minor clarif ications throughout document(denoted with change bars). 11/19/2014 1.9.1 Corrected document date 02/23/2015 1.10 Added clarification on the timing relationship between PL power up and the PS POR reset signal to section 2.2 Power pins and section 6.3.3 BootROM Performance: PS Por B De-assertion guidelines Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 &A XILINX Table of contents Revision History....... 2 Chapter 1: Introduction 1.1 Overview,,,,,,,,,,,,,,,。,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,26 1.1.1 Block Diagram 27 1.1.2 Documentation resources 28 1.1.3 Notice 30 1.2 Processing System(PS)Features and Descriptions....,......,...... 31 1.2.1 Application Processor Unit (APU) ,,,,31 1.2.2 Memory Interfaces 32 1.2.3 1/o Peripherals 34 1.3 Programmable Logic Features and Descriptions 38 1.4 Interconnect Features and Description...,.......,.......... 39 1.4.1 PS Interconnect based on AXI High Performance datapath switches 39 1.4.2 PS-PL Interfaces 40 1.5 System Software............. 42 Chapter 2: Signals, Interfaces, and Pins 2.1 Introduction ,,,。,,43 2.1.1 Notice 43 2.2 Power pins...,,,,,,,。,,,,。。,,。。,,。,, 45 2.3 PS I/O Pins. 46 2.4 PS-PL Voltage Level Shifter Enables 47 2.5 PS-PL MIO-EMIO Signals and Interfaces...................... 48 2.5.1 1/0 Peripheral (loP) Interface Routing ,,,,,,,,,48 2.5.2 OP Interface Connections ,,49 2.5.3 MIO Pin Assignment Considerations ,,,,,,,,.51 2.5, 4 MIO-at-a-Glance table 53 2.5.5 MIO Signal Routing 54 2.5.6 Default Logic Levels 54 2.5.7 MIO Pin electrical parameters 55 2.6 PS-PL AXI Interfaces 56 2.7 PS-PL Miscellaneous signals ,,,,,,,,56 2.7.1 Clocks and Resets 57 2.7.2 Interrupt Signals 58 2.7.3 Event Signals 58 2.7.4 Idle AXl, DDR Urgent/Arb, SRAM Interrupt Signals .58 2.7.5 DMA Req/Ack Signals...... .......59 2.8 PL l/ O Pins................ 59 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 &A XILINX Chapter 3: Application Processing Unit 3.1 Introduction..,,,,,,,,,,,,,,,,,,,, 61 3. 1.1 Basic Functionality 61 3.1.2 System-Level View 63 3.2 Cortex-A9 Processors,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,65 3.2.1 Summary 65 3.2.2 Central Processing Unit(CPU) 65 3.2.3 Level 1 Caches 重1E 68 3.2.4 Memory ordering ,,71 3.2.5 Memory Management Unit(MMU) ,,,,,,,,,76 3.2.6 interfaces.… ,,,,,,,,,,89 3.2.7 NEON 90 3.2.8 Performance Monitoring Unit 91 3.3 Snoop Control Unit (SCU) ∴...91 3.3.1 Summary .91 3.3.2 Address Filtering 92 3.3.3 SCU Master ports 92 3. 4 L2-Cache 93 3. 4.1 Summary 93 3.4.2 Exclusive L2-L1 Cache Configuration 96 3.4.3 Cache Replacement Strategy 97 3, 4,4 Cache lockdown ,97 3.4.5 Enabling and disabling the L2 Cache Controller 99 3.4.6 RAM Access Latency Control 99 3.4.7 Store Buffer Operation 99 3.4.8 Optimizations Between Cortex-A9 and L2 Controller.,............ 100 3.4.9 Pre-fetching Operation 101 3.4.10 Programming Model ,,,,,,,,,,,,102 3.5 APU Interfaces,,,,,,,,,,,,,,,,,,,,,,, ,,。,。,,,,,104 3.5.1 PL Co-processing Interfaces .,,,,,,,104 3.5.2 Interrupt Interface 107 3.6 Support for trustZone......... ID 108 3.7 Application Processing Unit(APU)Reset......... 108 3.7.1 Reset Functionality 108 3.7.2 APU State After reset 109 3.8 Power considerations,,,,,,,,,,,,,,,,,,,,,,。。,,,,,,, 109 3.8. Introduction 109 3.8.2 Standby Mode 110 3.8.3 Dynamic Clock Gating in the L2 Controller L1 3.9 CPU Initialization Sequence........,.................. 111 3.10 Implementation-Defined Configurations..,..........,....... 112 Chapter 4: System Addresses 4.1 Address Map 。113 4.2 System Bus Maste 115 4.3 SLCR Registers ....,,,..115 4.4 CPU Private Bus Registers...........................116 4.5 SMC Memory n,,。116 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 &A XILINX 4.6 PS I/O Peripherals ,117 4.7 Miscellaneous Ps registers ··。看鲁鲁 n.117 Chapter 5: Interconnect 5.1 Introduction .119 5.11 Features ,,,119 5.1.2 Block Diagram .120 5.1.3 Datapaths 122 5.1, 4 Clock domains 123 5.1.5 Connectivity 126 5.1.6AⅪ|D.. ,,,126 5.1.7 Read/ write Request capability ,,,,,,,,127 5.1.8 Register Overview 127 5.2 Quality of Service(Qos) 128 5.2.1 Basic Arbitration ,,,,,128 5.2.2 Advanced qos 128 5,2.3 DdR Port arbitration..,,,,,,,,,,,,,,,,,,,,,,,,, 129 5.3 AXI HP Interfaces ,,,,129 5.31 Features 129 5.3.2 Block Diagram 130 5.3.3 Functional Description ,131 5.3. 4 Performance 131 5.3.5 Register Overview 132 5.3.6 Bandwidth Management Features 132 5.3.7 Transaction Types ..136 5.3. 8 Command Interleaving and Re-Ordering ,,,,,,136 5.3.9 Performance Optimization Summary 137 5.4 AXI ACP Interface 。138 5.5 AXI GP Interfaces ,.139 5.5.1 Features .139 5.5.2 Performance 139 5.6 PS-PL AXI Interface Signals...... ,,。,139 5.6.1 AXI Signals 139 5.6.2 AXI Clocks and resets 143 5.7 Loopback 144 5.8 Exclusive axl Accesses .145 5.81CPU/L2 ·····.··· ,145 5.8.2 ACP 146 5.8.3 DDRC 146 5.8. 4 System Summary 147 Chapter 6: Boot and configuration 6.1 Introduction 着番·DD。着 ,,,。,149 6. 1.1 PS Hardware Boot stages ...153 6.1.2 PS Software Boot Stages 153 6.1.3 Boot device content 154 6. 1. 4 Boot modes 154 6.1.5 BootRoM Execution 155 6.1.6 FSBL/User Code Execution ,,156 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 &A XILINX 6.1/Pl Boot process 6.1.8 PL Configuration Path 157 6. 1.9 Device Configuration Interface ,,,,159 6. 1.10 Starting Code on Cpu 1 161 6.1.11 Development Environment 161 6.2 Device start. 162 6.2 1 Introducti 162 6.2.2 Power requirements 162 6.2.3 Clocks and plls ,,,163 6.2. 4 Reset Operations ......... 6.2.5 Boot Mode pin settings 6.2.6 l/0 Pin Connections for Boot Devices 167 6.3 BootROM n,,..168 6.3.1 BootroM Flowchart 168 6.3.2 BootROM Header ,171 6.3.3 BootROM Performance 176 6.3.4 Quad-SPl Boot...,,,,,,,,, ,,,,180 6.3.5 NAND Boot,,,,,,,,,, 183 6.3.6 noR Boot 186 6.3.7 SD Card Boot ,,,,,,,,,,,,,188 6.3.8 JTAG Boot 189 6.3.9 Reset Boot and lockdown states ,,,,,193 6.3.10 BootRoM Header search ,,195 6.3.11 MultiBoot 196 6.3.12 BootroM Error codes,,,,,,,,,,,,,,,,, ,,,198 6.3.13 Post bootrom State ......,202 6. 3. 14 Registers Modified by the bootRoM-Examples ,,,204 5.4 Device Boot and Pl Configuration........................ 205 6. 4.1 PL Control via PS Software 206 6.4.2 Boot Sequence EXamples ::· 207 6.4.3 PCAP Bridge to PL 212 6.4.4 PCAP Datapath Configurations 214 6.4.5 PL Control via user-jTAg 218 6.5 Reference section 220 6.5.1 PL Configuration Considerations ,220 6.5.2 Boot time reference 221 6.5.3 Register Overview 223 6. 5, 4 PS Version and device revision 224 Chapter 7: Interrupts 7.1 Environment,,,,,,,,。,。,,,。。,。,。,。, 225 7.1.1 Private, Shared and Software Interrupts ,,,,,,226 7.1.2 Generic Interrupt Controller ( GIC 226 7.1.3 Resets and clocks 226 7.1.4 Block Diagram 226 7.1.5 CPU Interrupt Signal Pass-through 227 7.2 Functional description a· 00 0:aa na-a..- 228 7.2.1 Software Generated Interrupts(SG).,…… 228 7. 2.2 CPU Private Peripheral Interrupts (PPl) 229 7.2.3 Shared Peripheral Interrupts (sPl) 229 7.2.4 Interrupt Sensitivity, Targeting and Handling 231 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 &A XILINX 7.2.5 Wait for Interrupt Event Signal (WFl 233 73 Register overview.....………..233 7.3 1 Write protection lock 234 7.4 Programming Model........... 235 7. 4.1 Interrupt Prioritization ,,,,,235 7.4.2 Interrupt Handling 235 7.4.3 ARM Programming Topics 235 7.4.4 Legacy Interrupts and security Extensions 236 Chapter 8: Timers 8.1 Introduction 237 8.1.1 System Diagram 238 8.1.2 Notices 238 8.2 CPU Private Timers and Watchdog timers.................... 239 8.2.1C|ock 239 8.2.2 Interrupt to ps Interrupt Controller ,,239 8.2.3 Resets..., ,239 8.2.4 Register Overview. 239 8.3 Global Timer GT).............................. 240 8.3.1 Clocking .240 8.3.2 Register Overview 240 8.4 System Watchdog Timer 8. 41 Features 241 8.4.2 block Diag .242 8.4.3 Functional Description ,,,,,,,242 8.4.4 Register Overview.....,,,,,,,,,,,,,,,,,, 243 8.4.5 Programming Mode 8.4.6 Clock Input Option for SWor 244 244 8.4.7 Reset Output Option for SWDT ,,244 8.5 Triple Timer Counters(TTc ··········· 245 8.5.1 Features 245 8.5.2 Block Diagram ,,245 8.5.3 Functional Description .....,,246 8.5.4 Register Overview 247 8.5.5 Programming Model 248 8.5.6 Clock Input Option for Counter /Timer 249 8.6 l/o Signals 250 Chapter 9: DMA Controller 9.1 Introduction 251 9.1.1 Features 252 9.1.2 System Viewpoint 253 9.1.3 Block diagram 254 9.1 4 Notices 256 9.2 Functional description 257 9.2.1 DMA Transfers on the axl interconnect 258 9.2.2 AXI Transaction Considerations 260 9.2.3 DMA Manager. 260 9.2.4 Multi-channel Data FIFO ( MFIFO) ,,,,,,,,262 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(1.10) February23,2015 【实例截图】
【核心代码】