VITA46.0标准

【实例简介】
VITA46.0正式标准。
ANsI/VITA46.02007(R2013) erican Natio American national standard for vPX Baseline standard Secretariat VMEbus International trade association Approved October 2007, Revised May 2013 American National Standards institute. Inc Abstract This standard describes vita 46.0 vPX Baseline standard. an evolutionar step forward for the provision of high-speed interconnects in harsh environment applications American Approval of an American National Standard requires verification y ANSi that the requirements for due process, consensus, and National other criteria for approval have been met by the standards developer Standard Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agreement has been reached by directly and materially affected interests Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that a concerted effort be made toward their resolution The use of American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes,or procedures not conforming to the standards The American National Standards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the american National Standard Institute. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that action be taken periodically to reaffirm, revise, or withdraw this standard Purchases of American National Standards may receive current information on all standard by calling or writing the american National standards institute NoTE- The user's attention is called to the possibility that compliance with this standard may require use of an invention covered by patent rights By publication of this standard, no position is taken with respect to the validity of this claim or of any patent rights in connection therewith. The patent holder has, however filed a statement of willingness to grant a license under these rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license Details may be obtained froin the standards developer Published by VMEbus international frade association PO Box 19658. Fountain Hills. AZ85269 Copyright o 2013 by vmebus International Trade Association All rights reserved No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without prior written permission of the publisher. Printed in the united states of america- r2 0a isbn 1-885731-44-2 ANSIITA 46.0. VPX Baseline Standard Table of contents 1 INTRODUCTION…aaa…………a15 Objectives…....,…, 15 1. 2 VITA 46 Overview 15 Terminology…………,….….….……,…,…….…,.…,,…,….….……..……17 1.3.1 Specification Key Words ∴17 1.3.2 VITA 46 Definitions 18 References 19 2 VITA 46 COMPLIANCE ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ ■■■■■■■■■■日■画■■■■ 21 3 SYSTEM,…,………… 22 3.1 Safety ground 22 3.2 Power supply 3.2.1 Capacity 3.2.2 Voltage Levels 24 3.2.3 Dielectric Separation 27 ystem Controller(SYS_CON)…..,.,,,….…,…,…,…,……………27 3.4 System-wide Connections . 3.4.1 Reference Clock(REF CLK-/- 28 3.4.2 JTAG Pin Allocation 申· 3.4.3 System Management Connections(Optional) 3.4.4 Non-Volatile Memory Read Only(Optional) ·中· 3.45 SYSRESET 3.5 Status Indicators. 3.6 Slot Type Indication………………"…":0 4 COMMON REQUIREMENTS ……31 4.1 Overview,n.1111111131 4.2 Connectors 31 4.3 Form factor and Outline 3 4.4 Alignment and Keying 4.4.1 Background and assumptions 4.4.2 Definitions ·中· *·····中·· 4.4.3 Keying rules... Page 5 ANSIITA 46.0. VPX Baseline Standard Two Level Maintenance 37 4.6 Connector pin definition·P0.…138 4.7 Electrical Budgets for Protocol Standards 4.8 Signal Definition-P0...,…,,… ,40 4.8 Power 4.8.2 Geographical Addressin…… .43 4.8.3 System Controller(SYS CON 43 4.8.4 Reference Clock(Optional) 44 4.8.5 Non-Volatile Memory Read Only(Optional) 45 4.8.6 Reserved for future Use Differential pair Error! bookmark not defined 4.8.7 JTAG Pin allocation( Optional)…… ······················*···:····* 46 4.8.8 System Management Connections(Optional) 46 4.8.93.3VAUX 46 4.8.10 12V AUX(+ and -)(Optional) 47 4.8.11 SYSRESETA ·········· 47 4.8.12 Electrical standards 48 4.9 Connector Pin Definition. Pl →······· 4.9.1 Reserved for Future Use Single-ended Signal …… Error! Bookmark not defined 4.9.2P1VBAT.. 中······· 4.9.3 PI-REF CLK SE 5 3U MODULE ……53 5,1 Overview -3U Module n53 5,2 Connectors-3U Module 53 Alignment and Keying-3U Module . 54 Connector pin Definition -3U Module p2. 5.4 Standard Connector p2 5.4.2 Recommended Location on 3U module for Application-Specific Connector 5 6 6U MODULE n57 6,10 verve……157 6.2 Connectors. 63 Alignment and Keying…… 6. 4 Connector Pin Definition 58 6.4.1C tor p2 ::·:·:·········· 6.4.2 Connector P3 6.4.3 Connector p4 62 6. 44 Connector ps 63 6. 4.5 Connector P6 64 6.4.6 Locations on 6U module for User Defined Application-Specific Connectors 66 ge ANSIITA 46.0. VPX Baseline Standard 7 BACKPLANES ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 67 7,1 Overview 67 7.1. 1 Backplane Dimensions 67 7.1.2 Power Delivery …………·…··… 67 7.1.3 Connector Selection 67 ITA46 slot numbering…………………… 68 7.3 Required connections……,…,…,….….,….,.,….…….….,….….….…,….………69 7.3. 1 Reference Clock(REF CLK-1-) 69 7.3.2 The System Controller and the SYS CON Signal ……………,70 7. 3. 3 Bussed DifFerential Pair. Reserved for Future Use............. Error! Bookmark not defined 7.3.4 JTAG Pin Allocation 7.3.5 System Management Connections…… 72 7.3.6 Non-Volatile Memory Read Onl 73 7.3.73.3VAUX 74 73812VAUX(+and-)........, 74 7.3 9 SYSRESETM 74 7.3.10 PI-RES BUS SE Error! bookmark not defined 7.3.11 P1-REF CLK SE …75 7.3.12 P1-ⅤBAT…… 75 7.4 Backplane Fabric Connections Electrical Requirements. 7.5 Hybrid Backplane . 鲁垂鲁鲁。看 76 7.6 Backplane Pin Mappings( Reference Only)….......….…76 7.7 Five Slot Fabric Full Mesh Backplane Routing(Optional 7.8 Backplane Keying... 79 Preventing damage from backwards plug-in Module Insertion eo . ge 7 ANSIITA 46.0. VPX Baseline Standard List of Figures FIGURE 4-1 CONNECTOR IDENTIFICATION FOR 3U AND 6U MODULES ............................32 FIGURE 4-2 VITA 46 KEYING SYSTEM ,34 FIGURE 7-1: RES BUS+/- BACKPLANE TERMINATION …71 FIGURE 7-3: SINGLE-ENDED PLUG-IN MODULE WAFER TO BACKPLANE PIN MAPPINGS. ..............77 FIGURE 7-4: ODD DIFFERENTIAL PLUG-IN MODULE WAFER TO BACKPLANE PIN MAPPINGS...78 FIGURE -5: EVEN DIFFERENTIAL PLUG-IN MODULE WAFER TO BACKPLANE PIN MAPPINGS.79 FIGURE 7-6: POWER WAFER TO BACKPLANE PIN MAPPINGS 80 FIGURE 7-7 RECOMMENDED PORT CONNECTION SCHEME 88 FIGURE A-13 U AIR COOLED MODULE LAYOUT……93 FIGURE A-2 3U CONDUCTION COOLED LAYOUT .94 FIGURE A-3 6U AIR COOLED LAYOUT 1垂垂 95 FIGURE A-4 6U CONDUCTION COOLED LAYOUT 96 FIGURE A-5 3U CONDUCTION COOLED MODULE END VIEW ,,, …97 FIGURE A-6 6U CONDUCTION COOLED MODULE END VIEW. .................. 98 FIGURE A-73U CHASSIS SIDE WALL FIGurE A-8 CONDUCTION COOLED MODULE SIDE VIEW 100 FIGURE B-1 3U AIR COOLED BACKPLANE, PLAN VIEW.........................101 FIGURE B-2 6U AIR COOLED BACKPLANE, PLAN VIEW. ..............................................................102 FIGUREB-3 3U CONDUCTION COOLED BACKPLANE PLAN VIEW .103 FIGURE B-4 6U CONDUCTION COOLED BACKPLANE, PLAN VIEW ·垂音。·垂垂垂音 104 FIGURE B-5 6U BACKPLANE. END VIEW. ....................................................................................105 FIGURE C-1 3U PCB FABRICATION DRAWING (VIEWED FROM PRIMARY SIDE 106 FIGURE C-2 6UPCB FABRICATION DRAWING( VIEWED FROM PRIMARY SIDE).......107 FIGURE D-1: TOP VIEW OF AIR COOLED CHASSIS SHOWING CORRECT PLUG-IN MODULE INSERTION (TOP MODULE) AND BACKWARDS PLUG-IN MODULE INSERTION(BOTTOM MODULE) 108 FIGURE D-2: CONCEPT FOR"STOPPER COMB FASTENED TO CHASSIS FOR PREVENTING CONNECTOR DAMAGE FROM BACKWARDS AIR COOLED PLUG-IN MODULE INSERTION ................109 FIGURE D-3: CONCEPT FOR HEX STAND-OFF FASTENED TO BACKPLANE. FOR PREVENTING CONNECTOR DAMAGE FROM BACK WARDS AIR COOLED PLUG-IN MODULE INSERTION . .........109 ge 8 ANSIITA 46.0. VPX Baseline Standard List of tables TABLE 4-1 MODULE PO AND P1 CONNECTORS 3 TABLE 4-2 ALIGNMENT AND KEYING MODULE PART NUMBERS FOR PLUG-IN MODULES.... 35 TABLE 4-3 PO UTILITY CONNECTOR 垂.垂。垂 38 TABLE 4-4 PO SIGNAL DEFINITIONS .38 TABLE4-5 POWER WAFER CURRENT RATINGS…………..141 TABLE 4-6 CoMmon P1 PINOUT ··.········.··;······.·..······:······ 51 TABLE 4-7 P1 SIGNAL DEFINITIONS 垂D垂 TABLE 5-1 3U MODULE CONNECTORS 垂·垂垂 54 TABLE 5-2 3U MODULE P2 DIFFERENTIAL PINOUT TABLE5-33 U MODULE P2 SINGLE- ENDED PⅠNOUT… 56 ⅠABLE6-l6 U MODULE CONNECTORS……………………58 TABLE 6-2 6U MODULE P2 DIFFERENTIAL PINOUT 59 TABLE 6-3 6U MODULE P2 SINGLE-ENDED PINOUT TABLE6-46 U MODULE P3 DIFFERENTIAL PINOUT∴… 61 TABLE 6-5 6U MODULE P3 SINGLE-ENDED PINOUT TABLE 6-6 6U MODULE P4 DIFFERENTIAL PINOUT …62 TABLE 6-7 6U MODULE P4 SINGLE-ENDED PINOUT 63 TABLE 6-8 6U MODULE P5 DIFFERENTIAL PINOUT 63 TABLE 6-9 6U MODULE P5 SINGLE-ENDED PINOUT .64 TABLE 6-10 6U MODULE P6 DIFFERENTIAL PINOUT. TABLE 6-11 6U MODULE P6 SINGLE-ENDED PINOUT 65 TABLE 7-1 GEOGRAPHICAL ADDRESS PIN ASSIGNMENTS ·垂音。·垂垂垂音 …69 TABLE Z-2JTAG SIGNALS 72 TABLE 7-3 JO (UTILITY CONNECTOR) BACKPLANE MAPPING 80 TABLE 7-4 J1 DIFFERENTIAL) BACKPLANE MAPPING............81 TABLE7-5J2( DIFFERENTIAL) BACKPLANE MAPPIⅠNG.… 82 TABLE 7-6J2 (SINGLE-ENDED) BACKPLANE MAPPING......82 TABLE7-7J3( DIFFERENTIAL) BACKPLANE MAPPⅠNG…,,,,… 83 TABLE 7-8 J3 (SINGLE-ENDED) BACKPLANE MAPPING TABLE 7-9 J4(DIFFERENTIAL) BACKPLANE MAPPING, 83 84 TABLE7-10J4( SINGLE-ENDED) BACKPLANE MAPPING…,,…,…,… 84 TABLE 7-11 J5 DIFFERENTIAL) BACKPLANE MAPPING 85 TABLE 7-12 J5 (SINGLE-ENDED) BACKPLANE MAPPING........85 TABLE7-13J6( DIFFERENTIAL) BACKPLANE MAPPⅠNG……,…,…,…,…,…,…,…,……86 TABLE 7-14J6(SINGL F-ENDED)BACKPLANE MAPPING. 86 TABLE 7-15 RECOMMENDED PIN MAPPINGS 87 ge ANSIITA 46.0. VPX Baseline Standard △ bstract This standard describes vita 46.0 vpX, an evolutionary step forward for the provision of high spced interconnects in harsh-cnvironment applications Foreword VME has been the de-facto bus standard for Commercial off the Shelf(CoTs)Circuit Card Assemblies since the 1980s. Vme boards have proven to be remarkably capable of evolving to support newer technologies with innovations such as VME Subsystem Bus, PCI Mezzanine Cards(Pmc's) and VME320 However, advances in technologies, particularly in interconnects, have demonstrated the need for an advance in system development. This advance needs to accommodate high speed interconnect, particularly serial interconnects, and higher power delivery in concert with better heat removal This standard addresscs thesc nccds in the context of ieee 1101 form factor modules. Othcr specifications address alternate outlines, such as VITA 48 Because electronics miniaturization is driving the plug-in module lo count, most system interconnects will need Multi-gigabit differential technology Core computing cluster switched fabrics Serial rapidio, Pci express, Hypertransport, Inifiniband or 1OG Ethernet Sufficient ports to enable distributed switching or centralized switching The plethora of high-speed interfaces available for tomorrows plug-in modules include Network interfaces Digital video Mass storage interface FPGA-based inter-board connections Custom sensor interfaces VITA 46 provides an evolutionary roadmap for vme uscrs To leverage the broad spectrum of high-speed interconnect technologies Backward compatibility with VMe bus electrical, software and selected mechanicals Enables heterogeneous architectures which preserve existing investments in COTS-based systems Addresses both 3U and 6U form factors Harsh environment fit designed-in? up front in the standard Rugged air or conduction-cooled form factors High value placed on rear-panel 1O High-speed connector survivability/compliance Connector with ESD protection, and options for handling covers to accommodate 2-level maintenance Page 10 【实例截图】
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