实例介绍
【实例简介】
介绍微波集成电路的各类元器件在基板上的制作，适合于新手，当然多看英文的资料有利于以后的开发，容易入门。
Library of Congress Cataloging-in-Publication Data Ladbrooke, Peter H MMIC design 1. Microwave integrated circuits-Design and construction. 2. Transistor circuits--Design and construction. 3. Gallium arsenide semiconductors To Jo and Abby Title TK7876.L331989 621.38173 88-34959 ISBN0-89006-3141 British Library Cataloging-in-Publication Data Ladbrooke. Peter. H. 1943. MMIC design: GaAs FETs and HEMTs 1. Electronic equipment. Monolithic microwave integrated circuits Design I. Title 621.38173 lSBN0-89006-314-1 C1989 ARTECH HOUSE INC 685 Canton Street Norwood. MA 02062 All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means. electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. International Standard Book Number: 0-89006-314-1 Library of Congress Catalog Card Number: 88-34959 1098765432 Contents Foreword X Acknowledgments Notes on nomenclature, acronyms and useful data List of symbols Chapter 1 Introdu uctIon 1.1 Statement of the problem 1.2 Design approaches 2 1.3 A simple ble 4 7 L4 Yield 15 The role of device physics Chapter 2 MMIC types and chip functions 2.1 Scale of IC fabrication 12 2.2 Applications 12 2.2.1C1 2.2.2 Military 14 2.3 Chip functions 2.4 Example MMICs Chapter3 Overview of passive elements 29 29 3.1 Introduction 3.2 Microstripline 30 3.3 Inductors 34 3.4 Capacitor 4 3.5 Resistors 47 3. 6 The Lange coupler 6.6 Output conductance and other microwave effects of substrate 3.7 Other components 50 current 125 3. 8 Final remarks 6.7 Effect of surface charge, non-uniform doping and gate recess depth Chapter 4 PIN and Schottky diodes 6.8 Series parasitic resistances Rs and Ra and effect on equivalent 138 4.1 Introduction circuit 4.2 Schottky diodes 56 6.8. 1 Source resistance, R. 6.8.2 Drain resistances, Rp and Ra 182 4.3 pin diodes 63 145 4.4 MMIC uses of PIN and Schottky diodes 67 6.9 Gate resistance 6. 10 Geometric cap 146 6. 11 Via-hole inductance Chapter 5 Elementary FET principles 6. 12 GaAs FET noise 156 5. 1 Introduction 69 6.13 Power MMICs 163 5.2 Review of Si JFET operation 70 5.3 Current saturation in the GaAs meSfet 77 5.4 Mechanism of current saturation--summary 82 Chapter 7 High electron mobility transistors 5.5 Essential enhancements 83 7.1 Introduction 189 5.5.1 Si JFET 7.2 Energy band line-up 190 5.5.2 GaAS MESFET 7.3 Physical basis and structure 192 196 5.6 Equivalent circuit of the GaAs MESFET 85 7. 4 Practical HEMT structures 5.7 Concluding remarks 87 7.5 Principal equivalent circuit elements 98 7.6 HEMT noise 201 Chapter 6 MESFETs 7.7 Prospects for HEMT integration 202 91 6.1 Introduction 91 6.2 Brief outline of structure Chapter8 Reverse modeling GaAs MESFETS and HEMTs 205 6.3 Equivalent circuit physical basis 8. 1 Introduction 205 95 6.3.1 Signal delay 95 8.2 Reverse modeling for gate length 205 6.3.2 Charge storage 8.3 Errors in eqns (8.2)and(8.6) 211 6.3.3 Current modulation 8. 4 Extension to HEMTs 6.3. 4 Transconductance delay 110 8. 5 General comments 215 6.4 Intrinsic equivalent circuit 112 8.6 Reverse modeling for channel doping 218 6.4.1 Configuration 112 8.7 Conclusion 219 6.4.2 Voltage dependence of the space-charge layer extension. X 116 Chapter 9 Design limit 6.4.3 Gate strip inductance, ig 12 9.1 Introduction 6. 4.4 Channel, or intrinsic, resistance, R 121 9.2 Limits to small-signal behavior 222 6.4.5 Channel current, ICH 12 9.2.1 Gain, frequency and voltage, and gate length 222 6.4.6 Intrinsic transconductance, gmo 122 9.2.2 Eflect of gatewidth, ZG 225 6.4.7 Gate-channel capacitance, Cge 123 9.2.3 Input and output refiection coefficient 232 6.4.8 Gate-drain capacitance, Cod 123 9.2.4 Maximum Tunable Gain(MTG), MAG, MSG and 6.4.9 Transconductance delay, tgm 124 MUG 242 6.5 Implications for FET design and usage 124 9.3 Limits to large-signal (power) behavior Chapter 10 FETs in amplifiers 259 10.1 Introduction 259 10.2 Amplifier topologies and design principles 261 10.2.1 Reactively matched amplifiers 263 10.2.2 Design of a two-element matching or gain slope Foreword compensation network 268 10.2.3 Lossy matched amplifiers 10.2.4 Feedback amplifiers 279 10.2.5 Distributed amplifiers 287 10.2.6 The matrix amplifier 300 10.2.7 Balanced amplifiers 303 10.3 First trial device synthesis 305 10.4 FET synthesis by reverse modeling 310 10.5 FET synthesis for distributed power amplifiers 312 Circuit design is always a compromise if the device parameters are fixed. In 10.5.1 Power-impedance considerations 313 many current processes the fabrication company concerned prefers to fix the 10.5.2 Frequency considerations 315 device geometry and material parameters giving the circuit designer few 10.5.3 FET synthesis- example 316 degrees of freedom when carrying out his design. Generally the device used is a 10.6 Final remarks 321 compromise between ultra-low noise, broad bandwidth and medium output Chapter 11 Computer-aided design 325 In this book. Peter Ladbrooke suggests that this practice is outdated and 11. 1 Introduction 325 that far better circuit performance could be achieved if each device was 11.2 Sensitivity analysis- basis 327 tailored to meet a specific circuit application, He says this is now possible with 11.3 Application of the Monte Carlo method to yield forecasting 33 recent advances in understanding the factors affecting technology and a 11.4 Uses of yield forecasting knowledge of the relationship between material properties, device geometries 11.5 FET centering 344 and device performance. The author derives quantitative expressions for the 1 1.6 Longer-term developments 346 elements of the equivalent circuit for the transistors and other components from which S parameters can be obtained and from which a circuit design can Chapter 12 Future developments 357 be created While circuit designers might welcome this idea, fabrication technologists Index 365 and production engineers may have other views! Imagine a production process in which almost all geometries and technologies are variable fron mask set to mask set and process run to process run. I can see production controllers blanching at the prospect. However if performance is at a premium it may be the only viable alternative The book covers most MMIC functions giving numerical relationships between key device and processing parameters. The chapters are littered with worked examples of his technique for HEMT and MESFET based technologies. In Chapter 8 the reader is introduced to the concept of reverse modeling and a number of examples are given in which the major fabrication parameters are derived from device electrical characteristics The arguments put forward by the author for his approach are compelling but it will remain to be seen whether or not his revolutionary approach will be accepted, particularly as it cuts across the presently accepted fixed process hilosophy adopted almost universally both in GaAs and silicon technologies However, careful choice of the numerous equations which follow in the text will certainly allow the reader to reverse model his competitors' process and this alone may be enough justification for purchasing this well written and Acknowledgments often controversial book LNL√ James Turner. MBE Plessey Research Caswell Ltd Caswell. November 1988 MMIC design: GaAs FETs and HEMTs is a compilation of many hitherto unpublished results arising from carefully executed FET research programs starting in 1974. Most of this work was done in the University of New South Wales, Sydney, Australia, or with the sponsorship of that organization in Cornell University, Ithaca. USA and at Plessey Research(Caswell), England The support of these organizations. the Radio Research Board of Australia and the Australian Research Grants Committee, must be acknowledged throughout. Advancements in the application of the resultant underlying FET physics has benefitted from the developments undertaken at GEC Research, with the very welcome support of the British Ministry of Defence(Directorate of Components, Valves and Devices). The existence of this book owes much to the efforts of others, spread over many years. Ruey Huang participated in early transport calculations, and helped with the practical realization of 0.7pm FETs at a time when such a capability was far less commonplace than it is now. Trevor Barton wrote the computer simulators which helped structure our thinking around the important physical phenomena occurring in GaAs MESFETS. Continuing financial support for FET physics research through the Radio Research Board of Australia occurred because Bill Williamson. at that time with the Telecom Research Laboratories, believed in it and in its long-term usefulness. Jim Turner and Mike Cardwell, both of Plessey Research( Caswell), offered the opportunity to work on a study of soft breakdown in GaAs FETs which yielded important clues to the structure dependence of breakdown processes Lester Eastman provided the environment and resources necessary to carry out a specific experiment at a time when the investigation could go very little further without such an experiment being done. While at Cornell University Peter Zwicknagl grew most of the layers for the experiment in question and together with Carolyn Lowe, did most of the device fabrication. During this phase. the added assistance of William Schaff (with the provision of DLtS data), of Lovell Camnitz(with E-beam direct writing ), and of Fa (with programming and physics theory )was greatly appreciated vez Najjar It was at Cornell University that I first met Colin Wood who together with Daniel Mc Caughan and Daryl Hooper, was subsequently to support the application of device physics in MMIC engineering within GEC's research Notes on nomenclature laboratories. Steve Ransome, Jonathan Nicholas and Anthony Jacomb-Hood gave excellent practical assistance to a programme of MMIC fault diagnosis acronyms and useful data and correction when it was needed most. Steve Ransome supplied Figure 3.1 Mike Allenson and Brian Taylor, both then at the Royal Signals and Radar Establishment, supported the idea of yield studies based on device physics Ged King, of Marconi Defence Systems, Stanmore, was quick to appreciate the potential of the method and, with the very able assistance of Steve Flynn helped to develop a perspective of it from the all-important end-users point of view. Chaz Caddick kept the effort well supplied with excellent S-parameter In the text, capital letters have been used to indicate differently doped regions measurements on any number of devices and circuits which allowed careful of a semiconductor by ion density rather than free-carrier density. The diagnostic and proving work to be done. Andy Hughes gave assistance with distinction is useful for hot-electron devices such as FETs where, on the one circuit modeling beyond the call of duty, and helped plan the book in its earl hand. injection of excess carriers can readily occur and, on the other. depletion stages, Co-operation with Pieter Abrie over software for power amplifier design provided a useful demonstration of designing FETs and passive of free carriers can equally occur in some parts of the device In cither case. it is most useful to distinguish regions of semiconductor by the way they are doped components concurrently. It is a particular pleasure to acknowledge the work requiring upper case letters)rather than by the free carriers(denoted by lower done with Steve Blight on some of the obscure rate-dependent effects exhibited case letters) they support. To quote an example, we shall talk of Pin diodes by short-channel MESFETs rather than pin diodes James Bridge and Adrian Hill have contributed a great deal by virtue of A bar over a symbol is used throughout to indicate normalized values. in their continuing collaboration and friendship. Some of the figures in this book particular currents or current-related quantities per unit gatewidth, e.g are taken from work done by them. Theirs has also been the task of writing the Ip=120 mA mm software involved in the application of device physics to MMICs The same symbol G, is used for power gain and conductance. The intended Im inclined to believe I've guessed correctly who the reviewers are although meaning for each use should be clear tradition demands they should remain nameless. Their involvement in The symbol yp has been used for inductance to save confusion with length, roviding continuous useful comment as the manuscript evolved is appre pr L, in particular gate length Lg ciated nonetheless. Elaine Peyton prepared all the drawings; her help has been The symbol m, rather than the more familiar I, has been adopted for the especially welcome ideality factor of a Schottky or Pin diode to save confusion with the electron Finally, and perhaps most importantly. I wish to thank my wife Jo-not just density n for the fact that she word-processed the entire manuscript--but for her patience and enduring unselfishness Acronyms CAD computer-aided design CHEMT conventional high electron mobility transistor DBS direct broadcast by satellite ESM electronic support measures EW electronIc warfare FET held effect transistor Gw uided weapo XI HEMT high electron mobility transistor IHEMT inverted high electron mobility transistor LDOS local density of state LEC liquid encapsulated czochralski MIC millimeter-wave monolithic integrated circuit MAG List of symbols maximum available gain MBE molecular beam epitaxy MIC microwave integrated circuit MMIC monolithic microwave integrated circuit MOCVD metal organic chemical vapor deposition MODFET modulation doped field effect transistor MSG maximum stable gain MTG maximum tunable gain MUG maximum unilateral transducer power gain mean radius of loop inductor OMVPE organo-metallic vapor-phase epitaxy number of turns, N, multiplied by the pitch, p PBT permeable base transistor b(x) h of channel opening SATCOMS satellite communications B(TO rate of electron energy loss SDHT selectively doped heterjunction transistor B imaginary part of input admittance SPDT single-pole, double throw B imaginary part of load admittance TGSM terminally-guided sub-munition velocity of light in free space TEGFET two-dimensional electron gas FET capacitance: Linville stability factor 2-DEG two-dimensional electron gas capacitance per unit length TEM transverse electromagnetic capacitance per drain-line section VGF vertical gradient freeze total capacitance per unit length of drain line VPE vapor phase epitaxy capacitance per gate-line section VSWR voltage standing wave ratio total capacitance per unit length of gate line C geometric capacitance, drain pad to back plane Useful data drain-source capacitance involving field in layer geometric capacitance, gate-drain, air path 3×108ms-1 C gate-channel space-charge capacitance kT 0.026 V at room temperature gate-drain space-charge capacitance 9.1×10-31kg 1.6×10-19C gascon total gate-drain geometric capacitance q geometric capacitance,, gate-source, air path 10 1.15×10-10CV gate-source geometric capacitar E E-Eo×3 x for Al Ga1-As geometric capacitance, gate pad to back plane 8854×10-42CV-m geometric capacitance, gate pad to drain pad 4×10-Hm tric capacitance, gate pad to sour space charge capacitance of region I space-charge capacitance of regions II-Iml output capacitance of FET or HEMT OFF of-state capacitance of diode arasitic, or geometrIc, capacita equivalent series input capacitance of FET or HEMT general height or spacing d depletion depth; spacing of capacitor plates H vector magnetic field depth of depletion for forward gate voltage small-signal current D spacing between co-planar electrodes small-signal drain current virtual drain total instantaneous value of drain current area density of occupied surface states mean-squared value of drain noise current DEEEEE8 electric field DTOT total small-signal current in dummy load vector electric field small-signal gate current longitudinal field in FET channel small-signal output current transverse field in FEt channel OTOT total small-signal output current breakdown electric field small-signal source current total energy of an electron dc current electron energy at the conduction band edge channel current CH electron energy at the valence band edge CH channel current per unit gatewidth 6△06。0 conduction-band oHset at a heterojunction dc value of drain current frequency; function or functional dependence drain current with gate shorted to source bandwidth, or upper frequency limit IDs value of Ipss per unitgatewidth cut-of frequency of lumped line drain current for forward gate bias maximum frequency oscillation, frequency at which value of F per unit gatewidth power gain of FET or HEMT falls to unit reverse saturation current in an ideal diode resonant frequency SUBS substrate current transition frequency, frequency at which current gain or SUBS SUBS CH FET or HEMT falls to unity J current density small-signal value of feedback conductance k Boltzmanns constant g microwave value of transconductance K constant g Intrinsic microwave transconductance K Fukui noise constant gmo value of gmo per millimeter of gatewidth microwave output conductance of FET or HEMT L.gth of microstrip in a drain-line section length of microstrip in a gate-line section conductance: gair length G power gain from generator to output D Debye length small-signal current gain cles efective electrical gate length real part of input admittance gLLLLL metallurgical gate length real part of load admittance gate-drain spacing Gus large-signal power gain source-gate spacing small-signal power gain of FET or HEMT inductance GGGGGG small-signal power gain of power amplifier inductance per unit length transducer power gain drain series inductance: microstrip inductance per unit unilateral transducer power gain length in drain artificial line small-signal voltage gain total inductance per unit length of drain line operating power gain gate series inductance: microstrip inductance per unit Gw-MAX maximum operating power gain, equal IO MAG length in gate artificial line substrate thick ness total inductance per unit length of gate line xvIll XIX 【实例截图】
【核心代码】
介绍微波集成电路的各类元器件在基板上的制作，适合于新手，当然多看英文的资料有利于以后的开发，容易入门。
Library of Congress Cataloging-in-Publication Data Ladbrooke, Peter H MMIC design 1. Microwave integrated circuits-Design and construction. 2. Transistor circuits--Design and construction. 3. Gallium arsenide semiconductors To Jo and Abby Title TK7876.L331989 621.38173 88-34959 ISBN0-89006-3141 British Library Cataloging-in-Publication Data Ladbrooke. Peter. H. 1943. MMIC design: GaAs FETs and HEMTs 1. Electronic equipment. Monolithic microwave integrated circuits Design I. Title 621.38173 lSBN0-89006-314-1 C1989 ARTECH HOUSE INC 685 Canton Street Norwood. MA 02062 All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means. electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. International Standard Book Number: 0-89006-314-1 Library of Congress Catalog Card Number: 88-34959 1098765432 Contents Foreword X Acknowledgments Notes on nomenclature, acronyms and useful data List of symbols Chapter 1 Introdu uctIon 1.1 Statement of the problem 1.2 Design approaches 2 1.3 A simple ble 4 7 L4 Yield 15 The role of device physics Chapter 2 MMIC types and chip functions 2.1 Scale of IC fabrication 12 2.2 Applications 12 2.2.1C1 2.2.2 Military 14 2.3 Chip functions 2.4 Example MMICs Chapter3 Overview of passive elements 29 29 3.1 Introduction 3.2 Microstripline 30 3.3 Inductors 34 3.4 Capacitor 4 3.5 Resistors 47 3. 6 The Lange coupler 6.6 Output conductance and other microwave effects of substrate 3.7 Other components 50 current 125 3. 8 Final remarks 6.7 Effect of surface charge, non-uniform doping and gate recess depth Chapter 4 PIN and Schottky diodes 6.8 Series parasitic resistances Rs and Ra and effect on equivalent 138 4.1 Introduction circuit 4.2 Schottky diodes 56 6.8. 1 Source resistance, R. 6.8.2 Drain resistances, Rp and Ra 182 4.3 pin diodes 63 145 4.4 MMIC uses of PIN and Schottky diodes 67 6.9 Gate resistance 6. 10 Geometric cap 146 6. 11 Via-hole inductance Chapter 5 Elementary FET principles 6. 12 GaAs FET noise 156 5. 1 Introduction 69 6.13 Power MMICs 163 5.2 Review of Si JFET operation 70 5.3 Current saturation in the GaAs meSfet 77 5.4 Mechanism of current saturation--summary 82 Chapter 7 High electron mobility transistors 5.5 Essential enhancements 83 7.1 Introduction 189 5.5.1 Si JFET 7.2 Energy band line-up 190 5.5.2 GaAS MESFET 7.3 Physical basis and structure 192 196 5.6 Equivalent circuit of the GaAs MESFET 85 7. 4 Practical HEMT structures 5.7 Concluding remarks 87 7.5 Principal equivalent circuit elements 98 7.6 HEMT noise 201 Chapter 6 MESFETs 7.7 Prospects for HEMT integration 202 91 6.1 Introduction 91 6.2 Brief outline of structure Chapter8 Reverse modeling GaAs MESFETS and HEMTs 205 6.3 Equivalent circuit physical basis 8. 1 Introduction 205 95 6.3.1 Signal delay 95 8.2 Reverse modeling for gate length 205 6.3.2 Charge storage 8.3 Errors in eqns (8.2)and(8.6) 211 6.3.3 Current modulation 8. 4 Extension to HEMTs 6.3. 4 Transconductance delay 110 8. 5 General comments 215 6.4 Intrinsic equivalent circuit 112 8.6 Reverse modeling for channel doping 218 6.4.1 Configuration 112 8.7 Conclusion 219 6.4.2 Voltage dependence of the space-charge layer extension. X 116 Chapter 9 Design limit 6.4.3 Gate strip inductance, ig 12 9.1 Introduction 6. 4.4 Channel, or intrinsic, resistance, R 121 9.2 Limits to small-signal behavior 222 6.4.5 Channel current, ICH 12 9.2.1 Gain, frequency and voltage, and gate length 222 6.4.6 Intrinsic transconductance, gmo 122 9.2.2 Eflect of gatewidth, ZG 225 6.4.7 Gate-channel capacitance, Cge 123 9.2.3 Input and output refiection coefficient 232 6.4.8 Gate-drain capacitance, Cod 123 9.2.4 Maximum Tunable Gain(MTG), MAG, MSG and 6.4.9 Transconductance delay, tgm 124 MUG 242 6.5 Implications for FET design and usage 124 9.3 Limits to large-signal (power) behavior Chapter 10 FETs in amplifiers 259 10.1 Introduction 259 10.2 Amplifier topologies and design principles 261 10.2.1 Reactively matched amplifiers 263 10.2.2 Design of a two-element matching or gain slope Foreword compensation network 268 10.2.3 Lossy matched amplifiers 10.2.4 Feedback amplifiers 279 10.2.5 Distributed amplifiers 287 10.2.6 The matrix amplifier 300 10.2.7 Balanced amplifiers 303 10.3 First trial device synthesis 305 10.4 FET synthesis by reverse modeling 310 10.5 FET synthesis for distributed power amplifiers 312 Circuit design is always a compromise if the device parameters are fixed. In 10.5.1 Power-impedance considerations 313 many current processes the fabrication company concerned prefers to fix the 10.5.2 Frequency considerations 315 device geometry and material parameters giving the circuit designer few 10.5.3 FET synthesis- example 316 degrees of freedom when carrying out his design. Generally the device used is a 10.6 Final remarks 321 compromise between ultra-low noise, broad bandwidth and medium output Chapter 11 Computer-aided design 325 In this book. Peter Ladbrooke suggests that this practice is outdated and 11. 1 Introduction 325 that far better circuit performance could be achieved if each device was 11.2 Sensitivity analysis- basis 327 tailored to meet a specific circuit application, He says this is now possible with 11.3 Application of the Monte Carlo method to yield forecasting 33 recent advances in understanding the factors affecting technology and a 11.4 Uses of yield forecasting knowledge of the relationship between material properties, device geometries 11.5 FET centering 344 and device performance. The author derives quantitative expressions for the 1 1.6 Longer-term developments 346 elements of the equivalent circuit for the transistors and other components from which S parameters can be obtained and from which a circuit design can Chapter 12 Future developments 357 be created While circuit designers might welcome this idea, fabrication technologists Index 365 and production engineers may have other views! Imagine a production process in which almost all geometries and technologies are variable fron mask set to mask set and process run to process run. I can see production controllers blanching at the prospect. However if performance is at a premium it may be the only viable alternative The book covers most MMIC functions giving numerical relationships between key device and processing parameters. The chapters are littered with worked examples of his technique for HEMT and MESFET based technologies. In Chapter 8 the reader is introduced to the concept of reverse modeling and a number of examples are given in which the major fabrication parameters are derived from device electrical characteristics The arguments put forward by the author for his approach are compelling but it will remain to be seen whether or not his revolutionary approach will be accepted, particularly as it cuts across the presently accepted fixed process hilosophy adopted almost universally both in GaAs and silicon technologies However, careful choice of the numerous equations which follow in the text will certainly allow the reader to reverse model his competitors' process and this alone may be enough justification for purchasing this well written and Acknowledgments often controversial book LNL√ James Turner. MBE Plessey Research Caswell Ltd Caswell. November 1988 MMIC design: GaAs FETs and HEMTs is a compilation of many hitherto unpublished results arising from carefully executed FET research programs starting in 1974. Most of this work was done in the University of New South Wales, Sydney, Australia, or with the sponsorship of that organization in Cornell University, Ithaca. USA and at Plessey Research(Caswell), England The support of these organizations. the Radio Research Board of Australia and the Australian Research Grants Committee, must be acknowledged throughout. Advancements in the application of the resultant underlying FET physics has benefitted from the developments undertaken at GEC Research, with the very welcome support of the British Ministry of Defence(Directorate of Components, Valves and Devices). The existence of this book owes much to the efforts of others, spread over many years. Ruey Huang participated in early transport calculations, and helped with the practical realization of 0.7pm FETs at a time when such a capability was far less commonplace than it is now. Trevor Barton wrote the computer simulators which helped structure our thinking around the important physical phenomena occurring in GaAs MESFETS. Continuing financial support for FET physics research through the Radio Research Board of Australia occurred because Bill Williamson. at that time with the Telecom Research Laboratories, believed in it and in its long-term usefulness. Jim Turner and Mike Cardwell, both of Plessey Research( Caswell), offered the opportunity to work on a study of soft breakdown in GaAs FETs which yielded important clues to the structure dependence of breakdown processes Lester Eastman provided the environment and resources necessary to carry out a specific experiment at a time when the investigation could go very little further without such an experiment being done. While at Cornell University Peter Zwicknagl grew most of the layers for the experiment in question and together with Carolyn Lowe, did most of the device fabrication. During this phase. the added assistance of William Schaff (with the provision of DLtS data), of Lovell Camnitz(with E-beam direct writing ), and of Fa (with programming and physics theory )was greatly appreciated vez Najjar It was at Cornell University that I first met Colin Wood who together with Daniel Mc Caughan and Daryl Hooper, was subsequently to support the application of device physics in MMIC engineering within GEC's research Notes on nomenclature laboratories. Steve Ransome, Jonathan Nicholas and Anthony Jacomb-Hood gave excellent practical assistance to a programme of MMIC fault diagnosis acronyms and useful data and correction when it was needed most. Steve Ransome supplied Figure 3.1 Mike Allenson and Brian Taylor, both then at the Royal Signals and Radar Establishment, supported the idea of yield studies based on device physics Ged King, of Marconi Defence Systems, Stanmore, was quick to appreciate the potential of the method and, with the very able assistance of Steve Flynn helped to develop a perspective of it from the all-important end-users point of view. Chaz Caddick kept the effort well supplied with excellent S-parameter In the text, capital letters have been used to indicate differently doped regions measurements on any number of devices and circuits which allowed careful of a semiconductor by ion density rather than free-carrier density. The diagnostic and proving work to be done. Andy Hughes gave assistance with distinction is useful for hot-electron devices such as FETs where, on the one circuit modeling beyond the call of duty, and helped plan the book in its earl hand. injection of excess carriers can readily occur and, on the other. depletion stages, Co-operation with Pieter Abrie over software for power amplifier design provided a useful demonstration of designing FETs and passive of free carriers can equally occur in some parts of the device In cither case. it is most useful to distinguish regions of semiconductor by the way they are doped components concurrently. It is a particular pleasure to acknowledge the work requiring upper case letters)rather than by the free carriers(denoted by lower done with Steve Blight on some of the obscure rate-dependent effects exhibited case letters) they support. To quote an example, we shall talk of Pin diodes by short-channel MESFETs rather than pin diodes James Bridge and Adrian Hill have contributed a great deal by virtue of A bar over a symbol is used throughout to indicate normalized values. in their continuing collaboration and friendship. Some of the figures in this book particular currents or current-related quantities per unit gatewidth, e.g are taken from work done by them. Theirs has also been the task of writing the Ip=120 mA mm software involved in the application of device physics to MMICs The same symbol G, is used for power gain and conductance. The intended Im inclined to believe I've guessed correctly who the reviewers are although meaning for each use should be clear tradition demands they should remain nameless. Their involvement in The symbol yp has been used for inductance to save confusion with length, roviding continuous useful comment as the manuscript evolved is appre pr L, in particular gate length Lg ciated nonetheless. Elaine Peyton prepared all the drawings; her help has been The symbol m, rather than the more familiar I, has been adopted for the especially welcome ideality factor of a Schottky or Pin diode to save confusion with the electron Finally, and perhaps most importantly. I wish to thank my wife Jo-not just density n for the fact that she word-processed the entire manuscript--but for her patience and enduring unselfishness Acronyms CAD computer-aided design CHEMT conventional high electron mobility transistor DBS direct broadcast by satellite ESM electronic support measures EW electronIc warfare FET held effect transistor Gw uided weapo XI HEMT high electron mobility transistor IHEMT inverted high electron mobility transistor LDOS local density of state LEC liquid encapsulated czochralski MIC millimeter-wave monolithic integrated circuit MAG List of symbols maximum available gain MBE molecular beam epitaxy MIC microwave integrated circuit MMIC monolithic microwave integrated circuit MOCVD metal organic chemical vapor deposition MODFET modulation doped field effect transistor MSG maximum stable gain MTG maximum tunable gain MUG maximum unilateral transducer power gain mean radius of loop inductor OMVPE organo-metallic vapor-phase epitaxy number of turns, N, multiplied by the pitch, p PBT permeable base transistor b(x) h of channel opening SATCOMS satellite communications B(TO rate of electron energy loss SDHT selectively doped heterjunction transistor B imaginary part of input admittance SPDT single-pole, double throw B imaginary part of load admittance TGSM terminally-guided sub-munition velocity of light in free space TEGFET two-dimensional electron gas FET capacitance: Linville stability factor 2-DEG two-dimensional electron gas capacitance per unit length TEM transverse electromagnetic capacitance per drain-line section VGF vertical gradient freeze total capacitance per unit length of drain line VPE vapor phase epitaxy capacitance per gate-line section VSWR voltage standing wave ratio total capacitance per unit length of gate line C geometric capacitance, drain pad to back plane Useful data drain-source capacitance involving field in layer geometric capacitance, gate-drain, air path 3×108ms-1 C gate-channel space-charge capacitance kT 0.026 V at room temperature gate-drain space-charge capacitance 9.1×10-31kg 1.6×10-19C gascon total gate-drain geometric capacitance q geometric capacitance,, gate-source, air path 10 1.15×10-10CV gate-source geometric capacitar E E-Eo×3 x for Al Ga1-As geometric capacitance, gate pad to back plane 8854×10-42CV-m geometric capacitance, gate pad to drain pad 4×10-Hm tric capacitance, gate pad to sour space charge capacitance of region I space-charge capacitance of regions II-Iml output capacitance of FET or HEMT OFF of-state capacitance of diode arasitic, or geometrIc, capacita equivalent series input capacitance of FET or HEMT general height or spacing d depletion depth; spacing of capacitor plates H vector magnetic field depth of depletion for forward gate voltage small-signal current D spacing between co-planar electrodes small-signal drain current virtual drain total instantaneous value of drain current area density of occupied surface states mean-squared value of drain noise current DEEEEE8 electric field DTOT total small-signal current in dummy load vector electric field small-signal gate current longitudinal field in FET channel small-signal output current transverse field in FEt channel OTOT total small-signal output current breakdown electric field small-signal source current total energy of an electron dc current electron energy at the conduction band edge channel current CH electron energy at the valence band edge CH channel current per unit gatewidth 6△06。0 conduction-band oHset at a heterojunction dc value of drain current frequency; function or functional dependence drain current with gate shorted to source bandwidth, or upper frequency limit IDs value of Ipss per unitgatewidth cut-of frequency of lumped line drain current for forward gate bias maximum frequency oscillation, frequency at which value of F per unit gatewidth power gain of FET or HEMT falls to unit reverse saturation current in an ideal diode resonant frequency SUBS substrate current transition frequency, frequency at which current gain or SUBS SUBS CH FET or HEMT falls to unity J current density small-signal value of feedback conductance k Boltzmanns constant g microwave value of transconductance K constant g Intrinsic microwave transconductance K Fukui noise constant gmo value of gmo per millimeter of gatewidth microwave output conductance of FET or HEMT L.gth of microstrip in a drain-line section length of microstrip in a gate-line section conductance: gair length G power gain from generator to output D Debye length small-signal current gain cles efective electrical gate length real part of input admittance gLLLLL metallurgical gate length real part of load admittance gate-drain spacing Gus large-signal power gain source-gate spacing small-signal power gain of FET or HEMT inductance GGGGGG small-signal power gain of power amplifier inductance per unit length transducer power gain drain series inductance: microstrip inductance per unit unilateral transducer power gain length in drain artificial line small-signal voltage gain total inductance per unit length of drain line operating power gain gate series inductance: microstrip inductance per unit Gw-MAX maximum operating power gain, equal IO MAG length in gate artificial line substrate thick ness total inductance per unit length of gate line xvIll XIX 【实例截图】
【核心代码】
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