Verilog-IEEE Std 1364 -2005 IEEE Standard

【实例简介】
Verilog的IEEE标准，比较新的一个吧应该是
IEEE Std 1364 TM-2005 (Revision of IEEE Std 1364-2001) lEE Standard for Verilog Hardware Description Language Sponsor Design Automation Standards Committee of the IEEE Computer Society Abstract: The Verilog hardware description language(HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Be cause it is both machine-readable and human-readable, it supports the development, verification synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language Keywords: computer, computer languages, digital systems, electronic systems, hardware, hard ware description languages, hardware design, HDL, PLI, programming language interface, Verilog, Verilog HDL, verilog Pll The Institute of Electrical and Electronics Engineers, Inc 3 Park Avenue. New york. NY 10016-5997 USA Copyright@ 2006 by the Institute of Electrical and Electronics Engineers, Inc All rights reserved Published 7 April 2006. Printed in the United states of America IEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and Electronics Engineers, Incorporated Verilog is a registered trademark of Cadence Design Systems, Inc Print:|sBN0-738148504SH95395 PDF SBN0-7381-48512SS95395 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. IEEE Standards documents are developed within the IEee Societies and the Standards Coordinating Committees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standards through a consensus development process, approved by the american National Standards Institute, which brings together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are not necessarily members of the Institute and serve without compensation. While the ieee administers the process and establishes rules to promote fairness in the consensus development process, the ieee does not independently evaluate, test, or verify the accuracy of any of the information contained in its standards. Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property or other damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or indirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard document The ieee does not warrant or represent the accuracy or content of the material contained herein, and expressly disclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a spe cific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standards documents are supplied "AS Is The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure purchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change brought about through developments in the state of the art and comments received from users of the standard Every IeeE Standard is subjected to review at least every five years for revision or reaffirmation. When a document is more than five years old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some value do not wholly reflect the present state of the art. Users are cautioned to check to determine that they have the latest edition of any IEEE Standard In publishing and making this document available, the IEeE is not suggesting or rendering professional or other ervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any duty other person or entity to another. Any person utilizing this, and any other ieee Standards document, should rel upon the advice of a competent professional in determining the exercise of reasonable care in any given circumstances Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to specific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiate action to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason, IEEE and the members of its societies and standards coordinating committees are not able to provide an instant response to interpretation requests except in those cases where the matter has previously received formal consideration. At lectures, symposia, seminars, or educational courses, an individual presenting information on IEee standards shall make it clear that his or her views should be considered the personal views of that individua rather than the formal position, explanation, or interpretation of the Ieee Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil- iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of text together with appropriate supporting comments Comments on standards and requests for interpretations should addressed to IEEE-SA Standards Board 445 Hoes lane Piscataway, NJ 08854 USA NoTE-Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEf shall not be responsible for identifying patents for which a license may be required by an ieee standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Insti tute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright Clearance Center. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service 222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi- idual standard for educational classroom use can also be obtained through the Copyright Clearance Center Introduction This introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description Language The Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 1364 1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis and synthesis. It is because of these rich features that verilog has been accepted to be the language of choice by an overwhelming number of integrated circuit(IC)designers Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in which expressions of both variables and nets can continuously drive values onto nets, provide the basic structural construct. Procedural assignments, in which the results of calculations involving variable and net values can be stored into variables, provide the basic behavioral construct. a design consists of a set of mod ules, each of which has an input/output(1/O)interface, and a description of its function, which can be struc tural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets The Verilog language is extensible via the programming language interface(PLI)and the verilog proce dural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to access information contained in a Verilog hdl description of the design and facilitates dynamic interaction with simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation and computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, and annotators The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer sity in England under a contract to produce a test generation system for the British Ministry of Defense hiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simulation, timing analysis, fault simulation, and test generation In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board of Directors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeE working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as IEEE Std 1364-1995 After the standardization process was complete, the IEEe P1364 Working Group started looking for feed back from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001 With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify outstanding issues with the language as well as ideas for possible enhancements. As Accellera began work- ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led to incompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was estab lished as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution of such issues. The result of this collaborative work is this standard ieee Std 1364-2005 Copyright C 2006 IEEE. All rights reserved Notice to users Errata Errata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan- dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errata periodica Interpretations CurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/ Index. html Patents Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEee shall not be responsible for identifying patents or patent applications for which a license may be required to implement an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention Participants At the time this standard was completed, the ieee P1364 Working group had the following membership Johny Srouji, IBM, IEEE SyStem verilog Working Group chair Tom Fitzpatrick, Mentor Graphics Corporation, Chair Neil Korpusik, Sun Microsystems, Inc, Co-chair Stuart sutherland sutherland hdl inc. editor Shalom Bresticker, Intel Corporation, Editor through February 2005 The Errata Task Force had the following membership Karen p ynopsys, r Kurt baty. WFSDB Consultin Dennis marsa. Xilinx Stefen Boyd, Boyd Technology Francoise Martinolle, Cadence Design Systems, Inc Shalom Bresticker, Intel Corporation Mike McNamara, Verisity, Ltd Dennis Brophy, Mentor Graphics Corporation Don Mills, LCDM Engineering Cliff Cummings, Sunburst Design, Inc Anders nordstrom, Cadence Design Systems, Inc Charles dawson, Cadence Design Systems, Inc Karen Pieper, Synopsys, Inc Tom Fitzpatrick, Mentor Graphics Corpo Brad Pierce, Synopsys, Inc Ronald goodstein, first shot Logic simulation and Steven Sharp Cadence Design Systems, Inc Alec Stanculescu. Fintronic USA Inc Design Stuart Sutherland. Sutherland HDL Inc Mark Hartog, Synopsys inc Gordon Vreugdenhil, Mentor Graphics Corporation James Markevitch, Evergreen Technology Group Jason Woolf, Cadence design Systems, Inc Copyright C 2006 IEEE. All rights reserved The behavioral Task Force had the following membership: Steven Sharp, Cadence Design Systems, InC, Chair Kurt Baty, WFSDB Consulting Jay lawrence. Cadence design Systems. Inc Stefen Boyd, Boyd Technology Francoise Martinolle, Cadence Design Systems, Inc Shalom Bresticker, Intel Corporation Kathryn McKinley, Cadence Design Systems, Inc Dennis brophy, Mentor graphics corporation Michael mcnamara. Verisity Ltd Cliff Cummings, Sunburst Design, Inc Don Mills, LCDM Engineering Steven Dovich, Cadence Design Systems, Inc Mehdi Mohtashemi, Synopsys, Inc Tom Fitzpatrick, Mentor Graphics Corporation Karen Pieper, Synopsys, Inc Ronald Goodstein, First Shot Logic Simulation and Brad Pierce, Synopsys, Inc Design Dave Rich, Mentor Graphics Corporation Keith Gover, Mentor Graphics Corporation Steven Sharp, Cadence Design Systems, Inc Mark Hartoog, Synopsys, Inc Alec Stanculescu. Fintronic USA Ennis Hawk, Jeda Technologies Stuart Sutherland. Sutherland hdl. Inc Atsushi kasuya, Jcda Technologics Gordon Vrcugdcnhil, Mentor Graphics Corporation The PLI Task Force had the following membership Charles Dawson, Cadence Design Systems, Inc, Chair Ghassan Khoory, Synopsys, Inc Co-chair Tapati Basu, Synopsys, Inc Michael rohleder. Freescale Semiconductor. Inc Steven Dovich, Cadence Design Systems, Inc Rob Slater, Freescale Semiconductor Inc Ralph duncan, Mentor Graphics Corporation John Stickley, Mentor Graphics Corporation Jim garnett, Mentor Graphics Corporation Stuart Sutherland. Sutherland HDL. inc Joao geada CLK Design Automation Bassam Tabbara. Novas software. Inc Andrzej litwiniuk, Synopsys, Inc Jim Vellenga, Cadence Design Systems, Inc Francoise Martinolle, Cadence Design Systems, Inc Doug Warmke, Mentor Graphics Corporation Sachchidananda Patel, Synopsys, Inc In addition, the working group wishes to recognize the substantial efforts of past contributors Michael McNamara, Cadence Design Systems, Inc 1364 Working Group past chair(through September 2004) Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004) Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004) The following members of the entity balloting commitlee voted on this standard. Balloters may have voted for approval, disapproval, or abstention Accellera Intel Corporation Bluespec, Inc. Mentor Graphics Corporation Cadence Dcsign Systcms, Inc Sun microsystems, Inc Intronic u.s.a Sunburst design, Inc IBM Sutherland hdl lnc Infineon Technologies Synopsys, Inc Copyright C 2006 IEEE. All rights reserved When the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the following membership Steve M. mills. chair Richard h. hulett vice chair Don wright Past chair Judith gorman. secretary Mark d. bowman William B Hopf T W. olsen Dennis B. Brophy Lowell G. Johnson Glenn parsons Joseph brude Herman Koch Ronald c. petersen Richard cox Joseph L. Koepfinger* Gary s. Robinson Bob davis David J law Frank stone Julian forster k Daleep c mohla Malcolm v thaden Joanna n. guenin Paul nikolich Richard l. townsend S. Halp Joe d. watse Raymond hapeman Howard L, wolfman Also included are the following nonvoting Ieee-Sa Standards board liaisons Satish K. a val, NRC Representative Richard Deblasio, DOE Representative Alan H. Cookson, NIST Representative Michelle d, tr IEEE Standards Project Edito Copyright C 2006 IEEE. All rights reserved Contents Overview 1. 2 Conventions used in this standard 1.3S Iption 1 4 Use of color in this standard 1.5 Contents of this standard 1.6 Deprecated clauses……….….….….… 1.7 Header file listings.... 18 Examples………………… 1.9P Normative references 6 3. Lexical conventions 8 3.1 Lexical tokens 3.2 White space 3. 3 Comments 中··…·········:···············中·····“:·:·:·4·····“·········· 3. 4 Operators 3. 5 Numbers steger constants 3.5.2 Real constants 12 3.5.3 Conversion 12 3.6 Strings 12 3.6. 1 String variable declaration 13 3.6.2 String manipulation 13 3.6.3 Special cha 3.7 Identifiers. ke ds, and syste 14 3.7.1 Escaped identifiers 14 3.7.2 Keywords 15 3.7.3 System tasks and functions 3.7.4 Compiler directives 15 3.8 Attrib 16 3.8.1 Examples 3.8.2 SyI ata typ ·· 4.1 Val 21 4.2 Nets and variables 4.2.1 Net declarations 4.2.2 Variable declarations 4.3V 4.3.1 g v 24 4.3.2 Veclor net accessibility 4 4.4 Strengths 4.4.1 Charge strength 4.4.2 Drive strength..... 卓········中····“·········:·····················:········ 25 4.5 Implicit declarations 4.6 Net types……… 26 4.6.1 Wire and tri nets 26 4.6.2 Wired nets 4.6.3T Copyright C 2006 IEEE. All rights reserved 4.6.4 Trio and tri l nets 4.6.5 Unresolved nets 4.6.6 Supply nets 32 4.7 Regs 32 4.8 Integers, reals, times, and realtime 4.8.1 Operators and real numbers 4.8.2 Conversion 4.9 Arrays 4.9.1 Net arrays… ·中·····:·· 34 4.9.2 reg and variable arrays 34 4.9.3 Memories 4.10 Parameters………………… 35 4.10.1 Module parameters …36 4.10.2 Local parameters(localparam ““ 37 4.10.3 Specify parameters…… 38 4. Name spaces… 39 Expressions…… 5.1 Operators 41 Operators with real operands 42 5.1.2 Operator precedence……… 5.1.3 Using integer numbers in expressions…… .44 5.1.4 Expression evaluation order…… 245 1. 5 Arithmetic operators 5.1.6 Arithmetic expressions with regs and integers 5. 1.7 Relational operators 48 5.1.8Equ 49 5.1.9 Logical operators …49 5.1.10 bitw is ators 50 5.1.11 Reduction operators 5.112 Shift operators…… .53 5. 1. 13 Conditional operator 53 5.1. 14 Concatenations 54 5.2 Operands……… 5.2. 1 Vector bit-Select and part-select addressing ..56 5.2.2 Array and memory addressing.......,.…… 5.2.3 ings 58 5.3 Minimum, typical, and maximum delay expressions 5.4 Expression bit lengths 5.4.1 Rules for expression bit lengths 6 5.4.2 Exam ole of expression bit-length probler pl 63 5.4.3 Example of self-determined expressions .64 5.5 Signed expressions 5.5.1 Rules for expression types..... 5.5.2 Steps for evaluating 5.5.3 Steps for evaluating an assignment 5.54 Handling X and Z in signed expressions……… 5.6 Assignments and truncation 6. Assignments…………… 68 6.1 Continuous assignments 68 6. 1. 1 The net declaration assignment 6.1.2 The continuous assignment statement ·····中·· ·:·:·4·中····· 6.1.3 71 Copyright C 2006 IEEE. All rights reserved 【实例截图】
【核心代码】