Delta-Sigma Data Converters Theory，Design，and Simulation

【实例简介】
Delta—Sigma 调制器的最经典著作，微电子、通信、集成电路设计相关方向的权威书籍，pdf高清版，不是扫描版！！
IEEE Press 445 Hoes Lane. P o. Box 1331 Piscataway, NJ 08855-1331 Editorial board John B. Anderson, Editor in Chief P.M. Anderson A.H. Haddad P Laplante M. Eden R. Herrick R S Muller M.E. El-Hawary G. F. Hoffnagle W.D. Reeve S Furui R. F. Hoyt D.. Wells S. Kartalopoulos Dudley R. Kay, Director of Book Publishing John Griffin. Senior editor Lisa dayne, Assistant editor Linda matarazzo. Editorial assistant Savoula amanatidis Production editor IEEE Circuits Systems Society, sponsor CAS-S Liaison to IEEE Press, Jaime Ramirez-Angulo Also of Interest from IEEE Press Oversampling Delta-Sigma Data Converters: Theory, Design and simulation edited by James C. Candy, aT&T Bell laboratories and gabor C. temes, Oregon state university Hardcover 512 pp ISBN0-87942-285-8 Clock Distribution Networks in VLsi Circuits and Systems edited by Eby G. Friedman, University of rochester 1995 arcover 544p ISBN0-7803-1058-6 Nonvolatile semiconductor Memories: Technologies, Design, and Applications edited by Chenming Hu, University of california, Berkeley 1991 Hardcover 496 ISBN0-87942-269-6 Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and design edited by behzad razavi at&T Bell laboratories 1996 Hardcover 512 pp ISBN0-7803-1149-3 Routing in the Third Dimension: From VLSI Chips to MCMs Naveed A. Sherwani, Siddharth Bhingarde, and Anand Panyam, Microprocessor Division, Inter Corporation 1995 Hardcover 376 pp ISBN0-7803-10896 Circuits and Systems Tutorials Chris Toumazou, Editor; Nick Battersby and Sonia Porta, Assistant Editors 1996 Softcover 700 pp ISBN0-7803-1170 Delta-Sigma Data Converters Theory, Design, and simulation Edited by Steven R Norsworthy Motorola Richard schreier Oregon State University Gabor c temes Oregon State University lEEE Circuits Systems Society, Sponsor ◆EEE The Institute of Electrical and Electronics Engineers, Inc, New York 少 WILEY NTERSCIENCE A JOHN WILEY & SONS, INC, PUBLICATION C 1997 THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS. INC 3 Park Avenue 17th Floor, New York, NY 10016-5997 All rights Published by John Wiley sons, InC, Hoboken, New Jersey No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc, 222 Rosewood Drive Danvers MA 01923. 978-750-8400. fax 978-750-4470. or onthewebatwww.copyright.comRequeststothePublisherforpermission should be addressed to the Permissions department John Wiley sons, Inc 1 11 River Street, Hoboken, NJ07030, (201)748-6011, fax(201)748-6008, e- mail:permcoordinator@wiley.com For general information on our other products and services please contact our Customer Care Department within the u.s at 877-762-2974, outside the U. S at317-572-3993 or fax317572-4002. Library of Congress Cataloging-in-Publication Data Delta-Sigma data converters: theory, design, and simulation /edited by Steven R Norsworthy, Richard Schreier, Gabor C. Temes; IEEE Circuits systems Society, sponsor p. Cm. Includes index ISBN0-7803-1045-4 1. Analog-to-digital converters. 2. Digital-to-analog converters 3. Modulators(Electronics)--Design. I. Norsworthy, Steven R. date). II. Schreier, Richard(date). Ill. Temes, Gabor C (date). IV. IEEE Circuits Systems Society TK7887.6D451996 621.3815322-dc20 96-14774 CIP Contents Preface xv Introduction xvii Chapter 1 An Overview of Basic Concepts 1 J.C. C 1.1 Introduction 1 1.2 Digital Modulation 3 1.2 1 Quantization 3 1.2.2 Delta-Sigma Modulation 5 1.2.2.1 First-Order Feedback Quantizer 5 1.2.2.2 Modulation Noise in Busy Signals 7 1.2.2. 3 Pattern Noise from AE Modulation with dc inputs 8 1.2.2.4 Dead Zones in△∑ Modulation10 1.2.2.5 Influence of Circuit Parameters on 42 Modulation 11 1.2.3 High-Order Modulation 14 1.2.3.1 Predicting In-Band values of Quantization Error 14 1.232 Noise in high- Order△Σ Modulation14 1.2.3. 3 Dynamic Range of the Modulators 16 1.2.3 4 Influence of circuit Parameters on Second-Order Modulators 19 1.2. 3.5 Limit Cycles in Third-Order AE Modulators 20 1.2 3.6 Noise Shaping Using Filters with Nonmonotonic Transfer Functions 22 1.2. 4 Some Alternative Modulator Structures 23 1.2.4.1 Error Feedback 23 1.2. 4.2 Cascaded modulators 24 1.2.4.3 Delta Modulation 26 Contents 1.3 Decimating the Modulated Signal 28 1.3. 1 Multistage Decimation 28 1.3.2 Design of the First-Stage Decimator 29 1.3.3 Implementing sinc Decimators 32 1.3.4 The Low-Pass Filter 35 1.4 Oversampling D/A Converters 36 1.4.1 Demodulating Signals at Elevated Word Rates 36 1.4.2 Interpolating with sinc -Shaped Filter Functions 37 1.4.3 Demodulator Stage 38 1.4.3.1 Quantizing the Digital Signal 38 1.4.3.2 Quantization with error Feedback 38 1.4.3.3 Cascaded Demodulators 40 1434 Circuit Design for△∑ Demodulation40 1.5 Conclusion 41 References 41 Chapter 2 Quantization Noise in AE A/D Converters 44 Robert M. Gray 2.1 Introduction 44 2.2 Uniform Quantization 45 2.3 Additive White-Noise Approximation 46 2. 4 Characteristic Function Method 53 2.5 Pulse Code modulation quantization noise 55 2. 6 Dithered PCm 58 2.7 Single-Loop AE Modulation 59 28Two- Stage( Cascade or MASH)△∑ Modulation64 29 Second-0rder△∑ Modulation66 2.10 Some Extensions 68 210.1 Dithered Single-Loop△∑ Modulation68 210.2 Multistage and Higher Order△∑ Modulation68 210.3 Leaky Integrating△Σ Modulation69 2.10.4 Multibit Quantizer, Single-Bit Feedback 69 2.10.5 Related Work 69 2.11 Conclusion 70 Acknowledgments 70 References 70 Chapter 3 Quantization Errors and Dithering in A2 Modulators 75 Steven R. Norsworthy 3. 1 Introduction 75 3.1.1 Problems with Empirically Based Reports on AE Modulators 77 3.1.2 Steps Taken to Ensure Accuracy of Results 77 3.2 Basic Structures and Terminology 78 Contents 3.3 Observability of Periodic Sequences 80 34 Tones in Single- Stage△∑ Modulators84 3.4.1 Second -Order Modulator 85 3.4.2 Third-Order Modulator 88 3.4.3 Fifth-Order modulator 92 3.4.4 Baseband Demodulation of Tones Near f /2 95 3.4.5 Higher-Order and Multibit Single-Stage Modulators 97 35 Tones in Multistage△∑ Modulators98 3.6 Tones in△∑ Converter Hardware100 3.6.1 Third-Order Digital Modulator Test 101 3.6.2 Fifth-Orcer Digital Modulator Test 102 3.6.3 Multistage Modulator Test 104 3.7 Dither in PCM Quantizers 104 3.7.1 Nonsubtractive Dither 104 3.7.2 Subtractive Dither 105 38 Dither Topologies for△∑ Modulators107 3.8.1 Dither Topologies for Single-Stage Modulators 107 3.8.2 Dither Topologies for Multistage Modulators 109 3. 9 Empirical Studies of Noise-Shaped Dithering 112 3.9.1 Second-Order Modulator 112 3.9.2 Third-Order Modulator 116 3.9.3 Fifth -Order Modulator 118 3. 9.4 Effect of Dither on Tones Near f /2 119 3.9.5 Multistage Modulators 120 3.10 Dither generation 121 3.11 Dither in Ad Modulators 121 3. 11. 1 Single-Stage AD Modulator Example 121 3.11.2 Multistage AD Modulators 121 3.12 Subtractive Noise-Shaped Dithering 123 3.13 Dynamic Noise-Shaped Dithering 124 3. 13. 1 Theory of Dynamic Dither 124 3.13.2 Implementation Considerations of Dynamic Dither 127 3.14 Dithered Multibit Noise-Shaping Coders 130 3. 14. 1 Stability Test with Dither 130 3.15 Chaos versus Noise-Shaped Dither 131 3.16 Other Techniques 134 3.17 Conclusion 135 References 136 Chapter 4 Stability Theory for AE Modulators 141 Robert W. Adams and richard Schreier 4.1 Introduction 141 4.2 Linear Analysis 142 4.2. 1 The Linear Model 142 4.2.2 Root Locus of a high-order Modulator 144 4.2.3 Describing Function Method 145 4.3 First- and Second-Order Modulators 147 4.3.1 First-Order Modulator 148 4.3.2 Second-Order Modulator 149 4.4 Practical Design Methodology 152 4.4.1 Cookbook Design Procedure 152 4.4.2 SNR Limits 153 4.4.3 Sixth-Order NTF 154 4.4.4 Design Trade-Offs 156 4.5 Continuous-Time Design 158 4.6 Nonlinear Stabilization Techniques 162 4.7 Conclusion 163 Acknowledgments 163 References 163 Chapter 5 The design of High-order Single-Bit A2 ADCS 165 Robert w. adams 5.1 Introduction 165 5.2 Motivation for Using High-Order Single- Bit Loops 166 5. 3 Design Choices: SC or Active-RC? 167 5.4 Stability 170 5.4.1 Stability and the Uncontrolled Input signal A Practical Guide to Safe Operation 170 The Case for mild Prefiltering 170 5.4.2 Transient Input Signals and Stabilit 5.5 Choices for the ntf 172 5.5.1 nth-Order pure differentiation 172 5.5.2 Butterworth High-Pass Response 173 5.5.3 Complex Zeros on the Unit Circle ( Inverse Chebyshev )174 5.6 Comparison of Loop Topologies 174 5.6.1 Chain of Integrators with Weighted Feedforward Summation 176 5.6.2 Chain of Integrators with Feedforward Summation and local Resonator Feedbacks 177 5.6.3 Chain of Integrators with Distributed Feedback 178 5.6.4 Chain of Integrators with Distributed Feedback and Distributed Feedforward Inputs 179 5.6.5 Error Feedback Only 180 5.7 Nonlinear Global Stabilization Techniques 183 5.8 Practical Measures for Preventing Idle Tones 185 5.9 Practical Implementation of a Stereo 18-Bit AE ADC IC 186 5.9.1 Noise-Shaping Modulator IC 186 5.9.2 Switched-Capacitor Loop Filter Design 186 5.9.3 Circuit Noise Considerations 189 5.9. 4 Stabilization Using Integrator reset 190 5.9.5 0p-Amp Design 190 5.9.6 Results and comments 191 References 192 Contents Chapter6 The Design of cascaded△ΣADcs193 Mike rebeschini 6.1 Introduction 193 6.2 System Design 195 6.2.1 Comparison of Single-Loop and Cascaded Designs 195 6.2. 1 1 Single-Loop Designs 195 6.2.1.2 Cascaded Designs 196 6.2.2 Analytical Linearized Modeling 196 6.2.3 Software Simulations 197 6. 3 Analysis of Specific Cascaded Architectures 199 6.3.1 Third-Order(1-1-1) Modulator 199 6. 3.2 Third-Order (2-1) Modulator 203 6.4 Circuit Topologies for Third-Order(1-1-1)Cascade 204 6.4.1 Autozeroed Integrator 204 6.4.2 First Modulator of Third-Order (1-1-1)Cascade 206 6.4.3 Second and Third Modulators of Third-Order(1-1-1) Cascade 207 6.5 Sources of Error for the Third-Order(1-1-1)Cascade 209 6.6 Experimental Results for the Third-Order(1-1-1)Cascade 211 6.7 Continuous-Time cascaded△∑ Modulators213 6.8 Conclusion 217 References 218 Chapter7 High-Speed cascaded△∑ADcs219 Brian Brandt 7.1 Introduction 219 72△∑ Modulation at low0 versampling Ratios220 7.3 A Cascaded multibit△∑ Modulator222 7.3.1 Interstage Coupling 225 7. 4 Implementation of the cascaded multibit Modulator 229 7. 4.1 Gain Error 230 7.4.2 Incomplete Settling 232 7.4.3 Integrator Leakage 232 7.5 Design of the Cascaded Multibit Modulator 233 7.6 Experimental results 239 7.7 Summary 242 References 242 Chapter 8 Delta-Sigma ADCs with Multibit Internal converters 244 Richard L. Carley, richard Schreier, and gabor C. Temes 8.1 Introduction 244 8.2 Multibit Noise-Shaping Modulator Architectures 245 8.3 DAC Architectures for Improved Linearity 247 【实例截图】
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