高通9531手册(QCA9531).pdf

【实例截图】80_Y7991_1_QCA9531_V2_0_802_11N_2X2_2_4_GHZ_PREMIUM_SOC_FOR_WLAN_PLATFORMS_DATA_SHEET.pdf

【核心代码】

Contents
1 GeneralDescription ...................................................... 20
1.1 Features ............................................................... 20
1.2 QCA9531SystemBlockDiagram ........................................... 21
  2 3
PinDescriptions .......................................................... 22
FunctionalDescription.................................................... 29
3.1 FunctionalBlockDiagram ................................................. 29
3.2 BootstrapOptions ....................................................... 31
3.3 Reset..................................................................32
3.4 PLLandClockControl ................................................... 33
3.4.1 FullChipClockingStructure ...................................... 33
3.4.2 PLL .......................................................... 34
3.4.3 DDRPLL ..................................................... 34
3.4.4 EthernetPLL ................................................... 35
3.5 MIPSProcessor ......................................................... 35
3.6 AddressMap ........................................................... 35
3.7 DDRMemoryController .................................................. 36
3.7.1 DDRConfigurations ............................................. 36
3.7.2 DDRInitializationSequences ...................................... 37
3.7.3 DDRMemoryInitialization ....................................... 41
3.7.4 CPUDDRAddressMapping ...................................... 42
3.7.5 Refresh ....................................................... 42
3.7.6 SelfRefresh.................................................... 42
3.8 PCIERC...............................................................43
3.8.1 PowerManagement.............................................. 44
3.8.2 Interrupts ...................................................... 44
3.8.3 ErrorReportingCapabilityandStatusChecking ....................... 44
3.8.4 Byte-SwapOption............................................... 44
3.8.5 RequestSizesandPayloads ....................................... 44
3.9 GPIO .................................................................45
3.9.1 GPIOOutput ................................................... 46 3.9.2 GPIOInput .................................................... 48
3.10 SerialFlashSPI/ROM .................................................... 49
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 80-Y7991-1 Rev. C
 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
 4
3.10.1 SPIOperations ................................................. 49 3.10.2 WriteEnable ................................................... 49 3.10.3 PageProgram .................................................. 49 3.10.4 PageRead ..................................................... 50
3.11 Low-SpeedUARTInterface ............................................... 51 3.12 USB2.0Interface........................................................ 51
WLANMediumAccessControl(MAC) .................................... 52
4.1 Overview .............................................................. 52
4.2 Descriptor..............................................................53
4.3 DescriptorFormat ....................................................... 53
4.4 QueueControlUnit(QCU) ................................................ 71
4.5 DCFControlUnit(DCU) ................................................. 71
4.6 ProtocolControlUnit(PCU) ............................................... 71
4.7 RegisterProgrammingDetailsforObservingWMACInterrupts ................... 72
DigitalPHYBlock ......................................................... 74
5.1 Overview .............................................................. 74
5.2 802.11n(MIMO)Mode ................................................... 74
5.2.1 Transmitter(Tx) ................................................ 75
5.2.2 Receiver(Rx) .................................................. 76
5.3 802.11b/gLegacyMode .................................................. 76 5.3.1 Transmitter .................................................... 76 5.3.2 Receiver ...................................................... 76
RadioBlock............................................................... 77
6.1 Receiver(Rx)Block...................................................... 78
6.2 Transmitter(Tx)Block.................................................... 79
6.3 Synthesizer(SYNTH)Block ............................................... 80
6.4 Bias/Control(BIAS)Block ................................................ 80
RegisterDescriptions..................................................... 81
5
6
7
7.1
DDRRegisters .......................................................... 82
7.1.1 DDRDRAMConfiguration(DDR_CONFIG) ......................... 83
7.1.2 DDRDRAMConfiguration2(DDR_CONFIG2) ...................... 84
7.1.3 DDRModeValue(DDR_MODE_REGISTER) ........................ 85
7.1.4 DDR Extended Mode (DDR_EXTENDED_MODE_REGISTER) . . . . . . . . . 85
7.1.5 DDRControl(DDR_CONTROL) .................................. 85
7.1.6 DDR Refresh Control and Configuration (DDR_REFRESH) . . . . . . . . . . . . . 86
7.1.7 DDR Read Data Capture Bit Mask (DDR_RD_DATA_THIS_CYCLE) . . . . . 86
7.1.8 DQSDelayTapControlforByte0(TAP_CONTROL_0) ................ 86
7.1.9 DQSDelayTapControlforByte1(TAP_CONTROL_1) ................ 87
7.1.10 GE0 Interface Write Buffer Flush (DDR_WB_FLUSH_GE0) . . . . . . . . . . . . 87
7.1.11 GE1 Interface Write Buffer Flush (DDR_WB_FLUSH_GE1) . . . . . . . . . . . . 87
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 80-Y7991-1 Rev. C

 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.1.12 USB Interface Write Buffer Flush (DDR_WB_FLUSH_USB) . . . . . . . . . . . . 88
7.1.13 PCIE Interface Write Buffer Flush (DDR_WB_FLUSH_PCIE) . . . . . . . . . . . 88
7.1.14 WMAC Interface Write Buffer Flush (DDR_WB_FLUSH_WMAC) . . . . . . . 88
7.1.15 DDR2Configuration(DDR_DDR2_CONFIG) ........................ 89
7.1.16 DDREMR2(DDR_EMR2) ....................................... 89
7.1.17 DDREMR3(DDR_EMR3) ....................................... 89
7.1.18 DDRBankArbiterPerClientBurstSize(DDR_BURST)................ 90
7.1.19 DDRBankArbiterPerClientBurstSize2(DDR_BURST2) ............. 90
7.1.20 DDR AHB Master Timeout Control (DDR_AHB_MASTER_TIMEOUT_MAX)
91
7.1.21 DDR AHB Timeout Current Count (DDR_AHB_MASTER_TIMEOUT_ CURNT) 91
7.1.22 Timeout Slave Address (AHB_MASTER_TIMEOUT_SLV_ADDR) . . . . . . 91
7.1.23 DDRControllerConfiguration(DDR_CTL_CONFIG) .................. 92
7.1.24 DDRSelfRefreshControl ..........................(DDR_SF_CTL) 93
7.1.25 SelfRefreshTimer(SF_TIMER) ................................... 94
7.1.26 WMACFlush(WMAC_FLUSH)................................... 94
7.1.27 DDR3ConfigurationRegister(DDR3_CONFIG) ...................... 95
7.2 UART0(Low-Speed)Registers ............................................. 96
7.2.1 ReceiveBuffer(RBR)............................................ 96
7.2.2 TransmitHolding(THR).......................................... 97
7.2.3 DivisorLatchLow(DLL)......................................... 97
7.2.4 DivisorLatchHigh(DLH) ........................................ 98
7.2.5 InterruptEnable(IER) ........................................... 98
7.2.6 InterruptIdentity(IIR) ........................................... 99
7.2.7 FIFOControl(FCR) ............................................ 100
7.2.8 LineControl(LCR)............................................. 101
7.2.9 ModemControl(MCR) ......................................... 102
7.2.10 LineStatus(LSR) .............................................. 103
7.2.11 ModemStatus(MSR) ........................................... 104
7.3 USBRegisters ......................................................... 105 7.3.1 USBConfigurationControl(USB_CONFIG) ........................ 105
7.4 GPIORegisters ........................................................ 106
7.4.1 GPIOOutputEnable(GPIO_OE) .................................. 106
7.4.2 GPIOInputValue(GPIO_IN)..................................... 107
7.4.3 GPIOOutputValue(GPIO_OUT) ................................. 107
7.4.4 GPIOPerBitSet(GPIO_SET) .................................... 107
7.4.5 GPIOPerBitClear(GPIO_CLEAR) ............................... 107
7.4.6 GPIOInterruptEnable(GPIO_INT)................................ 108
7.4.7 GPIOInterruptType(GPIO_INT_TYPE) ........................... 108
7.4.8 GPIOInterruptPolarity(GPIO_INT_POLARITY) .................... 108
7.4.9 GPIOInterruptPending(GPIO_INT_PENDING) ..................... 108
7.4.10 GPIOInterruptMask(GPIO_INT_MASK) .......................... 109
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.4.11 GPIO Ethernet LED Routing Select (GPIO_IN_ETH_SWITCH_LED) . . . . 109
7.4.12 GPIOFunction0(GPIO_OUT_FUNCTION0) ....................... 110
7.4.13 GPIOFunction1(GPIO_OUT_FUNCTION1) ....................... 110
7.4.14 GPIOFunction2(GPIO_OUT_FUNCTION2) ....................... 110
7.4.15 GPIOFunction3(GPIO_OUT_FUNCTION3) ....................... 111
7.4.16 GPIOFunction4(GPIO_OUT_FUNCTION4) ....................... 111
7.4.17 GPIOInSignals0(GPIO_IN_ENABLE0) .......................... 112
7.4.18 GPIOFunction(GPIO_FUNCTION) ............................... 112
7.5 PLLControlRegisters ................................................... 113
7.5.1 CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG) . . . . . . . . . . . . 113
7.5.2 DDRPLLConfiguration(DDR_PLL_CONFIG)...................... 114
7.5.3 CPU DDR Clock Control (CPU_DDR_CLOCK_CONTROL) . . . . . . . . . . . 115
7.5.4 CPUSyncRegister(CPU_SYNC) ................................. 116
7.5.5 PCIE PLL Configuration Register (PCIE_PLL_CONFIG) . . . . . . . . . . . . . . 116
7.5.6 PCIE Clock Jitter Control Maximum Register (PCIE_PLL_DITHER_DIV_
MAX) 117
7.5.7 PCIE Clock Jitter Control Minimum Register (PCIE_PLL_DITHER_DIV_MIN) 117
7.5.8 PCIE Clock Jitter Control Step Register (PCIE_PLL_DITHER_STEP) . . . . 118
7.5.9 LDO Power Control Register (LDO_POWER_CONTROL) . . . . . . . . . . . . . 118
7.5.10 Switch Clock Source Control (SWITCH_CLOCK_CONTROL) . . . . . . . . . 119
7.5.11 Current Dither Logic Output (CURRENT_PLL_DITHER) . . . . . . . . . . . . . . 119
7.5.12 Baseband PLL Configuration Register (BB_PLL_CONFIG) . . . . . . . . . . . . 120
7.5.13 DDRPLLDitherParameter(DDR_PLL_DITHER) ................... 120
7.5.14 CPUPLLDitherParameter(CPU_PLL_DITHER) .................... 120
7.6 ResetRegisters ......................................................... 121
7.6.1 GeneralPurposeTimers(RST_GENERAL_TIMERx) ................. 122
7.6.2 General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx) . . 122
7.6.3 Watchdog Timer Control (RST_WATCHDOG_TIMER_CONTROL) . . . . . 123
7.6.4 WatchdogTimer(RST_WATCHDOG_TIMER) ...................... 123
7.6.5 Miscellaneous Interrupt Status (RST_MISC_INTERRUPT_STATUS) . . . . . 124
7.6.6 Miscellaneous Interrupt Mask (RST_MISC_INTERRUPT_MASK) . . . . . . 125
7.6.7 Global Interrupt Status (RST_GLOBAL_INTERRUPT_STATUS) . . . . . . . 126
7.6.8 Reset(RST_RESET)............................................ 126
7.6.9 ChipRevisionID(RST_REVISION_ID)............................ 127
7.6.10 PCIE WMAC Interrupt Status (RST_PCIE _WMAC_INTERRUPT_STATUS) 127
7.6.11 ResetBootstrap(RST_BOOTSTRAP) .............................. 128
7.6.12 StickyRegisterValue(SPARE_STKY_REG[0:0]) .................... 129
7.6.13 MiscellaneousCPUControlBits(RST_MISC2) ...................... 129
7.6.14 AHBClockGatingResetRegister(RST_CLKGAT_EN) ............... 129
7.7 GMACInterfaceRegisters................................................ 130 7.7.1 EthernetConfiguration(ETH_CFG) ............................... 130
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
 7.8
PCIERCControlRegisters ............................................... 131
7.8.1 PCIEApplicationControl(PCIE_APP) ............................. 132
7.8.2 PCIEInterruptandError(PCIE_AER) ............................. 133
7.8.3 PCIEPowerManagement(PCIE_PWR_MGMT) ..................... 133
7.8.4 PCIEElectromechanical(PCIE_ELEC) ............................. 134
7.8.5 PCIEConfiguration(PCIE_CFG) ................................. 134
7.8.6 PCIEReceiveCompletion(PCIE_RX_CNTL) ....................... 135
7.8.7 PCIEReset(PCIE_RESET) ...................................... 135
7.8.8 PCIEDebugandControl(PCIE_DEBUG) .......................... 136
7.8.9 PCIEPHYRead/WriteData(PCIE_PHY_RW_DATA) ................ 136
7.8.10 PCIE PHY Serial Interface Load/Read Trigger (PCIE_PHY_TRG_RD_LOAD) 137
7.8.11 PCIE PHY Configuration Data (PCIE_PHY_CFG_DATA) . . . . . . . . . . . . . . 137
7.8.12 PCIEMAC-PHYInterfaceSignals(PCIE_MAC_PHY) ................ 137
7.8.13 PCIEPHY-MACInterfaceSignals(PCIE_PHY_MAC) ................ 138
7.8.14 PCIESidebandBus1(PCIE_SIDEBAND1) ......................... 138
7.8.15 PCIESidebandBus2(PCIE_SIDEBAND2) ......................... 138
7.8.16 PCIESpare(PCIE_SPARE) ...................................... 139
7.8.17 PCIEMSILowerAddress(PCIE_MSI_ADDR) ...................... 139
7.8.18 PCIEMSIDataValue(PCIE_MSI_DATA) .......................... 139
7.8.19 PCIEInterruptStatus(PCIE_INT_STATUS) ......................... 139
7.8.20 PCIEInterruptMask(PCIE_INT_MASK)........................... 141
7.8.21 PCIEErrorCounter(PCIE_ERR_CNT)............................. 142
7.8.22 PCIE AHB Latency Interrupt Counter (PCIE_REQ_LATENCY_W_INT) . . 142
7.8.23 MiscellaneousPCIEBits(PCIE_MISC) ............................ 142
WDMARegisters....................................................... 143
7.9.1 Command(CR) ................................................ 144
7.9.2 ConfigurationandStatus(CFG) ................................... 144
7.9.3 Rx DMA Data Buffer Pointer Threshold (RXBUFPTR_THRESH) . . . . . . . 145
7.9.4 Tx DMA Descriptor Pointer Threshold (TXDPPTR_THRESH) . . . . . . . . . . 145
7.9.5 MaximumInterruptRateThreshold(MIRT) ......................... 145
7.9.6 InterruptGlobalEnable(IER)..................................... 146
7.9.7 TxInterruptMitigationThresholds(TIMT) .......................... 146
7.9.8 RxInterruptMitigationThresholds(RIMT).......................... 146
7.9.9 TxConfiguration(TXCFG) ...................................... 147
7.9.10 RxConfiguration(RXCFG) ...................................... 148
7.9.11 MIBControl(MIBC) ........................................... 148
7.9.12 DataBufferLength(DATABUF) .................................. 149
7.9.13 GlobalTxTimeout(GTT) ....................................... 149
7.9.14 GlobalTxTimeoutMode(GTTM)................................. 149
7.9.15 CarrierSenseTimeout(CST) ..................................... 150
7.9.16 SizeofHighandLowPriority(RXDP_SIZE) ........................ 150
7.9.17 MAC Rx High Priority Queue RXDP Pointer (RX_QUEUE_HP_RXDP) . . 150
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7.9
 80-Y7991-1 Rev. C

 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.9.18 MAC Rx Low Priority Queue RXDP Pointer (RX_QUEUE_LP_RXDP) . . . 150
7.9.19 PrimaryInterruptStatus(ISR_P) .................................. 151
7.9.20 SecondaryInterruptStatus0(ISR_S0) .............................. 152
7.9.21 SecondaryInterruptStatus1(ISR_S1) .............................. 153
7.9.22 SecondaryInterruptStatus2(ISR_S2) .............................. 153
7.9.23 SecondaryInterruptStatus3(ISR_S3) .............................. 154
7.9.24 SecondaryInterruptStatus4(ISR_S4) .............................. 154
7.9.25 SecondaryInterruptStatus5(ISR_S5) .............................. 155
7.9.26 PrimaryInterruptMask(IMR_P) .................................. 156
7.9.27 SecondaryInterruptMask0(IMR_S0) ............................. 157
7.9.28 SecondaryInterruptMask1(IMR_S1) ............................. 157
7.9.29 SecondaryInterruptMask2(IMR_S2) ............................. 158
7.9.30 SecondaryInterruptMask3(IMR_S3) ............................. 158
7.9.31 SecondaryInterruptMask4(IMR_S4) ............................. 159
7.9.32 SecondaryInterruptMask5(IMR_S5) ............................. 159
7.9.33 PrimaryInterruptStatusReadandClear(ISR_P_RAC) ................ 160
7.9.34 SecondaryInterruptStatus0(ISR_S0_S) ............................ 160
7.9.35 SecondaryInterruptStatus1(ISR_S1_S) ............................ 160
7.9.36 SecondaryInterruptStatus2(ISR_S2_S) ............................ 160
7.9.37 SecondaryInterruptStatus3(ISR_S3_S) ............................ 161
7.9.38 SecondaryInterruptStatus4(ISR_S4_S) ............................ 161
7.9.39 SecondaryInterruptStatus5(ISR_S5_S) ............................ 161
7.10 WQCURegisters ....................................................... 162
7.10.1 TxQueueDescriptor(Q_TXDP) .................................. 162
7.10.2 QCU_STATUS_RING_START_ADDRESS Lower 32 bits of Address (Q_
STATUS_RING_START) 163
7.10.3 QCU_STATUS_RING_END_ADDR Lower 32 Bits of Address (Q_STATUS_ RING_END) 163
7.10.4 QCU_STATUS_RING_CURRENT Address (Q_STATUS_RING_CURRENT) 163
7.10.5 TxQueueEnable(Q_TXE) ...................................... 163
7.10.6 TxQueueDisable(Q_TXD) ...................................... 164
7.10.7 CBRConfiguration(Q_CBRCFG) ................................. 164
7.10.8 ReadyTimeConfiguration(Q_RDYTIMECFG) ...................... 164
7.10.9 OneShotArmSetControl(Q_ONESHOTARM_SC) ................... 165
7.10.10 OneShotArmClearControl(Q_ONESHOTARM_CC) ................. 165
7.10.11 Misc.QCUSettings(Q_MISC) ................................... 166
7.10.12 Misc.QCUStatus(Q_STS) ...................................... 167
7.10.13 ReadyTimeShutdownStatus(Q_RDYTIMESHDN) ................... 167
7.10.14 Descriptor CRC Check (MAC_QCU_DESC_CRC_CHK) . . . . . . . . . . . . . . 168
7.11 WDCURegisters ....................................................... 169 7.11.1 QCUMask(D_QCUMASK) ..................................... 169 7.11.2 DCU-GlobalSIFS(D_GBL_IFS_SIFS)............................. 170
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.11.3 DCU-SpecificIFSSettings(D_LCL_IFS) ........................... 170
7.11.4 QCUGlobalIFSSlots(D_GBL_IFS_SLOT) ........................ 170
7.11.5 RetryLimits(D_RETRY_LIMIT) ................................. 171
7.11.6 QCUGlobalIFSEIFS(D_GBL_IFS_EIFS) ......................... 171
7.11.7 ChannelTimeSettings(D_CHNTIME) ............................. 171
7.11.8 QCUGlobalIFSMiscellaneous(D_GBL_IFS_MISC) ................. 172
7.11.9 Misc.DCU-SpecificSettings(D_MISC) ............................ 173
7.11.10 DCUSequence(D_SEQ) ........................................ 175
7.11.11 DCUPause(D_PAUSE) ......................................... 176
7.11.12 DCUTransmissionSlotMask(D_TXSLOTMASK) ................... 176
7.11.13 MACSleepStatus(SLEEP_STATUS) .............................. 177
7.11.14 MACLEDConfiguration(LED_CONFIG) .......................... 177
7.12 WMACGlueRegisters .................................................. 178
7.12.1 Interface Reset Control (WMAC_GLUE_INTF_RESET_CONTROL) . . . . 179
7.12.2 Synchronous Interrupt Enable (WMAC_GLUE_INTF_INTR_SYNC_ENABLE)
179
7.12.3 Interface Timeout (WMAC_GLUE_INTF_TIMEOUT) . . . . . . . . . . . . . . . . 179
7.12.4 Synchronous Interrupt Cause (WMAC_GLUE_INTF_INTR_SYNC_CAUSE) . 179
7.12.5 Synchronous Interrupt Enable (WMAC_GLUE_INTF_INTR_SYNC_ENABLE) 180
7.12.6 Asynchronous Interrupt Mask (WMAC_GLUE_INTF_INTR_ASYNC_MASK) 180
7.12.7 Synchronous Interrupt Mask (WMAC_GLUE_INTF_INTR_SYNC_MASK) . . 180
7.12.8 Asynchronous Interrupt Cause (WMAC_GLUE_INTF_INTR_ASYNC_ CAUSE) 180
7.12.9 Asynchronous Interrupt Enable (WMAC_GLUE_INTF_INTR_ASYNC_ ENABLE) 181
7.12.10 GPIOOutput(WMAC_GLUE_INTF_GPIO_OUT) ................... 181
7.12.11 GPIOInput(WMAC_GLUE_INTF_GPIO_IN) ...................... 181
7.12.12 GPIO SWCOM Enable Function (WMAC_GLUE_INTF_SWCOM_GPIO_ FUNC_ENABLE) 181
7.12.13 WMAC Glue GPIO Input Value (WMAC_GLUE_INTF_GPIO_INPUT_ VALUE) 182
7.12.14 Output Values from MAC to GPIO Pins (WMAC_GLUE_INTF_GPIO_INPUT_ STATE) 182
7.12.15 WMAC Glue Miscellaneous (WMAC_GLUE_INTF_MISC) . . . . . . . . . . . . 183
7.12.16 Synchronous AP Transmit (WMAC_GLUE_INTF_MAC_TXAPSYNC) . . 183
7.12.17 Synchronous Initial Timer (WMAC_GLUE_INTF_MAC_TXSYNC_INITIAL_ SYNC_TMR) 183
7.12.18 Synchronous Priority Interrupt Cause (WMAC_GLUE_INTF_INTR_ PRIORITY_SYNC_CAUSE) 183
7.12.19 Synchronous Priority Interrupt Enable (WMAC_GLUE_INTF_INTR_ PRIORITY_SYNC_ENABLE) 184
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet
Contents
  80-Y7991-1 Rev. C
7.12.20 Asynchronous Priority Interrupt Mask (WMAC_GLUE_INTF_INTR_ PRIORITY_ASYNC_MASK) 184
7.12.21 Synchronous Priority Interrupt Mask (WMAC_GLUE_INTF_INTR_ PRIORITY_SYNC_MASK) 184
7.12.22 Asynchronous Priority Interrupt Cause (WMAC_GLUE_INTF_INTR_ PRIORITY_ASYNC_CAUSE) 185
7.12.23 Asynchronous Priority Interrupt Enable (WMAC_GLUE_INTF_INTR_ PRIORITY_ASYNC_ENABLE) 185
7.12.24 AXI to MAC and MAC to AXI Byte Swap Enable (WMAC_GLUE_INTF_ AXI_BYTE_SWAP) 185
7.13 RTCRegisters ......................................................... 186
7.13.1 ResetControl(RESET_CONTROL) ............................... 186
7.13.2 XTALControl(XTAL_CONTROL) ............................... 187
7.13.3 SwitchingRegulatorControlBits0(REG_CONTROL0) ............... 187
7.13.4 WLANPLLControlSettings(WLAN_PLL_CONTROL) .............. 188
7.13.5 PLLSettlingTime(PLL_SETTLE) ................................ 189
7.13.6 CrystalSettlingTime(XTAL_SETTLE) ............................ 189
7.13.7 PinClockSpeedControl(CLOCK_OUT) ........................... 190
7.13.8 ResetCause(RESET_CAUSE) ................................... 191
7.13.9 SystemSleepStatus(SYSTEM_SLEEP) ............................ 191
7.13.10 KeepAwakeTimer(KEEP_AWAKE) .............................. 192
7.13.11 DerivedRTCClock(DERIVED_RTC_CLK) ........................ 192
7.13.12 PLLControl(PLL_CONTROL2).................................. 193
7.13.13 RTCSyncReset(RTC_SYNC_RESET) ............................ 193
7.13.14 RTCSyncStatus(RTC_SYNC_STATUS) ........................... 193
7.13.15 RTCDerived(RTC_SYNC_DERIVED) ............................ 194
7.13.16 RTCForceWake(RTC_SYNC_FORCE_WAKE)..................... 194
7.13.17 RTCInterruptCause(RTC_SYNC_INTR_CAUSE) ................... 194
7.13.18 RTCInterruptEnable(RTC_SYNC_INTR_ENABLE) ................. 195
7.13.19 RTCInterruptMask(RTC_SYNC_INTR_MASK) .................... 195
7.14 WPCURegisters ....................................................... 196
7.14.1 STA Address Lower 32 Bits (WMAC_PCU_STA_ADDR_L32) . . . . . . . . . 199
7.14.2 STA Address Upper 16 Bits (WMAC_PCU_STA_ADDR_U16) . . . . . . . . . 199
7.14.3 BSSIDLower32Bits(WMAC_PCU_BSSID_L32) ................... 200
7.14.4 BSSIDUpper16Bits(WMAC_PCU_BSSID_U16) ................... 200
7.14.5 Beacon RSSI Average (WMAC_PCU_BCN_RSSI_AVE) . . . . . . . . . . . . . . 200
7.14.6 ACK and CTS Timeout (WMAC_PCU_ACK_CTS_TIMEOUT) . . . . . . . . . 201
7.14.7 Beacon RSSI Control (WMAC_PCU_BCN_RSSI_CTL) . . . . . . . . . . . . . . . 201
7.14.8 Ms Counter and Rx/Tx Latency (WMAC_PCU_USEC_LATENCY) . . . . . . 201
7.14.9 ResetTSF(WMAC_PCU_RESET_TSF) ........................... 202
7.14.10 Maximum CFP Duration (WMAC_PCU_MAX_CFP_DUR) . . . . . . . . . . . . 202
7.14.11 RxFilter(WMAC_PCU_RX_FILTER) ............................. 203
7.14.12 Multicast Filter Mask Lower 32 Bits (WMAC_PCU_MCAST_FILTER_L32) .
204
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet
Contents
  80-Y7991-1 Rev. C
7.14.13 Multicast Filter Mask Upper 32 Bits (WMAC_PCU_MCAST_FILTER_U32) . 204
7.14.14 DiagnosticSwitches(WMAC_PCU_DIAG_SW) ..................... 204
7.14.15 TSFLower32Bits(WMAC_PCU_TSF_L32) ....................... 205
7.14.16 TSFUpper32Bits(WMAC_PCU_TSF_U32) ....................... 206
7.14.17 AES Mute Mask 0 (WMAC_PCU_AES_MUTE_MASK_0) . . . . . . . . . . . . 206
7.14.18 AES Mute Mask 1 . . . . . . . . . . . . (WMAC_PCU_AES_MUTE_MASK_1) 206
7.14.19 Dynamic MIMO Power Save (DYM_MIMO_PWR_SAVE) . . . . . . . . . . . . . 206
7.14.20 Last Receive Beacon TSF (MAC_PCU_LAST_BEACON_TSF) . . . . . . . . . 207
7.14.21 CurrentNAV(WMAC_PCU_NAV) ................................ 207
7.14.22 Successful RTS Count (WMAC_PCU_RTS_SUCCESS_CNT) . . . . . . . . . . 207
7.14.23 FailedRTSCount(WMAC_PCU_RTS_FAIL_CNT) .................. 208
7.14.24 FAILACKCount(WMAC_PCU_ACK_FAIL_CNT) ................. 208
7.14.25 FailedFCSCount(WMAC_PCU_FCS_FAIL_CNT) .................. 208
7.14.26 BeaconCount(WMAC_PCU_BEACON_CNT) ...................... 209
7.14.27 MACPCUSleep1(SLP1) ....................................... 209
7.14.28 Sleep2(WMAC_PCU_SLP2) .................................... 209
7.14.29 Address 1 Mask Lower 32 Bits (WMAC_PCU_ADDR1_MASK_L32) . . . . 210
7.14.30 Address 1 Mask Upper 16 Bits (WMAC_PCU_ADDR1_MASK_U16) . . . . 210
7.14.31 TxPowerControl(WMAC_PCU_TPC) ............................ 210
7.14.32 TxFrameCounter(WMAC_PCU_TX_FRAME_CNT) ................ 211
7.14.33 RxFrameCounter(WMAC_PCU_RX_FRAME_CNT) ................ 211
7.14.34 RxClearCounter(WMAC_PCU_RX_CLEAR_CNT) ................. 211
7.14.35 CycleCounter(WMAC_PCU_CYCLE_CNT) ....................... 211
7.14.36 QuietTime1(WMAC_PCU_QUIET_TIME_1) ...................... 212
7.14.37 QuietTime2(WMAC_PCU_QUIET_TIME_2) ...................... 212
7.14.38 QoSNoACK(WMAC_PCU_QOS_NO_ACK)....................... 213
7.14.39 PHYErrorMask(WMAC_PCU_PHY_ERROR_MASK) .............. 214
7.14.40 RxBuffer(WMAC_PCU_RXBUF) ................................ 214
7.14.41 QoSControl(WMAC_PCU_MIC_QOS_CONTROL) ................. 215
7.14.42 Michael QoS Select (WMAC_PCU_MIC_QOS_SELECT) . . . . . . . . . . . . . 215
7.14.43 MiscellaneousMode(WMAC_PCU_MISC_MODE) .................. 216
7.14.44 Filtered OFDM Counter (WMAC_PCU_FILTER_OFDM_CNT) . . . . . . . . . 217
7.14.45 Filtered CCK Counter (WMAC_PCU_FILTER_CCK_CNT) . . . . . . . . . . . . 217
7.14.46 PHY Error Counter 1 (WMAC_PCU_PHY_ERR_CNT_1) . . . . . . . . . . . . . 218
7.14.47 PHY Error Counter 1 Mask (WMAC_PCU_PHY_ERR_CNT_1_MASK) . . 218
7.14.48 PHY Error Counter 2 (WMAC_PCU_PHY_ERR_CNT_2) . . . . . . . . . . . . . 218
7.14.49 PHY Error Counter 2 Mask (WMAC_PCU_PHY_ERR_CNT_2_MASK) . . 219
7.14.50 TSFThreshold(WMAC_PCU_TSF_THRESHOLD) .................. 219
7.14.51 PHY Error EIFS Mask (WMAC_PCU_PHY_ERROR_EIFS_MASK) . . . . . 219
7.14.52 PHY Error Counter 3 (WMAC_PCU_PHY_ERR_CNT_3) . . . . . . . . . . . . . 220
7.14.53 PHY Error Counter 3 Mask (WMAC_PCU_PHY_ERR_CNT_3_MASK) . . 220
7.14.54 MAC PCU Generic Timers 2 (WMAC_PCU_GENERIC_TIMERS2) . . . . . 220
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet
Contents
 80-Y7991-1 Rev. C
12
7.14.55 MAC PCU Generic Timers Mode 2 (WMAC_PCU_GENERIC_TIMERS2_ MODE) 220
7.14.56 SIFS,TxLatencyandACKShift(WMAC_PCU_TXSIFS) .............
7.14.57 TXOPforNon-QoSFrames(WMAC_PCU_TXOP_X) ................
7.14.58 TXOPforTID0to3(WMAC_PCU_TXOP_0_3) ....................
7.14.59 TXOPforTID4to7(WMAC_PCU_TXOP_4_7) ....................
7.14.60 TXOPforTID8to11(WMAC_PCU_TXOP_8_11) ..................
7.14.61 TXOPforTID0to3(WMAC_PCU_TXOP_12_15) ..................
7.14.62 Generic Timers (WMAC_PCU_GENERIC_TIMERS[0:15]) . . . . . . . . . . . .
7.14.63 Generic Timers Mode (WMAC_PCU_GENERIC_TIMERS_MODE) . . . . .
7.14.64 32KHzSleepMode(WMAC_PCU_SLP32_MODE) ..................
7.14.65 32KHzSleepWake(WMAC_PCU_SLP32_WAKE) ..................
7.14.66 32KHzSleepIncrement(WMAC_PCU_SLP32_INC) .................
7.14.67 SleepMIBSleepCount(WMAC_PCU_SLP_MIB1) ..................
7.14.68 SleepMIBCycleCount(WMAC_PCU_SLP_MIB2) ..................
7.14.69 SleepMIBControlStatus(WMAC_PCU_SLP_MIB3) ................
7.14.70 1μSClocks(1μS)..............................................
7.14.71 PHY Error Counter Continued (PHY_ERR_CNT_MASK_CONT) . . . . . . .
7.14.72 GlobalMode(WMAC_PCU_20_40_MODE) ........................
7.14.73 Difference RX_CLEAR Counter (WMAC_PCU_RX_CLEAR_DIFF_CNT) 227
7.14.74 Self Generated Antenna Mask (SELF_GEN_ANTENNA_MASK) . . . . . . .
7.14.75 Control Registers for Block BA Control Fields (WMAC_PCU_BA_BAR_ CONTROL) 228
7.14.76 Legacy PLCP Spoof (WMAC_PCU_LEGACY_PLCP_SPOOF) . . . . . . . . .
7.14.77 PHY Error Mask and EIFS Mask (WMAC_PCU_PHY_ERROR_MASK_
CONT) 229
7.14.78 TxTimer(WMAC_PCU_TX_TIMER) .............................
7.14.79 Alternate AES QoS Mute Mask (ALT_AES_MUTE_MASK) . . . . . . . . . . .
7.14.80 TSF2Lower32(TSF2_L32) .....................................
7.14.81 TSF2Upper32(TSF2_U32) .....................................
7.14.82 BSSID2Upper16(BSSID2_U16) ................................
7.14.83 TID Value Access Category (WMAC_PCU_TID_TO_AC) . . . . . . . . . . . . .
7.14.84 High Priority Queue Control (WMAC_PCU_HP_QUEUE) . . . . . . . . . . . . .
7.14.85 HardwareBeaconProcessing1(HW_BCN_PROC1) ..................
7.14.86 HardwareBeaconProcessing2(HW_BCN_PROC2) ..................
7.14.87 KeyCache(WMAC_PCU_KEY_CACHE[0:1023]) ...................
7.15 PMURegisters ......................................................... 7.15.1 PMU1 ....................................................... 7.15.2 PMU2 .......................................................
7.16 PLLSRIFRegisters .....................................................
7.16.1 DPLL........................................................
7.16.2 DPLL2.......................................................
7.16.3 DPLL3.......................................................
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.17 PCIEConfigurationSpaceRegisters ........................................ 239
7.17.1 VendorID .................................................... 239
7.17.2 DeviceID .................................................... 240
7.17.3 Command .................................................... 240
7.17.4 Status........................................................241
7.17.5 RevisionID ................................................... 241
7.17.6 ClassCode.................................................... 241
7.17.7 ClassLineSize ................................................ 242
7.17.8 MasterLatencyTimer ........................................... 242
7.17.9 HeaderType .................................................. 242
7.17.10 BaseAddress0(BAR0) ......................................... 242
7.17.11 BAR0Mask................................................... 243
7.17.12 BusNumber .................................................. 243
7.17.13 SecondaryStatus ............................................... 244
7.17.14 MemoryBase ................................................. 244
7.17.15 MemoryLimit ................................................. 244
7.17.16 PrefetchableMemoryBase ....................................... 245
7.17.17 PrefetchableMemoryLimit ...................................... 245
7.17.18 CapabilityPointer .............................................. 245
7.17.19 InterruptLine ................................................. 245
7.17.20 InterruptPin .................................................. 246
7.17.21 BridgeControl................................................. 246
7.18 PCIERCPHYRegisters ................................................. 247
7.18.1 PLLDivision(DPLL) ........................................... 247
7.18.2 PLLDivision2(DPLL2) ........................................ 248
7.18.3 PLLDivision3(DPLL3) ........................................ 248
7.19 PCIERC0PHYRegisters ................................................ 249 7.19.1 PCIEPHY1(PCIE_PHY_REG_1) ................................ 249 7.19.2 PCIEPHY2(PCIE_PHY_REG_2) ................................ 250 7.19.3 PCIEPHY3(PCIE_PHY_REG_3) ................................ 251
7.20 GMAC0/GMAC1Registers............................................... 252
7.20.1 MACConfiguration1 ........................................... 255
7.20.2 MACConfiguration2 ........................................... 256
7.20.3 IPG/IFG...................................................... 257
7.20.4 Half-Duplex .................................................. 258
7.20.5 MaximumFrameLength ........................................ 258
7.20.6 MIIConfiguration .............................................. 259
7.20.7 MIICommand................................................. 260
7.20.8 MIIAddress .................................................. 260
7.20.9 MIIControl ................................................... 260
7.20.10 MIIStatus .................................................... 261
7.20.11 MIIIndicators ................................................. 261
7.20.12 InterfaceControl ............................................... 262
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.20.13 InterfaceStatus ................................................ 263
7.20.14 STAAddress1 ................................................ 264
7.20.15 STAAddress2 ................................................ 264
7.20.16 ETH_FIFORAMConfiguration0 ................................. 264
7.20.17 ETHConfiguration1 ........................................... 265
7.20.18 ETHConfiguration2 ........................................... 266
7.20.19 ETHConfiguration3 ........................................... 266
7.20.20 ETHConfiguration4 ........................................... 267
7.20.21 ETHConfiguration5 ........................................... 268
7.20.22 Tx/Rx64ByteFrameCounter(TR64) .............................. 268
7.20.23 Tx/Rx65-127ByteFrameCounter(TR127) ......................... 269
7.20.24 Tx/Rx128-255ByteFrameCounter(TR255) ........................ 269
7.20.25 Tx/Rx256-511ByteFrameCounter(TR511) ........................ 269
7.20.26 Tx/Rx512-1023ByteFrameCounter(TR1K) ........................ 270
7.20.27 Tx/Rx1024-1518ByteFrameCounter(TRMAX) .................... 270
7.20.28 Tx/Rx1519-1522ByteVLANFrameCounter(TRMGV) .............. 270
7.20.29 ReceiveByteCounter(RXBT) .................................... 271
7.20.30 ReceivePacketCounter(RPKT) .................................. 271
7.20.31 ReceiveFCSErrorCounter(RFCS) ................................ 271
7.20.32 ReceiveMulticastPacketCounter(RMCA).......................... 272
7.20.33 ReceiveBroadcastPacketCounter(RBCA).......................... 272
7.20.34 ReceiveControlFramePacketCounter(RXCF) ...................... 272
7.20.35 ReceivePauseFramePacketCounter(RXPF) ........................ 273
7.20.36 ReceiveUnknownOPCodePacketCounter(RXUO) .................. 273
7.20.37 ReceiveAlignmentErrorCounter(RALN) .......................... 273
7.20.38 ReceiveFrameLengthErrorCounter(RFLR) ........................ 274
7.20.39 ReceiveCodeErrorCounter(RCDE)............................... 274
7.20.40 ReceiveCarrierSenseErrorCounter(RCSE) ........................ 274
7.20.41 ReceiveUndersizePacketCounter(RUND) ......................... 275
7.20.42 ReceiveOversizePacketCounter(ROVR) .......................... 275
7.20.43 ReceiveFragmentsCounter(RFRG) ............................... 275
7.20.44 ReceiveJabberCounter(RJBR) ................................... 276
7.20.45 ReceiveDroppedPacketCounter(RDRP) ........................... 276
7.20.46 TransmitByteCounter(TXBT) ................................... 276
7.20.47 TransmitPacketCounter(TPKT) .................................. 277
7.20.48 TransmitMulticastPacketCounter(TMCA) ......................... 277
7.20.49 TransmitBroadcastPacketCounter(TBCA) ......................... 277
7.20.50 TransmitPauseControlFrameCounter(TXPF) ...................... 278
7.20.51 TransmitDeferralPacketCounter(TDFR)........................... 278
7.20.52 TransmitExcessiveDeferralPacketCounter(TEDF) .................. 278
7.20.53 TransmitSingleCollisionPacketCounter(TSCL) .................... 279
7.20.54 TransmitMultipleCollisionPacket(TMCL) ......................... 279
7.20.55 TransmitLateCollisionPacketCounter(TLCL) ...................... 279
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet
Contents
 7.20.56 TransmitExcessiveCollisionPacketCounter(TXCL) .................
7.20.57 TransmitTotalCollisionCounter(TNCL) ...........................
7.20.58 TransmitPauseFramesHonoredCounter(TPFH) .....................
7.20.59 TransmitDropFrameCounter(TDRP) .............................
7.20.60 TransmitJabberFrameCounter(TJBR) .............................
7.20.61 TransmitFCSErrorCounter(TFCS) ...............................
7.20.62 TransmitControlFrameCounter(TXCF) ...........................
7.20.63 TransmitOversizeFrameCounter(TOVR) ..........................
7.20.64 TransmitUndersizeFrameCounter(TUND) .........................
7.20.65 TransmitFragmentCounter(TFRG) ...............................
7.20.66 CarryRegister1(CAR1) ........................................
7.20.67 CarryRegister2(CAR2) ........................................
7.20.68 CarryMaskRegister1(CAM1) ...................................
7.20.69 CarryMaskRegister2(CAM2) ...................................
7.20.70 DMA TransferControlforQueue0(DMATXCNTRL_Q0) .............
7.20.71 DescriptorAddressforQueue0Tx(DMATXDESCR_Q0) .............
7.20.72 TransmitStatus(DMATXSTATUS) ................................
7.20.73 ReceiveControl(DMARXCTRL) .................................
7.20.74 PointertoReceiveDescriptor(DMARXDESCR) .....................
7.20.75 ReceiveStatus(DMARXSTATUS) ................................
7.20.76 InterruptMask(DMAINTRMASK) ................................
7.20.77 Interrupts(DMAINTERRUPT) ...................................
7.20.78 EthernetTXBurst(ETH_ARB_TX_BURST) ........................
7.20.79 CurrentTxandRxFIFODepth(ETH_XFIFO_DEPTH) ...............
7.20.80 Ethernet Transmit FIFO Throughput (ETH_TXFIFO_TH) . . . . . . . . . . . . . .
7.20.81 EthernetReceiveFIFOThreshold(ETH_RXFIFO_TH) ................
7.20.82 EthernetFreeTimer(ETH_FREE_TIMER)..........................
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 80-Y7991-1 Rev. C
7.20.89 DMA Transfer Arbitration Configuration (DMATXARBCFG) . . . . . . . . . . .
7.20.90 Tx Status and Packet Count for Queues 1 to 3 (DMATXSTATUS_123) . . . .
7.20.91 LocalMACAddressDword0(LCL_MAC_ADDR_DW0) ..............
7.20.92 LocalMACAddressDword1(LCL_MAC_ADDR_DW1) ..............
7.20.93 Next Hop Router MAC Address Dword0 (NXT_HOP_DST_ADDR_DW0)
7.20.94 Next Hop Router MAC Destination Address Dword1 (NXT_HOP_DST_
ADDR_DW1) 296
7.20.95 LocalGlobalIP Address0(GLOBAL_IP_ADDR0) ...................
7.20.96 LocalGlobalIP Address1(GLOBAL_IP_ADDR1) ...................
7.20.97 LocalGlobalIP Address2(GLOBAL_IP_ADDR2) ...................
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7.20.83 DMA Transfer Control for Queue 1 (DMATXCNTRL_Q1)
7.20.84 Descriptor Address for Queue 1 Tx (DMATXDESCR_Q1)
7.20.85 DMA Transfer Control for Queue 2 (DMATXCNTRL_Q2)
7.20.86 Descriptor Address for Queue 2 Tx (DMATXDESCR_Q2)
7.20.87 DMA Transfer Control for Queue 3 (DMATXCNTRL_Q3)
7.20.88 Descriptor Address for Queue 3 Tx (DMATXDESCR_Q3)
.............
.............
.............
.............
.............
.............
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.20.98 LocalGlobalIP Address3(GLOBAL_IP_ADDR3) ................... 297 7.21 SerialFlashSPIControllerRegisters........................................ 298
7.21.1 SPI Controller GPIO Mode Select (FUNCTION_SELECT_ADDR) . . . . . . 298
7.21.2 SPIAddressControl(SPI_CONTROL_ADDR) ...................... 298
7.21.3 SPII/OAddressControl(SPI_IO_CONTROL_ADDR) ................ 299
7.21.4 SPIReadDataAddress(SPI_READ_DATA_ADDR) .................. 299
7.21.5 SPIDatatoShiftOut(SPI_SHIFT_DATAOUT_ADDR) ............... 299
7.21.6 SPIContenttoShiftOutorIn(SPI_SHIFT_CNT_ADDR) .............. 300
7.21.7 SPIDatatoShiftIn(SPI_SHIFT_DATAIN_ADDR)................... 300
7.22 EthernetSwitchRegisters ................................................ 301 7.23 GlobalControlRegisters ................................................. 302
7.23.1 MaskControl.................................................. 302
7.23.2 OperationalMode0 ............................................ 303
7.23.3 OperationalMode1 ............................................ 303
7.23.4 GlobalInterrupt................................................ 304
7.23.5 GlobalInterruptMask ........................................... 305
7.23.6 GlobalMACAddress ........................................... 306
7.23.7 LoopCheckResult ............................................. 306
7.23.8 FloodMask ................................................... 307
7.23.9 GlobalControl................................................. 308
7.23.10 FlowControl0 ................................................ 309
7.23.11 FlowControl1 ................................................ 309
7.23.12 QMControl...................................................309
7.23.13 VLANTableFunction0 ......................................... 311
7.23.14 VLANTableFunction1 ......................................... 311
7.23.15 AddressTableFunction0 ........................................ 312
7.23.16 AddressTableFunction1 ........................................ 313
7.23.17 AddressTableFunction2 ........................................ 313
7.23.18 AddressTableControl .......................................... 314
7.23.19 IPPriorityMapping2 ........................................... 315
7.23.20 TagPriorityMapping ........................................... 317
7.23.21 ServiceTag ................................................... 317
7.23.22 CPUPort ..................................................... 317
7.23.23 LPI..........................................................318
7.23.24 MIBFunction0................................................318
7.23.25 MDIOControl................................................. 319
7.23.26 LEDControl .................................................. 319
7.24 PortControlRegisters ................................................... 321
7.24.1 PortStatus .................................................... 321
7.24.2 PortControl................................................... 322
7.24.3 Port-BasedVLAN.............................................. 324
7.24.4 Port-BasedVLAN2 ............................................ 325
7.24.5 RateLimit .................................................... 326
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 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
  80-Y7991-1 Rev. C
7.24.6 PriorityControl ................................................ 327
7.24.7 StormControl ................................................. 327
7.24.8 QueueControl ................................................. 328
7.24.9 RateLimit1 .................................................. 329
7.24.10 RateLimit2 .................................................. 330
7.24.11 RateLimit3 .................................................. 330
7.24.12 Robin........................................................331
7.24.13 LPIControl ................................................... 331
7.25 PHYControlRegisters................................................... 332
7.25.1 Control ...................................................... 332
7.25.2 Status........................................................334
7.25.3 PHYIdentifier.................................................335
7.25.4 PHYIdentifier2 ............................................... 335
7.25.5 Auto-NegotiationAdvertisement .................................. 335
7.25.6 LinkPartnerAbility ............................................ 337
7.25.7 Auto-negotiationExpansion ...................................... 338
7.25.8 MMDAccessControl ........................................... 338
7.25.9 MMDAccessAddressData ...................................... 338
7.25.10 FunctionControl ............................................... 339
7.25.11 PHYSpecificStatus ............................................ 340
7.25.12 InterruptEnable................................................ 341
7.25.13 InterruptStatus ................................................ 342
7.25.14 SmartSpeed .................................................. 343
7.25.15 ReceiveErrorCounter .......................................... 343
7.25.16 VirtualCableTesterControl ...................................... 343
7.25.17 VirtualCableTesterStatus ....................................... 344
7.25.18 DebugPort(AddressOffset)...................................... 344
7.25.19 DebugPort2(RWPort) ......................................... 344
7.26 DebugPortRegisters .................................................... 345
7.26.1 AnalogTestControl ............................................ 345
7.26.2 SystemModeControl ........................................... 346
7.26.3 HibernateControl .............................................. 346
7.26.4 100Base-TxTestModeSelect .................................... 347
7.26.5 10Base-TxTestModeSelect ..................................... 347
7.26.6 PowerSavingControl ........................................... 348
7.26.7 PHYControl .................................................. 348
7.26.8 CABLE_LTH_DETECT_DEBUG1 ................................ 348
7.27 MMD3PCSRegisters ................................................... 349
7.27.1 PCSControl1 ................................................. 349
7.27.2 PCSStatus1 .................................................. 349
7.27.3 EEECapability ................................................ 350
7.27.4 EEEWakeErrorCounter ........................................ 350
7.28 MMD7Auto-NegotiationRegisters......................................... 351
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 10
80-Y7991-1 Rev. C
8
7.28.1 Auto-Negotiation .............................................. 351
7.28.2 Auto-NegotiationStatus ......................................... 351
7.28.3 EEEAdvertisement............................................. 352
7.28.4 EEELP Advertisement .......................................... 352
7.28.5 EEEAbilityAuto-NegotiationResult............................... 352
EthernetSubsystem ..................................................... 353
8.1 GMAC0andGMAC1 ................................................... 353
8.2 EthernetSwitch ........................................................ 354
8.3 Five-PortEthernetSwitch ................................................ 354
8.3.1 Overview.....................................................355
8.3.2 BasicSwitchOperation.......................................... 356
8.3.3 MediaAccessControllers(MAC) ................................. 356
8.3.4 ACL.........................................................356
8.3.5 RegisterAccess ................................................ 357
8.3.6 LEDControl .................................................. 358
8.3.7 VLANs ...................................................... 359
8.3.8 IEEEPortSecurity ............................................. 359
8.3.9 Mirroring.....................................................359
8.3.10 Broadcast/Multicast/UnknownUnicast ............................. 360
8.3.11 IGMP/MLDSnooping .......................................... 360
8.3.12 SpanningTree ................................................. 360
8.3.13 MIB/StatisticsCounters ......................................... 361
8.3.14 QualcommAtherosHeaderConfiguration ........................... 363
8.3.15 IEEE802.3ReservedGroupAddressesFilteringControl ............... 363
8.3.16 PPPoEHeaderRemoval ......................................... 364
8.4 EthernetCoreReset ..................................................... 365
ElectricalCharacteristics ................................................ 366
9.1 AbsoluteMaximumRatings .............................................. 366
9.2 RecommendedOperatingConditions ....................................... 366
9.3 RadioCharacteristics .................................................... 367
9.3.1 RadioReceiverCharacteristics .................................... 367
9.3.2 TransmitterCharacteristics ....................................... 368
9.3.3 SynthesizerCharacteristics ....................................... 369
9.4 PowerConsumption ..................................................... 369
9.5 ACSpecifications ...................................................... 370
9.5.1 SPITiming ................................................... 370
9.5.2 DDRTiming .................................................. 371
9.5.3 DDRTimingInput ............................................. 372
9.5.4 ResetTiming .................................................. 372
PartReliability ........................................................... 373 10.1 ReliabilityQualificationsSummary ......................................... 373
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9
 
 QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms Data Sheet Contents
 10.2 QualificationSampleDescription .......................................... 374 11 PackageDimensions .................................................... 375 12 OrderingInformation .................................................... 377