实例介绍
【实例简介】
fm1288音频处理，回声消除配置样例，及配置手册，
TABLE OF CONTENT STATUS INFORMATION∴ 1■■■ 1 INTRODUCTION 1. I OvERVIEW 4888 L2 KEY FEATURES 1.3 PIN CONFIGURATION (LQFP) 1. 4 DEVICE TERMINAL FUNCTIONS 10 1. 5 INTERNAL HARDWARE BLOCK DIAGRAM 13 1. 6 SYSTEM APPLICATION BLOCK DIAGRAM 14 2. FUNcTIONAL DESCRIPTION mmm 16 2.1 OVERVIEW .16 2.2 SERIAL EEPROM INTERFACE(PINS 15,16) .16 2.3 UART INTERFACE (PINS 12,13) 21 2. 4 IIC COMPATIBLE SERIAL HOST INTERFACE-SHI(PINS 23, 24) ·中· ············ 2.5 DIGITAL VOICE DATA INTERFACES(PINS 8, 9, 10, 11)......25 2.5.1 PCM INTERFACE MASTER/SLAVE 25.2 IS INTERFACE 7 2.6ADC(PNS39,40,41,42,43,44) 32 2.7DAC(PINs1,3,47,48).…… 33 2. 8 MODES OF OPERATION 34 2.9 POWER-UP STAP OPTION (PIN 17 ······· .36 2. 10 MUTE CONTROL AND INDICATION (PINS 20, 21) 2. 11 SYSTEM CLOCK INPUT AND GENERATION(PINS 27,2e)"...... 2.11 SPEAKER VOLUME CONTROL (PINS 25, 26) 37 2. 12 BYPASS MODE (PIN 14) 38 3. ACCESSING FM1288 THROUGH EEPROM, UART SHIm.39 3.1 ACCESSING TIIROUGII EEPROM 40 3.2 EXAMPLES OF ACCESSING THROUGH EEPROM 41 3. 3 ACCESSING THROUGH UART 42 3.4 EXAMPLES OF ACCESSING THROUGH UART 42 3. 5 ACCESSING THROUGH SHI 43 3.6 EXAMPLES OF ACCESSING THROUGH SHI.............................43 4 ELECTRICAL AND TIMING SPECIFICATION 44 4.1 ABSOLUTE MAXIMUM RATINGS……. 4.2 RECOMMENDED OPERATING CONDITIONS 45 4.3 DC CHARACTERISTICS…………………… …146 4. 4 AC CHARACTERISTICS 47 4.5 TIMING CHARACTERISTICS 49 5. VOICE PROCESSOR PERFORMANCE DETAILS 6. PIN DEFINITION DETAILS …56 7. PACKAGE DIMENSIONS(LQFP)mee aImRaaEmI 58 8. ORDERING INFORMATION 61 APPENDIX I: REQUIRED EXTERNAL COMPONENTS FOR OPERATIONmmmaamammmmamam 62 REFERENCES …64 Ⅰ. TERMINOLOGY.… ……64 IL RELATED DOCUMENTS ····申 64 IP a g Status information The status of this product data sheet is product information Advance information Information for designers concerning Fortemedia product in development. All values specified in the document are the target values of the design. Minimum and maximum values, if specified, are only given as guidance to the final specification limits and must not be considered as the final values All detailed specifications including pinouts and electrical specifications may be changed by Fortemedia without notice Pre-production Information Pinout and mechanical dimension specifications finalized. All values specified in the document are the target values of the design. Minimum and maximum values if specified are only given as guidance to the final specification limits and must not be considered as the final values All electrical specifications may be changed by Fortemedia without notice Product information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications Product Data Sheets supersede all previous document versions. Note While every case has been taken to ensure the accuracy of the contents in this data Sheet Fortemedia cannot accept responsibility for any errors. fortemedia reserves the right to make technical changes to its products as part of its development program. pAge FIGURES Figure1:LQFP48- Pin Configuration- Top view.……..… Figure 2: IC Hardware Block Diagram.…,…,…,,…, 13 Figure 3: Example bluetooth Application Block Diagrams 14 Figure 4: FM-1288 as an example Stand-alone Minimal System 15 Figure 5: Example UART Command Protocol..... 22 Figure 6: UART Data Transfers (tX and rx)......... 22 Figure 7: SHI Data Transfer Command Protocol 23 Figure8: SHI Command sequence,…,,,,…,,,, 24 Figure9: IIS Falling edge Latch, LRCK High for Left Channel,1 Cycle delay,,…,…,……,27 Figure 10: IIS Falling Edge Latch, LRCK High for Left Channel, 0 Cycle Delay 28 Figure 11: IIS Falling Edge Latch, LRCK High for Right Channel, 1 Cycle delay.. 28 Figure12: IIS Falling Edge Latch, LRCK High for Right Channel,0 ycle delay…,…,…,,…,29 Figure 13: IIS Rising Edge Latch, LRCK High for Left Channel, 1 Cycle delay 29 Figure14: Iis Rising Edge Latch, LRCK High for Left Channel, 0 Cycle Delay………,……,30 Figure 15: IIS Rising Edge Latch LRCK High for Right Channel, 1 Cycle Delay Figure 16: IIS Rising Edge Latch LRCK High for Right Channel, 0 Cycle delay.. 31 Figure17: Analog-to- Digital Converter Block Diagram……………….…………………,32 Figure18: Digital-to-Analog Converter Block Diagram,…,…,,…,…,,…,…, 33 Figure 19: State Transition diagram 35 Figure 20: Accessing FM1288. ■重重重重1■ 39 Figure 21: Command Entry Data Pattern ∴39 Figure22: Timing Chart: Normal power- Up Sequence.,...,,,…,,…,,,,…,…50 Figure 23: Timing Chart: Reset while in Hardware reset .51 Figure 24: Timing Chart: RESET while in Software Reset, Operational, and Power Down 52 Figure 25: Timing Chart: PWD and state transition 1国重 Figure 26: Master Clock(MCLK) Timing 54 Figure 27: Shi Timing ■重重1面日D日面量面面量面重■ 54 Figure28:48- pin lqFp Package Drawing and dimensions………,,,…,…,,…,,,,…,58 Figure 29: 48-pin LQFP Package Side view 59 Figure30:48 pin lQFp Package on Fm-1288.……… 面■面面面量面1面国面B重 60 Figure 31: External CrystalyOscillator as Clock Source 62 pIPage TABLES Table 1: Shi StaRT and stop data transition 23 Table 2: shi command name Table 3: SHI Command Byte -format 24 Table 4: SHI Command Byte-bit definition 24 Table 5: Digital Voice Data Interface( Pins 8, 9, 10, 11) 25 Table 6: aDc mic in and line IN PGa controls wmwm 32 Table 7: dac line out and spk out Pga controls 33 Table 8: Strap Option Pins to Select Operation Mode. 36 Table 9: Command entries 39 Table 10: Examples of Accessing through EEPROM 41 Table 11: Examples of Accessing through UART 42 Table 12: SHI Command Symbols 重1 43 Tabe13: Examples吖 Accessing through SHI…,,…,,,…,……………43 Table 14: Absolute Maximum Ratings for FM1288-GA1-410 44 Table 15: Absolute Maximum Ratings for FM1288-GE-410 44 Table 16: Absolute Maximum Ratings for fM1288-GA1-400B and fm1288-GE-400B 44 Table 17: Recommended operating conditions for FM1288-GA1-410 45 Table 18: Recommended operating Conditions for FM1288-GE-410 45 Table 19: Recommended Operating Conditions for 45 Table 20: dc characteristics 46 Table 21: ac characteristics n47 Table 22: ADC PGA (MICO_IN, MIC1_ IN, LINE_ IN) 48 Tabe23: DAC PGA(LINE_OUT,SPK_OUT)…………… 48 Table24: Timing Characteristics………,……,…,……,…………………49 Table 25: Voice processor performance details BBI..I 55 Table 26: Pin description 56 Tabe27: Available Packages and Temperature grade…,,……,,,…,,,,…,,,,…,61 Table 28: External Components recommendations 1重重量量面1面1■量量1面重 62 Tabe29: Terminology.......,.,.,,,,,…,,,,.64 Table 30: Related documents 64 6P age Document History Revision Date Description 0.1 Oct 30, 2011 Early Draft, original publication date 0.2 Nov2,2011 Editorial updates 1 draft Advance Information 0.3 Nov5,2011 Editorial updates 0.4 Nov25,2011 Editorial updates, initial release after 2 mic support added 0.5 Mar31,2012 Editorial updates, analog design spec changed on 3/16 0.6 Ap18,2012 Editorial update, after reviews in NJ 0.7 Apr28,2012 Editorial update, after reviews with digital, analog, software 0.8 June20,2012 Editorial update after SQa measurement and updates 091uy04,2012 O.He,AZhang, H Liu, et al updates and edits 1.0 Sep30,2012 O. He, A Zhang h. Liu et al revised updates and edits 1.1 DeC27,2012 Editorial update, after clarification about mic-inputs 1.2 Dec29,2012 Editorial update and clarified some details 1.3 Jan02,2013 Updates based on fab data and testings 1.4 Jan10,2013 Updates on current ratings and crystal related 1.5 Mar31,2013 FM-1288-GA1-410 and Uart format correction 1.6 Apr05,2013 Improved top/side view diagrams 1.7 Jun10,2013 Editorial corrections on Figure 20 and Table 22 18 July09,2013 Clarified Figure 22 and expanded into Fig 22a, b, c; corrected Fig. 19 and sec 2.8; revised related items 1.9 Juy16,2013 Added Timing Chart for Power Down 2.0 Oct31,2013 Corrected, and clarified voltage supply details for FM1288-GA1-400B FM1288-GE-400B,FM1288-GA1-410, and fm1288-GE410 2.1 Jun19,2014 Corrected and clarified Table 21 AC characteristics 2.2 Jan 06, 2015 Clarified VDd D and VDD A, pp 49 2.3 Jan 29, 2015 I2C max value, pp49 pAge 1. Introduction FM1288 is the new generation of Fortemedia's system-on-chip (SoC)solution that provides high performance voice processing for automotive hands-free applications. It delivers state of the art single microphone and dual-microphone noise suppression with acoustic echo cancellation technologies for in vehicle and personal navigation devices(pnd)based hands-free voice communications 11 Overview Incorporating the latest Fortemedia technologies for removing ambient noise and acoustic echoes, the FM1288 preserves voice naturalness for greater speech intelligibility in a variety of noisy automotive enviroments. Designed to be compatible with a wide range of host processors and blue-tooth devices the FM1288 voice processor is designed for easy system integration The FM1288 provides system designer the flexibilities to customize each processing module and fine-tune the algorithms to the unique needs and acoustic path characteristics of the manufacturer's automotive model cabin or handsfree communication device 1.2 Key Features Highly integrated soc o Digital Signal Processor(dSP)with Hardware Accelerators RAM, and rom o 3 ADC (Analog to Digital Converter) o 2 DAC(Digital to Analog Converter) o Differential i o on all analogs to improve noise immunit 2 On-chip analog microphone inputs IIC-Compatible Serial (SHi) and UART control interface to host processor o IIS-Compatible and pCm data interface to host or bluetooth processor o Built-in PLL supports highly flexible clocking input o Can operate as Co-processor or as standalone processor High performance o Advanced algorithms for acoustic echo cancellation and noise reduction Robust full-duplex for in-vehicle applications o Preserves voice naturalness and effective in automotive environment o Wideband(hd voice and narrowband voice processing o Bright Voice Enhancement(BVE) for downlink listening improvement o Dynamic Range Control(DRC) for range control o Equalization(EQL) on uplink and downlink voice paths o Line in and Line out signal path automatic Gain Control (AGC) o Configurable processing modules performance o Non-invasive run-time performance tuning via UART and IIc-compatible port Run time switching between processing mode and various by-pass modes o User-selectable between two microphone inputs usage-one for front-seat passengers and another for back-seat passengers in vehicle cabins Available in 48-pin LQFP packages, Automotive Grade 8P a g 1.3 Pin Configuration (LQFP) 出9a口 z￥三 十 VDD C SDA VSS A MICO P VAD LED MIC0N囗 MUTE OUT MIC1 P MUTE IN MIC1 N VDD D LINE IN P OO LINE IN_N囗 GPIO VSS A O SCL EE VREF SDA EE LINE OUT P口 TEST2 Pin 1 SPK OUT_P囗 UART TX 廿凵 乙呈兰兰9总影 u Figure 1: LQFP 48-Pin Configuration-Top View 9P a g 1. 4 Device Terminal Functions Analog Audio I/O Lead Pad type Supply Description Domain LINE OUT N Analogue VDD A AudIo LINE OUTPUT () LINE OUT P Analogue VDD A Audio LINE OUTPUT (+ sPK。UTN Analogue VDD Audio SPEAKER OUTPUT(-) SPK QUT P 48 Analogue VDD A Audio SPEAKER OUTPUT (+) LINE IN N Analogue VDD A Audio LINE INPUT(-) LINE IN P 43 Analogue VDD A Audio LINE INPUT(+) MICO 40 Analogue VDD A Audio MIC INPUT(-) MICO P 39 Analogue VDD A Audio MIC INPUT (+) M工c1N 42 Analogue VDD A Audio MIC INPUT(-) MICI P 41 Analoque VDD Audio Mic INPut(+) oscilator and clock Lead Pad Type Supply Description Domain XTAL_ IN/MCLK_IN 27 Ial VDD D For crystal or external clock in XTAL OUT/MCLK_OUT 28 Digital VDD D Drive for crystal 0P a g 【实例截图】
【核心代码】
fm1288音频处理，回声消除配置样例，及配置手册，
TABLE OF CONTENT STATUS INFORMATION∴ 1■■■ 1 INTRODUCTION 1. I OvERVIEW 4888 L2 KEY FEATURES 1.3 PIN CONFIGURATION (LQFP) 1. 4 DEVICE TERMINAL FUNCTIONS 10 1. 5 INTERNAL HARDWARE BLOCK DIAGRAM 13 1. 6 SYSTEM APPLICATION BLOCK DIAGRAM 14 2. FUNcTIONAL DESCRIPTION mmm 16 2.1 OVERVIEW .16 2.2 SERIAL EEPROM INTERFACE(PINS 15,16) .16 2.3 UART INTERFACE (PINS 12,13) 21 2. 4 IIC COMPATIBLE SERIAL HOST INTERFACE-SHI(PINS 23, 24) ·中· ············ 2.5 DIGITAL VOICE DATA INTERFACES(PINS 8, 9, 10, 11)......25 2.5.1 PCM INTERFACE MASTER/SLAVE 25.2 IS INTERFACE 7 2.6ADC(PNS39,40,41,42,43,44) 32 2.7DAC(PINs1,3,47,48).…… 33 2. 8 MODES OF OPERATION 34 2.9 POWER-UP STAP OPTION (PIN 17 ······· .36 2. 10 MUTE CONTROL AND INDICATION (PINS 20, 21) 2. 11 SYSTEM CLOCK INPUT AND GENERATION(PINS 27,2e)"...... 2.11 SPEAKER VOLUME CONTROL (PINS 25, 26) 37 2. 12 BYPASS MODE (PIN 14) 38 3. ACCESSING FM1288 THROUGH EEPROM, UART SHIm.39 3.1 ACCESSING TIIROUGII EEPROM 40 3.2 EXAMPLES OF ACCESSING THROUGH EEPROM 41 3. 3 ACCESSING THROUGH UART 42 3.4 EXAMPLES OF ACCESSING THROUGH UART 42 3. 5 ACCESSING THROUGH SHI 43 3.6 EXAMPLES OF ACCESSING THROUGH SHI.............................43 4 ELECTRICAL AND TIMING SPECIFICATION 44 4.1 ABSOLUTE MAXIMUM RATINGS……. 4.2 RECOMMENDED OPERATING CONDITIONS 45 4.3 DC CHARACTERISTICS…………………… …146 4. 4 AC CHARACTERISTICS 47 4.5 TIMING CHARACTERISTICS 49 5. VOICE PROCESSOR PERFORMANCE DETAILS 6. PIN DEFINITION DETAILS …56 7. PACKAGE DIMENSIONS(LQFP)mee aImRaaEmI 58 8. ORDERING INFORMATION 61 APPENDIX I: REQUIRED EXTERNAL COMPONENTS FOR OPERATIONmmmaamammmmamam 62 REFERENCES …64 Ⅰ. TERMINOLOGY.… ……64 IL RELATED DOCUMENTS ····申 64 IP a g Status information The status of this product data sheet is product information Advance information Information for designers concerning Fortemedia product in development. All values specified in the document are the target values of the design. Minimum and maximum values, if specified, are only given as guidance to the final specification limits and must not be considered as the final values All detailed specifications including pinouts and electrical specifications may be changed by Fortemedia without notice Pre-production Information Pinout and mechanical dimension specifications finalized. All values specified in the document are the target values of the design. Minimum and maximum values if specified are only given as guidance to the final specification limits and must not be considered as the final values All electrical specifications may be changed by Fortemedia without notice Product information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications Product Data Sheets supersede all previous document versions. Note While every case has been taken to ensure the accuracy of the contents in this data Sheet Fortemedia cannot accept responsibility for any errors. fortemedia reserves the right to make technical changes to its products as part of its development program. pAge FIGURES Figure1:LQFP48- Pin Configuration- Top view.……..… Figure 2: IC Hardware Block Diagram.…,…,…,,…, 13 Figure 3: Example bluetooth Application Block Diagrams 14 Figure 4: FM-1288 as an example Stand-alone Minimal System 15 Figure 5: Example UART Command Protocol..... 22 Figure 6: UART Data Transfers (tX and rx)......... 22 Figure 7: SHI Data Transfer Command Protocol 23 Figure8: SHI Command sequence,…,,,,…,,,, 24 Figure9: IIS Falling edge Latch, LRCK High for Left Channel,1 Cycle delay,,…,…,……,27 Figure 10: IIS Falling Edge Latch, LRCK High for Left Channel, 0 Cycle Delay 28 Figure 11: IIS Falling Edge Latch, LRCK High for Right Channel, 1 Cycle delay.. 28 Figure12: IIS Falling Edge Latch, LRCK High for Right Channel,0 ycle delay…,…,…,,…,29 Figure 13: IIS Rising Edge Latch, LRCK High for Left Channel, 1 Cycle delay 29 Figure14: Iis Rising Edge Latch, LRCK High for Left Channel, 0 Cycle Delay………,……,30 Figure 15: IIS Rising Edge Latch LRCK High for Right Channel, 1 Cycle Delay Figure 16: IIS Rising Edge Latch LRCK High for Right Channel, 0 Cycle delay.. 31 Figure17: Analog-to- Digital Converter Block Diagram……………….…………………,32 Figure18: Digital-to-Analog Converter Block Diagram,…,…,,…,…,,…,…, 33 Figure 19: State Transition diagram 35 Figure 20: Accessing FM1288. ■重重重重1■ 39 Figure 21: Command Entry Data Pattern ∴39 Figure22: Timing Chart: Normal power- Up Sequence.,...,,,…,,…,,,,…,…50 Figure 23: Timing Chart: Reset while in Hardware reset .51 Figure 24: Timing Chart: RESET while in Software Reset, Operational, and Power Down 52 Figure 25: Timing Chart: PWD and state transition 1国重 Figure 26: Master Clock(MCLK) Timing 54 Figure 27: Shi Timing ■重重1面日D日面量面面量面重■ 54 Figure28:48- pin lqFp Package Drawing and dimensions………,,,…,…,,…,,,,…,58 Figure 29: 48-pin LQFP Package Side view 59 Figure30:48 pin lQFp Package on Fm-1288.……… 面■面面面量面1面国面B重 60 Figure 31: External CrystalyOscillator as Clock Source 62 pIPage TABLES Table 1: Shi StaRT and stop data transition 23 Table 2: shi command name Table 3: SHI Command Byte -format 24 Table 4: SHI Command Byte-bit definition 24 Table 5: Digital Voice Data Interface( Pins 8, 9, 10, 11) 25 Table 6: aDc mic in and line IN PGa controls wmwm 32 Table 7: dac line out and spk out Pga controls 33 Table 8: Strap Option Pins to Select Operation Mode. 36 Table 9: Command entries 39 Table 10: Examples of Accessing through EEPROM 41 Table 11: Examples of Accessing through UART 42 Table 12: SHI Command Symbols 重1 43 Tabe13: Examples吖 Accessing through SHI…,,…,,,…,……………43 Table 14: Absolute Maximum Ratings for FM1288-GA1-410 44 Table 15: Absolute Maximum Ratings for FM1288-GE-410 44 Table 16: Absolute Maximum Ratings for fM1288-GA1-400B and fm1288-GE-400B 44 Table 17: Recommended operating conditions for FM1288-GA1-410 45 Table 18: Recommended operating Conditions for FM1288-GE-410 45 Table 19: Recommended Operating Conditions for 45 Table 20: dc characteristics 46 Table 21: ac characteristics n47 Table 22: ADC PGA (MICO_IN, MIC1_ IN, LINE_ IN) 48 Tabe23: DAC PGA(LINE_OUT,SPK_OUT)…………… 48 Table24: Timing Characteristics………,……,…,……,…………………49 Table 25: Voice processor performance details BBI..I 55 Table 26: Pin description 56 Tabe27: Available Packages and Temperature grade…,,……,,,…,,,,…,,,,…,61 Table 28: External Components recommendations 1重重量量面1面1■量量1面重 62 Tabe29: Terminology.......,.,.,,,,,…,,,,.64 Table 30: Related documents 64 6P age Document History Revision Date Description 0.1 Oct 30, 2011 Early Draft, original publication date 0.2 Nov2,2011 Editorial updates 1 draft Advance Information 0.3 Nov5,2011 Editorial updates 0.4 Nov25,2011 Editorial updates, initial release after 2 mic support added 0.5 Mar31,2012 Editorial updates, analog design spec changed on 3/16 0.6 Ap18,2012 Editorial update, after reviews in NJ 0.7 Apr28,2012 Editorial update, after reviews with digital, analog, software 0.8 June20,2012 Editorial update after SQa measurement and updates 091uy04,2012 O.He,AZhang, H Liu, et al updates and edits 1.0 Sep30,2012 O. He, A Zhang h. Liu et al revised updates and edits 1.1 DeC27,2012 Editorial update, after clarification about mic-inputs 1.2 Dec29,2012 Editorial update and clarified some details 1.3 Jan02,2013 Updates based on fab data and testings 1.4 Jan10,2013 Updates on current ratings and crystal related 1.5 Mar31,2013 FM-1288-GA1-410 and Uart format correction 1.6 Apr05,2013 Improved top/side view diagrams 1.7 Jun10,2013 Editorial corrections on Figure 20 and Table 22 18 July09,2013 Clarified Figure 22 and expanded into Fig 22a, b, c; corrected Fig. 19 and sec 2.8; revised related items 1.9 Juy16,2013 Added Timing Chart for Power Down 2.0 Oct31,2013 Corrected, and clarified voltage supply details for FM1288-GA1-400B FM1288-GE-400B,FM1288-GA1-410, and fm1288-GE410 2.1 Jun19,2014 Corrected and clarified Table 21 AC characteristics 2.2 Jan 06, 2015 Clarified VDd D and VDD A, pp 49 2.3 Jan 29, 2015 I2C max value, pp49 pAge 1. Introduction FM1288 is the new generation of Fortemedia's system-on-chip (SoC)solution that provides high performance voice processing for automotive hands-free applications. It delivers state of the art single microphone and dual-microphone noise suppression with acoustic echo cancellation technologies for in vehicle and personal navigation devices(pnd)based hands-free voice communications 11 Overview Incorporating the latest Fortemedia technologies for removing ambient noise and acoustic echoes, the FM1288 preserves voice naturalness for greater speech intelligibility in a variety of noisy automotive enviroments. Designed to be compatible with a wide range of host processors and blue-tooth devices the FM1288 voice processor is designed for easy system integration The FM1288 provides system designer the flexibilities to customize each processing module and fine-tune the algorithms to the unique needs and acoustic path characteristics of the manufacturer's automotive model cabin or handsfree communication device 1.2 Key Features Highly integrated soc o Digital Signal Processor(dSP)with Hardware Accelerators RAM, and rom o 3 ADC (Analog to Digital Converter) o 2 DAC(Digital to Analog Converter) o Differential i o on all analogs to improve noise immunit 2 On-chip analog microphone inputs IIC-Compatible Serial (SHi) and UART control interface to host processor o IIS-Compatible and pCm data interface to host or bluetooth processor o Built-in PLL supports highly flexible clocking input o Can operate as Co-processor or as standalone processor High performance o Advanced algorithms for acoustic echo cancellation and noise reduction Robust full-duplex for in-vehicle applications o Preserves voice naturalness and effective in automotive environment o Wideband(hd voice and narrowband voice processing o Bright Voice Enhancement(BVE) for downlink listening improvement o Dynamic Range Control(DRC) for range control o Equalization(EQL) on uplink and downlink voice paths o Line in and Line out signal path automatic Gain Control (AGC) o Configurable processing modules performance o Non-invasive run-time performance tuning via UART and IIc-compatible port Run time switching between processing mode and various by-pass modes o User-selectable between two microphone inputs usage-one for front-seat passengers and another for back-seat passengers in vehicle cabins Available in 48-pin LQFP packages, Automotive Grade 8P a g 1.3 Pin Configuration (LQFP) 出9a口 z￥三 十 VDD C SDA VSS A MICO P VAD LED MIC0N囗 MUTE OUT MIC1 P MUTE IN MIC1 N VDD D LINE IN P OO LINE IN_N囗 GPIO VSS A O SCL EE VREF SDA EE LINE OUT P口 TEST2 Pin 1 SPK OUT_P囗 UART TX 廿凵 乙呈兰兰9总影 u Figure 1: LQFP 48-Pin Configuration-Top View 9P a g 1. 4 Device Terminal Functions Analog Audio I/O Lead Pad type Supply Description Domain LINE OUT N Analogue VDD A AudIo LINE OUTPUT () LINE OUT P Analogue VDD A Audio LINE OUTPUT (+ sPK。UTN Analogue VDD Audio SPEAKER OUTPUT(-) SPK QUT P 48 Analogue VDD A Audio SPEAKER OUTPUT (+) LINE IN N Analogue VDD A Audio LINE INPUT(-) LINE IN P 43 Analogue VDD A Audio LINE INPUT(+) MICO 40 Analogue VDD A Audio MIC INPUT(-) MICO P 39 Analogue VDD A Audio MIC INPUT (+) M工c1N 42 Analogue VDD A Audio MIC INPUT(-) MICI P 41 Analoque VDD Audio Mic INPut(+) oscilator and clock Lead Pad Type Supply Description Domain XTAL_ IN/MCLK_IN 27 Ial VDD D For crystal or external clock in XTAL OUT/MCLK_OUT 28 Digital VDD D Drive for crystal 0P a g 【实例截图】
【核心代码】
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