UVM_A Practical Guide to Adopting the Universal Verification Methodology(UVM)

【实例简介】
UVM介绍的很详细，未来验证方法学的发展趋势，希望对你有用
Contents Preface∴.,, ,。。。,。,,,,.;.a。Xv 1 What is the Universal Verification Methodology (UVM)? I Verification Planning and Coverage-Driven Verification 1.2 Multi-Language and methodologies 1. 3 what is Unique about this Book? 4 How to Use this book 1.4. 1 How to Run the Examples 1.4.2 Conventions in This book 1.4.3 Abbreviations 2 UVM Overview 2.1 UVM Testbench and environments 2.2 Interface UV Cs 2.3 System and module uvcs 14 2.3.1 Software uvcs I5 2.4 The System Verilog UVM Class Library 2.4.1 UM Utilities 18 3 Object-Oriented Programming(OOP) 21 3.1 Introduction 2 3.2 Designing Large Software Applications 3.3 What is an Object in OOP? 4 Distributed Development Environment 2 3.5 Separation of Concerns 23 3.6 Classes, Objects, and Programs 23 3. 7 Using Generalization and Inheritance 24 A Practica/ Guide to Adopting the Universal Verification Methodology (UVM) Contents 3. 8 Creating Compact Reusable Code 26 3.9 Polymorphism in OOP 26 3. 10 Downcast 3.11 Class libraries 画e .28 3.12 Static Methods and Attributes 29 3.13 Parameterized classes 29 3. 14 Packages and Namespaces 3. 15 Unified Modeling Language Diagrams 31 3.16 Software Design Patterns 32 3. 16.1 Software Design Anti-Patterns 33 3. 17 Why Isnt the Existing OOP Methodology enough? ,,33 3. 18 Aspect-Oriented Programming 34 4 UVM Library Basics 抽■邮幕靠漕 鲁■■鼻增■·》■邮《■ 35 4.1 Using the UVM Library 35 4. 1.1 Hello Worid example 36 4.1. 2 Guidelines for Using the UVM Library 6 4.2 Library base Classes 4.3 The uvm object Class 37 4.3.1 UVM Field Automation 4.3.2 uvm object Definition guidelines 4.3.3 UVM Obiect Automation Usage Examples 41 4.3. 4 Using UVM Field automation 42 4.4 The uvm component Class 43 4.4.1 Simulation phase methods 43 4. 4.2 Hierarchy Information Functions 4.4.3 uvm_top Component 49 4.5 UVM Configuration Mechanism 49 4.6 Transaction- Level Modeling in uVM 52 4.6.1 Key TLM Concepts in UVM ,,,53 4.7 UVM Fact 62 4.8 UVM Message Facilities 66 4.8.】 UVM Message APls 66 4.8.2 Guidelines for Using UVM Messages ,,67 4.8.3 Modifying Message Verbosity 4.9 Callbacks 4.9.I Using Callbacks 4.9.2 Guidelines for Using Callbacks 4.9.3 The Report Catcher Built-In Callback 71 A Practical Guide to Adopting the Universal venfication Methodology (UVM) Contcnts 5 Interface UVCs 73 5.1 Stimulus Modeling and generation 5.1.1 Modeling Data Items 5.1. 2 Defining Control Fields 75 5.1.3 Inheritance and Constraint Layering 76 5.1.4 Using Empty Constraint Blocks for Tests 77 5.1.5 A Simple data Item Test 77 5.2 Creating the Driver 5.2.1 The System Verilog Interface and Virtual Interface .,, 5.3 Creating the Sequencer 82 5.3.1 Key randomization Requirements 5.3.2 A Non-UVM GE 5.3.3 The UVM Sequencer 85 5.4 Connecting the Driver and Sequencer ,86 5. 4. 1 Basic Sequencer and Driver Interaction 5.4.2 Querying for the Randomized item 87 5.4.3 Supporting Pipeline Pi 88 5.4.4 Sending Processed Data Back to the Sequencer 89 5.5 Creating the Collector and monitor 89 Connecting the Collector and monitor 93 5.6 Modeling Topology with UVM 93 5.7 Creating the Agent 96 5.7.1 Using connect() to Connect Components 5.7.2 Agent Configuration ..99 5.8 Creating the uvm verification Component 5.8.1 The Environment Class 100 5.8.2 Point-to-Point environments .102 5.8.3 The UVM Configuration Mechanism 103 5.8.4 Setting the Agent Virtual Interface 107 5.9 Creating UVM Sequences 110 5.9. 1 User-Detined sequences 5.9.2 Predefined Sequences 5.10 Configuring the Sequencer's Default Sequence 116 5.10.1 Controlling the Sequencer and Generated Sequences 17 5. 10.2 Overriding sequence items and sequences l18 5.10.3 Building a reusable Sequence library 118 5.11 Coordinating End-of-Test 119 5.11.1 UVM Objection Mechanism ,,119 5.11.2 End-of-Test Objection Mechanism Usage A Practica/ Guide to Adopting the Universa/ verification Methodology (Uv/) Content 5. 11.3 Tracing Objection Information. ..... ,121 5.11. 4 Setting drain Time 122 5.11.5 Identifying Lack of Progress .,,,123 5.12 Implementing Protocol-Specific Coverage and Checks 127 5.12.1 Placing Coverage Groups 27 2. 2 Implementing Checks 5.12.3 Enabling and Disabling Coverage and Checks .130 5.12.4 Implementing Checks and Coverage in Interfaces 131 5.13 Handling Reset 132 5. 13.1 Reset Methodology for interface UVCs ...l32 5. 14 Packaging Interface UVCs ,135 5. 14.1 Interface UVC Directory Structure 135 5. 14.2 File naming conventions 136 5.14.3 UVC Packages ,136 6 Automating UVC Creation 139 6.1 UVC Development Flow 6.2 Code generators 6. 3 Compliance Checklist 144 6.4 Automated Compliance Checking 145 7 Simple Testbench Integration ......v..,..... 147 7. 1 Testbenches and Tests ,147 7. 1.I The Testbench class 148 1.2 The test classes 148 7. 2 Creating a Simple tes 149 7. 2.1 Instantiating UVCs in a Testbench 150 7.3 Testbench Configuration .,,,.153 7.3.1 UVC Configurable Parame 153 7.3.2 UVC Configuration Mechanism ,,153 7.3.3 Using a Configuration Class ,154 7. 4 Creating a Test 156 74』 Creating the Base Test∴ 156 7.4.2 Creating a Test library using a base test ∴..I57 7.4.3 Test Selection 7.5 Creating Meaningful Tests 158 7.5. I Constraining Data Items 158 7.5.2 Sequences and Sequencer Control 16 7.6 Virtual Sequencers and Sequences 167 7.6.1 The Virtual Sequencer 168 A Practica/ Guide to Adopting the Universal verification Methodology (UVM) 7.6.2 Creating a virtual sequence 7.6.3 Controlling Other Sequencers 70 7.6.4 Connecting a Virtual Sequencer to Sub-Sequencers IiI 7.7 Checking for DUT Correctness 172 7.7.1 Scoreboards 7. 8 Implementing a Coverage Model ,】75 7. 8. 1 Selecting a Coverage Method..,,....,....,,... ,175 7.8.2 Implementing a Functional Coverage model 176 8 Stimulus Generation Topics 177 8. 1 Fine Control Sequence generation ∴,,.177 8.2 Executing Multiple Sequences Concurrently 8.2.1 Using fork/join and'uvm_do in the Body of a Sequence n..,,180 8.2.2 Starting Several Sequences in parallel 180 8.3 Using p_sequencer∴ 181 8.4 Using the pre_body O and post-body(Methods 8.5 Controfling the Arbitration of Items 182 8, 6 Interrupt sequences 183 8.7 Protocol Layering ..184 6.7.1 Layering of Protocols l85 8.7.2 Layering and Sequences l85 8.73 Styles of Layering 188 8.7.4 Using Layered Sequencers 192 9 Register and Memory Package 197 9.1 Register-Related Terminology 198 9. 2 Register Package Overvie 198 2.1 Register Packages Usage fle 9 9.2.2 uvm_rgm Hook-Up and Data Flow 199 9.2.3 The Register Database(RGM DB) .200 9.2.4 Randomization and injection 92.5 Monitoring 201 9.3 Using the uvm rgm Package 9.3.1 Defining the register and memory models 202 9.3.2 Creating an IP-XACT File 9.3.3 Creating uvm_rgm System Verilog Classes 204 9.4 Connecting uvm rgm Components in a Testbench ,,,、.,210 9.4.1 Connecting Register Components to a Testbench 210 9.4.2 Adding the Necessary Infrastructure to the Bus Master Sequencer 11 9.4.3 Instantiation and Connection to the testbench 214 A Practical Guide to Adopting the Universa/ verification Methodology (UV// VEI 94 Reset handling∴ 217 9.5 Controlling Register Scenarios 217 Register operations 9.5.2 Register Read/Write Sequences ,,,219 9.5.3 Multi-Register Sequence Operations....... ...221 9.5.4 Sequences reuse 222 9.6 Using uvm rgm for Checkin 8 .222 9.6. 1 Using the Shadow Model for Checking .…n,.222 9.6.2 Advanced Register Checking 222 9.7 Updating the Register Database Model ,223 9.7.1 Updating the Module UVC 224 9.8 Collecting Coverage of Register Activities .225 9.8. 1 Using uvm_rgm Automatic Coverage Facilities 225 9.8.2 User-Defined Coverage 226 9.9 Controlling Coverage-Sampling Time 227 10 System UVCs and Testbench Integration ....B....,.,, 229 0.1 Introduction 229 10.2 Module and System uVc architecture 23 10.2.1 Reuse in module and System uvcs 23 10.2.2 Module uvc architecture 232 10.2. 3 System UVC Architecture .233 10.3 Sub-Components of Module and system uvcs 234 10.3.1 Monitor 34 10.3.2 Memory Blocks and Register Files 237 10.3.3 Active Stand-In mode .237 10.3.4 The module uvc class 238 10.4 Module uvc configuration 238 10.4.1 Standard Configuration Modes 239 10.4.2 Module uvc reconfiguration 240 0.5 The Testbench 241 I0.5. 1 The UART Controller Testbench Strategy 243 10.5.2 Virtual Sequencer and Register Sequencer 246 10.5.3 Interface UVC Extensions ...,,.,,,246 10.6 Sequences 246 10.6.1 Developing Reusable Sequences ..247 10.7 Coverage 248 10.7.1 Module uvc coverage 249 10.7.2 System-Level coverage .,,252 10.7.3 Adding Coverage Definitions to System UVCs ⅥI A Practical Guide to Adopting the Universa/ verification Methodology (UvM Contents 10.8 Stand-In mode 252 10.9 Scalability Concerns in System Verification 254 10 Randomization and stimuli Creation ,,255 10.9.2 Coverage ,,255 109.3 Messages……… 256 10. 10 Module UVC Directory Structure 256 11 The Future of UVM 11.1 Commercial UVM Verification IP .259 1.2 Class Library enhancements 260 11. 2. 1 Register package 260 11. 2.2 Runl-Time phases 260 11.2.3 Multi- Language Integration ..26I 11.3 Multi-Domain UVM 263 The Authors 265 ndex。.,,.,,,,。, ,,,..267 A Practical Guide to Adopting the Universal Verification Methodology (Uvm) EX 【实例截图】
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