SATA 3.2规范文档

【实例简介】
SATA 3.2最新规范，无删减带链接。
HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization Revision history… .27 1.1 Revision 2.5 (ratification date October 27, 2005) .27 1.2 Revision 2.6(ratification date February 15, 2007) 27 1.3 Revision 3.0(ratification date June 6, 2009 .27 1.4 Revision 3. 1 (ratification date July 18, 2011) 28 1.5 Revision 3. 2 (ratification date August 7, 2013) 29 2 Scope Normative references 33 3.1 Normative references overview .33 32A d references ::.:a.a:a. 33 3.3 References under development 35 3.4 other references 35 3.5 SATA-I0 Style Guide 36 3.6 Design guides 36 Definitions abbreviations and conventions 37 4.1 Terminglo .37 4.1.1 Definitions and abbreviations 37 4.1.2 Symbols and abbreviations 1·面 50 4.2 Conventions 53 4.2.1 Capitalization 4.2.2 Precedence 53 4.2.3 Keywords 53 4.2.4 Numberin 54 4.2.5 Dimensions 54 4.2.6 Signal conventions 54 4.2.7 State machine conventions .54 4.2.8 Byte, Word, Dword, and Qword Relationships 55 General overview ∴59 5.1 Connectivity 59 5.2 Architecture 60 5.3 Usage models… .....: 5.3.1 Usage models scope 66 5.3.2 nternal 1 m cabled host to device 68 5.3.3 Short backplane to device 68 5.3.4 Long backplane to device(obsolete 69 5.3.5 Internal 4-lane cabled disk arrays 69 5.3.6 System-to-system interconnects- data center applications(XSATA) 70 5.3.7 System-to-system interconnects- external desktop applications(eSATA)..72 5.3.8 Proprietary Serial Ata disk arrays 73 5.3.9 Serial ata and Sas 73 5.3. 10 Potential external sata incompatibility issues 74 5.3.11 Mobile applications 74 5312 SATA Universal Storage Module( SATA USM)………………………77 5.3.13 Port Multiplier example applications 78 Cables and connectors 6.1 Cables and connectors overview 88 6.2 Internal cables and connectors 6.2.1 Internal single lane description 81 6.2.2 Connector locations 84 6.2.3 Mating interfaces 93 6.2.4 Signal cable receptacle connector 97 6.2.5 Signal host plug connector…… .100 6. 2.6 Backplane connector 103 Serial ata revision 3.2 Gold page 3 of 874 6.2.7 Power cable receptacle connector 106 6.2.8 Internal single lane cable material .108 6.2.9 Connector labeling 109 6.2.10 Connector and cable assembly requirements and test procedures 109 6.2.11 Internal multilane cables 113 6.2.12 Mini sata Internal multilane 119 6.3 Internal micro sata connector for 1 8 inch hdd 126 6.3.1 Internal micro sata connector for 1.8 inch hdd overview 126 6.3.2 Usage model 126 6.3.3 General description 126 6.3. 4 Connector location 126 6.3.5 Mating interfaces 129 6.4 Internal slimline cables and connectors 135 6.4.1 nternal slimline cables and connectors overview 135 6.4.2 Usage models 135 6.4.3 General description 画国面面面面 136 6.4.4 Connector location and keep out zones. .........................................................137 6. 4.5 Mating interfaces 143 6.4.6 Backplane connector configuration and blind-mating tolerance 154 6.4.7 Connector labeling 4155 6.4.8 Connector and cable assembly requirements and test procedures....... 155 6.5 Internal LIF-sata connector for 1. 8 inch HDD 156 6.5.1 Internal lif-sata connector for 1.8 inch hdd overview ,,, 156 6.5.2 General description 156 6.5.3 Connector locations 157 6.5. 4 Mating interfaces 159 6.5.5 Internal LIF-SATA pin signal definition and contact mating sequence......162 6.5.6 Housing and contact electrical requirement 164 6.6 m sAta connector… .164 6.61 sata connector overview 164 6.6.2 General description ∴164 6.6.3 Connector location on sata host 164 6.6.4 Mating interfac 167 6.6.5 m Sata pin signal definition…… 170 6.7 SATA USM connector 174 6.7.1 SATA USM connector location 174 6.7.2 USM mating interfaces 178 6.8 SATA MicroSSD interface 182 6.8.1 SATA MicroSSD interface scope 182 6.8.2 SATA MicroSSD mechanical specification 183 6.8.3 SATA Micro SSd ballout -functional signal definition 188 6.9 Internal m.2 connector 194 6.9.1 Internal m.2 connector overview 194 6.9.2 M2 mechanical(informative) 194 6.9.3 M2 board connector(informative) 194 694M2keys( informative)…… 199 6.9.5 M.2 sockets(informative 199 6.9.6 M 2 land pattern for top mount connector motherboard(informative).....200 6.9.7 M2 Z-height stack up( informative)…………………… .200 6.9.8 M2 board sizes(informative) 201 6.9.9 M 2 component placement and board thickness(informative).........202 6.9.10 M.2 signal integrity ..203 6.9.11M2 pad and anti- pad recommendations( (informative)………………203 6.9.12M.2 minimum plane pul‖ back from finger( (informative)………….204 6.9.13 M.2 socket 2 pin definition 205 6.9.14 M2 SSD socket 3 206 Serial ata revision 3.2 Gold page 4 of 874 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 6.9.15 M2 electrical 209 6.9.16 M.2 signal definitions, configuration 209 6.9.17 M 2 mated connector differential impedance(informative) 209 6.10 SATA Express connector 210 6.101 SATA Express connector overview……………………… .210 6. 10.2 SATA Express connector goals 210 6103 SATA Express technical summary…… 6. 10.4 SATA Express scope 212 6.10.5 SATA Express signal list 212 6.10.6 SATA Express mechanical 215 6. 10.7 SATA Express device plug connector 216 6. 10.8 SATA Express device cable receptacle connector .218 6. 10. 9 SATA Express host receptacle connector 221 6. 10.10 SATA EXpress host plug connector 223 6.10.11 SATA Express host cable receptacle connector 226 6.10.12 Power dongle connector 1画画 228 6. 10.13 SATA Express connector intermateability summary 231 6. 10.14 SATA Express connector and cable electrical and mechanical requirements. ...23 1 6. 10.15 SATA EXpress connector and cable assembly signal integrity requirements.. 231 6. 10.16 SATA Express connector and cable shielding requirements for EMI.....232 6. 10.17 SATA Express connector and cable assembly dC electrical requirements 232 6. 10.18 SATA Express connector and cable assembly mechanical and environmental requirements , 232 6.11 External cables and connectors .232 6.11.1 External single lane 232 6. 11.2 EXternal Serial ATA component general descriptions 234 6.11.3 External multilane 面 242 6.11.4 Mini sata External multilane 246 6.12 Cable and connector electrical specifications 249 6.12.1 Cable and connector electrical specifications overview 249 6. 12.2 Serial ATA cable electrical requirements 250 6. 12.3 Cable/connector test methodology 25 6.13 Hardware Feature Control (optional) 259 6.13.1 Behavior 259 6. 13.2 Electrical requirements specification 259 6.13.3 Device activity signal 261 6.13.4 Disable Staggered spinup control 263 6.13.5 Micro sata connector p7 definition( optional)…………………………264 6.14 Precharge and device presence detection 267 6. 14.1 Precharge and device presence detection overview ....·1 267 6.14.2 Device requirements 267 6. 14.3 Receptacle precharge(informative 267 6. 14.4 Presence detection(informative) 269 7 Phy layer 271 7. 1 Phy layer introduction 271 7.2 Descriptions of Phy electrical specifications 271 Terms overview 271 7.2.2 List of services 272 7. 2.3 Low level electronics block diagrams(informative) ,画新 272 2.4 Compliance testing 279 7.2.5 Link performance 280 7.3 SATA Express system electrical requirements 280 7.3.1 SATA Express system electrical requirements overview 280 7.3.2 SATA Express AC coupling capacitance requirement 281 7.3.3 SATA Express interface detect 281 73.4 PCle sidebands .283 Serial ata revision 3.2 Gold page 5 of 874 7.3.5 PCle device power 284 7.4 Electrical specifications 284 7.4.1 Electrical specifications overview 284 7.4.2 Physical layer requirements tables 285 7.4.3 Phy layer requirements details 305 4.4 Loopback 320 7.4.5 Test pattern requirements 323 4.6 Hot plug considerations .348 7.4.7 Mated connector pair definition 350 7.4.8 Compliance interconnect channels(Gen3i, Gen3u 354 7.4.9 Impedance calibration(optional) 355 7. 5 Jitter …356 7.5.1 Jitter overview 356 7.5.2 Jitter definition 357 7.5.3 Reference clock definition 357 7.54 Spread spectrum clocking. 359 7.5.5 Jitter budget 361 7.6 Measurements 362 7.6.1 Measurements overview 362 7.6.2 Test fixtures 363 7.6.3 Frame error rate testing 37 7.6.4 Measurement of differential voltage amplitudes(Gen1, Gen2) 374 7.6.5 Measurement of differential voltage amplitudes(Gen3i, Gen 3u) 385 7.6.6 Rise and fall times ...a.“aa:a:a 387 7.6.7 Transmitter amplitude 388 7.6.8 Receive amplitude 390 7.6. 9 Long term frequency accuracy 392 76.10 Jitter measurements 393 6.11 Transmit jitter(Gen 1i, Gen1m, Gen1u, Gen 2i, Gen 2m, Gen 2u 397 76.12 Transmit jitter(Gen3i,Gen3u)…… 397 7.6.13 Receiver tolerance(Gen1i, Gen 1m, Gen1u, Gen2i, Gen2m, Gen 2u) 399 7.6.14 Receiver tolerance(Gen 3i, Genu) 40 7.6.15 Return loss and impedance balance .403 7.6.16 SSC profile.…. 406 7.6.17 Intra-pair skew 407 7.6.18 Sequencing transient voltage 409 7.6.19 AC coupling capacitor 410 Tx rise/ fall imbalance( obsolete)……… 7.6.20 Tx amplitude imbalance 410 7.6.21 411 7.6.22 TX AC common mode voltage 7.6.23 TX AC common mode voltage(Gen1u, Gen2u, Gen3i, Gen3u 412 7. 6.24 OOB common mode delta 412 76.25 ooB differential delta 412 7.6.26 Squelch detector tests 412 7.6.27 OOB signaling tests 414 7.6.28 TDR differential impedance(Gen li, Gen 1m, Genlu) 415 7.6.29 TDR single-ended impedance(Gen li, Gen 1 m) 416 76.30 DC coupled common mode voltage(Gen1i)……… .417 7.6.31 AC coupled common mode voltage(Genli, Gen 1m) 417 7.6. 32 Sequencing transient voltage-lab-load(Gen 3 i, Gen 3u) 418 7.7 Interface states .:.a.aaa·.. 419 7.7.1 Out-of-Band(ooB)signaling ==a-a. 419 7.7.2 Idle bus condition 427 7.8 Elasticity buffer management 427 8 OOB and phy power states 429 8.1 Interface power states 429 Serial ata revision 3.2 Gold page 6 of 874 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ata International organization 8.2 Asynchronous signal recovery(optional) 429 8.2. 1 Asynchronous signal recovery overview 429 8.2.2 Device Sleep and Asynchronous Signal Recovery 430 8.2.3 Unsolicited COMINIT usage(informative) 430 8.3 OOB and Signature FIs return(informative) 430 8.4 Power- on sequence state machine∴…… 430 8.4.1 Power-on sequence state machine overview 430 8.4.2 Host Phy initialization state machin 431 8. 4.3 Device phy initialization state machine 436 8.4.4 Speed negotiation 440 8.5 DEVSLP signal protocol and timing 446 8.5.1 DEVSLP overview 446 8.5.2 DEVSLP signal electrical characteristics 448 Link layer 451 9.1 Link layer overview .451 9.1.1 Frame transmission 45 9.1.2 Frame reception 451 9.2 Encoding method 451 9.2.1 Encoding method overveiw 451 9.2.2 Notation and conventions 451 9.2.3 Character code 453 9.2.4 Transmission order summary .461 9.2.5 Reception summary 462 9.3 Transmission overview 464 94 Primitives∴ 465 9.4.1 Primitives overview 465 9. 4.2 Primitive disparity 面1 465 9.4.3 Primitive handshakes 465 9.4.4 Primitive descriptions .465 9.4.5 Primitive encoding 467 9.4.6 DMATp primitive 467 9. 4.7 CONTp primitive 468 9. 4.8 ALIGNp primitive .471 9. 4.9 Flow control signaling latency B面面 471 9. 4.10 Examples of primitive usage(informative) 474 9.5 CRC and scrambling 477 9.5.1 CRC and scrambling overview 477 9.5.2 Relationship between scrambling of Fis data and repeated primitives.....477 9.5. 3 Relationship between scrambling and CRc 477 9.5.4 Scrambling disable(informative) 478 9.6 Link layer state machine 画 .478 9.6.1 Terms used in link layer transition tables .478 9.6.2 Link idle state machine 479 9.6.3 Link transmit state machine 482 9. 6. 4 Link receive state machine 490 9.6.5 Link power mode state machine 496 10 Transport layer 503 10.1 Transport layer overview 503 10.2 FiS construction 503 10.3 Fis decomposition 503 10.4 Frame information structure(F|s)……… 503 10.4.1 Frame information structure(FIs)overview 503 10.4.2 Payload content 504 10.5 FIs types 504 10.5.1 FIS types scope 504 10.5.2 FIs type values 504 Serial ata revision 3.2 Gold page 7 of 874 10.5.3 CRC errors on data rises 505 10.54AF| s types.… .505 10.5.5 Register Host to Device FIs 画国面( 506 10.5.6 Register Device to Host FIS .508 105.7 Set device bits- device to host fis .510 10.5. 8 DMA Activate- Device to host .512 10.5. 9 DMA Setup- Device to Host Fis or Host to device FIS (bidirectional)....513 10.5.10 BIST Activate fis bidirectional 516 10.5.11 PlO Setup-device to Host FIs 519 10.5.12 Data-Host to Device FIs or Device to Host FIs (bidirectional) .522 10.6 Host transport states 524 10.6.1 Host transport states overview 524 10.6.2 Host transport idle state machine 524 10.6.3 Host transport transmit command fis state machine 527 10.6.4 Host transport transmit control FIS state machine 528 10.6.5 Host transport transmit DMA Setup- Device to Host Fis or Host to Device FIS state machine 529 10.6.6 Host transport transmit bIsT Activate FIs 530 10.6.7 Host transport decomposes Register FIs state machine.……… 531 10.6.8 Host transport decomposes a Set device Bits fis state machine....... 532 10.6. 9 Host transport decomposes a dmA Activate Fis state machine 533 10.6. 10 Host transport decomposes a PlO Setup FIs state machine 536 10.6. 11 Host transport decomposes a dma setup fis state machine ,。 539 10.6.12 Host transport decomposes a bist activate fis state machine.......... 540 0.7 Device transport states ..541 10.7.1 Device transport idle state machine 541 10.7.2 Device transport sends register device to Host state machine 542 10.7.3 Device transport sends Set Device Bits FIs state machine 543 10.7.4 Device transport transmit Plo Setup- Device to Host FIs state machine 545 10.7.5 Device transport transmit DMA Activate FIs state machine 546 10.7.6 Device transport transmit dMa Setup- Device to Host FIs state machine....... 547 10.7.7 Device transport transmit data - Device to Host fis state machine.......547 10.7.8 Device transport transmit bisT Activate fis state machine ..549 10.7.9 Device transport decomposes Register Host to Device FIs state machine... 550 10.7.10 Device transport decomposes Data(Host to Device)FIs state machine....55 10.7.11 Device transport decomposes DMA Setup- Host to Device state machine. .....552 10.7.12 Device transport decomposes a bist activate fis state machine 553 Device command layer protocol 555 11.1 Device command layer protocol overview .555 11.2 Power-on and COMRESET protocol 555 11.3 Device idle protocol 558 11.4 Software reset protoco 564 11.5 EXECUTE DEVICE DIAGNOSTIC command protocol 566 11.6 DEVICE RESET command protocol 568 11.7 Non-data command protocol L,8 .569 11.8 Plo data- in command protocol ...1aa .570 11.9 PlO data-out command protocol 572 11.10 DMa data in command protocol 573 11.11 DMA data out command protocol 11日,面面国 …574 11.12 PACKET protocol 575 11.13 READ DMA QUEUED command protocol 582 11.14 WRITE DMA QUEUED command protocol 583 11.15 FPDMA QUEUED command protocol…… ∴585 12 Host command layer protocol 593 12.1 FPDMA QUEUED command protocol overview…… 593 12.2 FPDMA QUEUED command protocol 593 Serial ata revision 3.2 Gold page 8 of 874 HIGH SPEED SERIALIZED AT ATTACHMENT Serial ATA International Organization 13 Application layer… 599 13.1 Parallel ata emulation 599 13.1.1Parallelataemulationoverview.wwwww.599 13.1.2 Software reset 5 1313 Master- only emulation….…...… 00 13.1.4 Master/Slave emulation(optional) 601 13.2 IDENTIFY(PACKET)DEVICE …608 13.2.1 IDENTIFY(PACKET)DEVICE overview 608 13.22 IDENTIFY DEVICE 609 13.2.3 DENTIFY PACKET DEVICE 13.2.4 Determining support for Serial ata features. 617 623 13.3 SET FEATURES 1道 624 13.3.1 SET FEATURES OVerview 624 13.3.2 Enable/disable non-zero offsets in DMA Setup 624 13.3.3 Enable/disable DMA Setup FIS auto-activate optimization ........................624 13.3.4 Enable/disable device-initiated interface power state transitions 625 13.3.5 Enable/disable guaranteed in-order data delivery.. 1,国 625 13.3.6 Enable/disable asynchronous notification 625 13.3.7 Enable/disable software settings preservation 625 13.3. 8 Enable/disable device automatic Partial to slumber transitions 626 13.3. 9 Enable hardware feature Control 626 13.3. 10 Enable/disable Device Sleep 626 13.3.11 Enable/disable Hybrid Information 627 13.4 Device Configuration Overlay( obsolete)……… 628 13.5 Software settings preservation(optional) 629 13.5. 1 Software settings preservation overview 629 13.5.2 Warm reboot considerations(informative) 630 13.6 Native Command Queuing(optional) 63 13.6.1 Native Command Queuing overview .631 13.6. 2 Native Command Queuing(NCQ)Definition 631 13.6.3 Intermixing Non-Native Queued Commands and Native Queued Commands.. 635 13. 6. 4 READ EPDMA QUEUED 637 13.6.5 WRITE FPDMA QUEUED 643 13.6.6 NCQ NON-DATA 647 13.6.7 RECEIVE FPDMA QUEUED .669 13.6. 8 SEND FPDMA QUEUED 674 13.6.9 First-party DMA HBA support(informative) .682 13.7 SATA logs B面画面 683 13.7.1 SAtA logs overview 683 13.7.2 Log address definitions 683 13.7.3 General purpose log directory(ooh) 1 683 13.7.4 Queued error log(10h) 685 13.7.5 NCQ NON-DATA log(12h) 688 13.7.6 NCQ send and receive log(13h) 691 13.7.7 Hybrid Information log(14h .693 13.7.8 Rebuild Assist log(15h) 699 13.7. 9 Identify Device data log(30h) 701 138 Asynchronous notification( optional)………… 717 13.8.1 Asynchronous notification overview 717 13.82 Set device bits fis notification bit .717 13. 8.3 Notification mechanism 717 13.8.4 State machine for asynchronous notification 717 13.8.5 ATAPI notification 718 13. 9 Phy event counters(optional) 718 13.9. 1 Phy event counters overview 718 139.2 Counter reset mechanisms 面B国国B 719 Serial ata revision 3.2 Gold page 9 of 874 13.93 Counter identifiers………… 719 13.9.4 Phy Event Counters Log(11h) 723 13.10 Hardware Feature Control (optional) .724 13.11 Staggered spinup(optional) 724 13.12 Non-512 byte sector size(informative) 725 13.13 Defect management (informative) 725 13.13. 1 Defect management overview 725 13.13.2 Typical Serial ATA reliability metrics 726 13.13.3 An overview of Serial ATA defect management 726 13. 13.4 Continuous background defect scanning(CBDS) 727 13.13.5 Self-monitoring, analysis and reporting technology 727 1314 Enclosure services/management( optional)………727 13.14.1 Enclosure services/management overview 727 13. 14.2 Topology 728 13.14.3 Limitations… .730 13.144 Definition 730 13.14.5 SES and SAF-TE extensions .736 13.14. 6 Enclosure services hardware interface 742 13.15 HDD activity indication(optional) …743 13. 15.1 HDD activity indication overview …743 13.15.2 HDd activity emulation of desktop behavior 743 13. 15.3 Activity/status indication reference(informative) 744 13.16 Port Multiplier discovery and enumeration 747 13. 16.1 Power-up 747 13.16.2 Resets 747 13.16.3 Software initialization sequences(informative) 748 13.164 Port Multiplier discovery and device enumeration( formative).………….,749 13.17 Automatic Partial to slumber transitions 750 13.18 Serial ATA Link power management support 751 13 19 DHU specific operation(optional) 画 751 13.20 Hybrid Information feature(optional) 751 13. 20. 1 Hybrid Information feature overview 75 13.20.2 Hybrid Information field bits 753 13.203 Syncing… 757 13204 interactions with aTa power management.……… 757 13.20.5 Other Hybrid conditions 758 13.20. 6 Automatic disable 759 13.21 Rebuild Assist (optional) 翻面面国1B 759 13.21.1 Rebuild assist overview .759 13.21.2 Enabling Rebuild Assist feature 759 13.21.3 Using the Rebuild Assist feature 760 13.21.4 Disabling the rebuild Assist feature 76 13.21.5 Testing the Rebuild Assist feature 761 14 Host adapter register interface .763 14.1 Host adapter register interface overview 763 14.2 Status and control registers 763 14.2.1 Status and Control registers overview 763 14.2.2 STatus register 764 14.2.3 SError register 765 14.2.4 COntrol register 767 14.2.5 SActive register 768 14.2.6 NOtification register(optional) 768 15 Error handler 771 15.1 Architecture 771 15.2 Phy error handling overview 772 15.2.1 Error detection 772 Serial ata revision 3.2 Gold page 10 of 874 【实例截图】
【核心代码】