DDR3 JEDEC 官方标准文档

【实例简介】
DDR3 JEDEC 官方标准文档 DDR3 JEDEC 官方标准文档 DDR3 JEDEC 官方标准文档
PLEASE DON"TⅤ IOLATE THE LAW This document is copyrighted by JEDEC and may not be reproduced without permission Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact JEDEC Solid State Technology Association 3103 North 1 oth Street. Suite 240 South Arlington, Virginia 22201 or call(703)907-7559 This page left blank JEDEC Standard no. 79-3F Contents I Scope 2 DDR3 SDRAM Package Pinout and Addressing ······················· 2.1 DDR3 SDRAM x4 Ballout using mo-207 133 2.11.1512Mb 15 2.11.21Gb. 音垂垂D垂 2.11.32Gb ……………………………………15 2.11.44Gb.… 15 2.11.58Gb. …16 3 Functional Description 垂音.音垂音垂音音音垂音垂音垂音垂音着音垂音。垂垂音.音番垂音番 17 3. 1 Simplified Statc Diagram...............17 3.3. I Power- up Initialization Sequence……,,…,…,……,…,……….……….…..,19 3.3.2 Reset Initialization with Stable power 21 3. 4. 1 Programming the Mode registers 垂·垂垂。希。垂垂看D垂 22 3.4.2 Mode Register mro 23 3. 4.3 Mode Register mrI 27 3.4.4 Mode Register mr2 …30 3.4.5 Mode Register Mr3........ 32 4 DDR3 SDRAM Command Description and operation 33 4.1 Command Truth Table 33 4.3 No OPeration(NOP)Command 36 4.4 Deselect Command… 36 4.6.IDLL“on” tO dll“of? Procedure …38 4.6.2DLL“ off to dll“on” Procedure…39 4.8. 1 DRAM Setting for write leveling dra termination function in that mode.. 43 4.8.2 Procedure di 43 4.8.3 Write Leveling Mode exit..............,…,………………45 4.9.1 Self-Refresh Temperature Range- SRT 46 4.10 1 MPR Functional Description…………… 翻音查番垂音垂 49 4.10.2 MPR Register Address Definition................50 4.10.3 Relevant Timing Parameters 。番垂看音垂·垂·垂音看垂看垂 50 4.10.4 Protocol Example 50 4.12 PRECHARGE Command 4.13.1 READ Burst Operation…… 6 4.13.3 Burst Read Operation followed by a Precharge 66 4.14.1 DDR3 Burst Operation 68 4.14.2 WRITE Timing Violations…………68 4.14.3 Write Data Mask 4.14.4 tWPre Calculation…… …70 4.14.5 tWPST Calculation....………………………170 4. 17. 1 Power-Down Entry and exit 垂·垂垂 81 4.17.2 Power-Down clarifications -Case 1 ...:.:a.日 86 417.3 Powcr-Down clarifications- Casc 2 87 5on- Die termination(ODT)…… 89 5. 1 ODT Mode Register and odt Truth table .89 JEDEC Standard no.79-3F Contents 5,2 Synchronous odt mode…… 90 5.2.1 OdT Latency and Posted odt 90 5.2.2 Timing Parameters. 5.2. 3 Odt during reads …………92 5.3. 1 Functional Description ………………94 5.3.2 ODT Timing Diagrams..........95 5.4. I Synchronous to Asynchronous ODT Mode transitions …101 5.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down entry 垂音.音音垂音音音垂音垂音垂垂 101 5.4.3 Asynchronous to Synchronous ODT Modc Transition during Power-Down exit ………104 5.4. 4 ASynchronous to Synchronous OdT Mode during short CKe high and short CKE low periods.................,...,,105 5.5.1 zQ Calibration Description.…… 107 5.5.2 ZQ Calibration Timing 108 5.5.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ................108 6 Absolute Maximum Ratings ∴109 6. 1 Absolute Maximum dC ratings 109 6.2 DRAM Component Operating Temperature range.................109 7AC& DC Operating Conditions.……… 7. 1 Recommended DC Operating Conditions 111 8 AC and dc Input measurement Levels 113 8.1 AC and DC logic Input Levels for Single-Ended Signals.........113 8.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals...113 8.3 AC and dC Logic Input levels for Differential Signals a·:·· 116 8.3. 1 Differential signal definition..........116 8.3.2 Differential swing requirements for clock(CK-CK#f)and strobe (DQS-DQS#)… b音音看音B音垂D面面垂垂 16 8.3.3 Single-ended requirements for differential signals..........117 8.4 Differential Input Cross Point Voltage…………………,118 8.6 Slew Rate Definitions for Differential Input Signals 120 9 AC and dc output measurement Levels........................121 9, I Single上 Ended AC and DC Output Level!.……………………121 9.2 Differential AC and DC Output levels 121 9.6. 1 Address and Control Overshoot and undershoot specifications 125 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications....126 9.7. 1 Output Driver Temperature and voltage sensitivity 128 9.8. 1 On-Die Termination(ODT) Levels and I-V Characteristics.........130 9.8.2 ODT DC Electrical Characteristics. ........................................................................131 9.8.3 ODT Temperature and voltage sensitivity..... .····· ·4·:.·· 134 9.9 ODT Timing definitions 134 9.9. 1 Test Load for odt Timings 134 9.9.2 ODT Timing Definitions. ∴…135 10 IDD and IddQ Specification Parameters and Test Conditions …139 JEDEC Standard no. 79-3F Contents 10.1 IDD and IDDo measurement Conditions 139 11 Input/Output capacitance 153 11. 1 Input/Output Capacitance..........................153 12 ·:···4········· ··..·.·· 垂垂垂垂垂.非·垂·垂·垂 ,垂垂音,。垂 155 12. 1 Clock Specification 155 12. 1. 1 Definition for tCK(avg)...............155 2.1.2 Definition for tCK(abs) 155 12.1.3 Definition for tch(avg) and tCL(avg)……… 155 12. 1. 4 Definition for tJIT(per)and tIt(per, Ick).....................156 12. 1.5 Dcfinition for tJIT(cc)and tJIT(cc,Ick).......156 12.1.6 Definition for tErR(nper)......... 中···;.·.····· ………156 12.2 Refresh ters by device density 156 13 Electrical Characteristics and AC Timing 167 13. 1 Timing Parameters for DDR3-800, DDR3-1067, DDR3-1333, and DDR3-1600..167 13.6. 1 Data Setup, Hold and Slew Rate Derating of DDR3-1866/2133 190 JEDEC Standard no.79-3F List of figures Figure 1--Qual-stacked/Quad-die DDR3 SDRAM X4 rank association Figure 2--Qual-stacked/ Quad-die ddr3 Sdram 8 rank association 12 Figure 3-Qual-stacked/ Quad-die dDr3 SDRaM xl6 rank association 12 Figure 4-Simplified State Diagram Figure 5--Reset and Initialization Sequence at Power-on ramping Figure 6--Reset Procedure at Power Stable Condition 222 701 Figure 7-tMRD Timing ··· Figure 8--tMOD Timing 22 Figure 9--MRO Definition 24 Figure 10--MRI Definition 27 Figure 1l-MR2 Definition 30 Figure 12--MR3 Definition ,,,,,,,,,32 Figure 13--DLL-off mode READ Timing Operation 37 Figure 14--DlL Switch Sequence from DLL-on to DLL-off 38 Figure 15--DlL Switch Sequence from DlL Off to DLL On 39 Figure 16--Change Frequency during Precharge Power-down 41 Figure 17-Write Leveling Concept 42 Figure 18--Timing details of Write leveling sequence [dQs-DQs# is capturing CK-CK# low at TI and CK -CK# high at T2 Figure 19--Timing details of Write leveling exit 45 Figure 20--MPR Block Diagram 48 Figure 21-MPR Readout of predefined pattern, Bl& fixed burst order, single readout 51 Figure 22--MPR Readout of predefined pattern, bL8 fixed burst order, back-to-back readout ······ 52 Figure 23--MPR Readout predefined pattern, BC4, lower nibble then upper nibble Figure 24--MPR Readout of predefined pattern, BC4, upper nibble then lower nibble. ... 54 Figure 25--READ Burst Operation RL=5(AL=0, CL-5, bL8 Figure26— READ Burst Operation RL=9(AL=4,CL=5,BL8)…….¨…56 ···· 56 Figure 27--READ Timing Definition 57 Figure 28--Clock to Data Strobe Relationship 58 Figure 29--Data Strobe to Data Relationship Figure 30-tLz and thz method for calculating transitions and endpoints Figure 3 1-Method for calculating trPre transitions and endpoints 61 Figure 32--Method for calculating tRPST transitions and endpoints Figure 33--READ (BL8 to READ(BL8) ,,,,,,,,,,,,,,,62 Figure 34--Nonconsecutive REAd BlS)to READ (BL8), tCCD=5 62 Figure 35--REad (BC4) to READ(BC4 ····· 63 Figure 36--REad(BLS)to WRIte ( BL8 63 Figure 37--READ (BC4)to WRITE(BC4)OTF .64 Figure 38--READ(BL8 )to READ (BC4)OTF 64 Figure 39-READ( BC4 )to READ BL&)OTF 5 Figure 40--READ (BC4 )to WRITE BL&)OTF .,,,,,,,,,,,,,,,,,,,,,.65 Figure 41-READBL8)to WRITE ( BC4)OTF 66 Figure 42--Read to PRECHARGE, RL=5, AL=0, CL=5, tRTP=4, tRP=5 67 Figure 43--READ to PrECharge, rl =8, AL=CL-2, CL-5, tRTP=6, tRP=5 67 Figure 44-Write Timing Definition and parameters 69 Figure 45--Method for calculating tWpre transitions and endpoints ...................70 JEDEC Standard no. 79-3F List of figures Figure 46-Method for calculating tWPsT transitions and endpoints Figure 47-WRITE Burst Operation WL-5 (AL-0, CWL-5, BL8) 70 垂音 71 Figure 48--WRITE Burst Operation WL=9(AL=CL-1, CWL=5, BL8 71 Figure 49--WRitE (BC4)to READ (BC4 ) Operation 72 Figure 50-WRITE (BC4)to PRECHARGE Operation 72 Figure 51-WRitE (BC4)otF to PRECHARGE Operation 72 Figure52— WRITE(BL8) to WrIte(BL8),… ,,,,,,73 Figure 53-WRITE (BC4 )to WRITE (BC4)OTF 73 Figure 54-WRITE(BL8)to READ ( BC4/BLS)OTF ,,,,,,,,74 Figure 55-WRitE (BC4)to READ (BC4/BL8)OTF 74 Figure 56--WRITE (BC4)to READ (BC4 Figure 57-WRItE (BL8)to WRITE (BC4)OTF 75 Figure 58-WRITE (BC4)to WRITE(BL8)OTF 76 Figure 59-Refresh Command Timing 77 Figure 60--Postponing Refresh Commands (Example) ..,,,77 Figure 61--Pulling-in Refresh Commands(Example) ,,,,,,78 Figure 62--Self-Refresh Entry/Exit Timing 80 Figure 63-Active Power-Down Entry and Exit Timing diagram 82 Figure 64--Power-Down Entry after Read and read with Auto Precharge . ..............82 Figure 65--Power-Down Entry after Write with Auto Precharge ..83 Figure 66--Power -Down Entry after Write 83 Figure67— Precharge Power-Down( Fast Exit mode) Entry and exit,……,84 Figure 68- Precharge Power-Down(Slow Exit Mode) Entry and exit 84 Figure 69- Refresh Command to Power-Down Entry .,,,,,,,.,85 Figure 70- Active Command to Power-Down Entry 85 Figure 71- Precharge/Precharge all Command to Power-Down Entry 86 Figure 72- MrS Command to Power-Down entry · ..,,86 Figure 73--Power-Down Entry/Exit Clarifications -Case 1 垂4D·垂 87 Figure 75--Functional Representation of oDr Ons-Case 2 Figure 74--Power-Down Entry/ Exit Clarificati 87 89 Figure 76--Synchronous ODT Timing Example for AL =3; CWL=5 ODTLon= AL+ CWL-2=6.0: ODTLoff= Al CWL-2=6 ·· Figure 77-Synchronous OdT example with bl =4, WL=7 92 Figure 78--ODT must be disabled externally during Reads by driving OdT low (example: CL=6; AL=CL-1=5; RL=AL +Cl=1l; CWL=5; ODTLon-CWL+AL-2=8: ODTLoff=CWL+ AL-2=8) 93 Figure 79-Dynamic ODT: Behavior with Odt being asserted before and after the write.. 96 Figure 80--Dynamic ODT: Behavior without write command, AL=0, CWL=5 96 Figure 81--Dynamic ODT: Behavior with OdT pin being asserted together with write command for a duration of 6 clock cycles 97 Figure 82-Dynamic ODT: Behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4(via mrs or OtF) AL=O CWL=5 98 Figure 83--Dynamic ODT: Behavior with Odt pin being asserted together with write command for a duration of 4 clock cycles Figure 84-Asynchronous ODT Timings on ddR3 SDRaM with fast odt transition AL is ignored ····.···· 非垂 垂· .,100 JEDEC Standard no.79-3F List of figures Figure 85-Synchronous to asynchronous transition during Precharge Power Down (with dll frozen)entry(AL=0; CWL-5; tANPD-WL-1-4)....102 figure 86-Synchronous to asynchronous transition after refresh command Figure 87--ASynchronous to synchronous transition during Precharge Power Down (with.L0 (AL=0; CWL-5; tANPD-WL-1-4 03 DLL frozen)exit (CL-6; AL-CL -1; CWL-5; tANPD-WL-1-9). 104 Figure 88--Transition period for short CKE cycles, entry and exit period overlapping (AL-O,WL-5, tANPD-WL-1-4 105 Figure 89--zQ Calibration Timing ,,,108 Figure 90-Illustration of VRef(dC) tolerance and vref ac-noise limits ,,,,,,115 Figure 91-Definition of differential ac-swing and"time above ac-leveltDVAC l16 Figure 92-Single-ended requirement for differential signals 118 Figure 93-Vix Definition 翻 119 Figure 94--Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#..... 120 Figure 95--Single-ended Output Slew Rate Definition ··· 122 Figure 96--Differential Output Slew Rate Definition ··· ..123 Figure 97-Reference Load for AC Timing and Output Slew Rate ....................124 figure 98-Address and Control Overshoot and Undershoot definition ................125 Figure 99--Clock, Data, Strobe and mask Overshoot and undershoot definition ...126 Figure 100--Output Driver: Definition of Voltages and Currents........... 127 Figure 101--On-Die Termination: Definition of voltages and Currents ..,,130 Figure 103--Definition of tAaf ence Load Figure 102--ODT Timing Ref 134 136 Figure 105--Definition OttAof Figure 104--Definition of tAONPD .,,,,,,,,,,,,,,,,,136 Figure107- definition of ta◇∵,··.. ,.137 Figure 106--Definition of tAOFF 非·音垂着D音垂垂 137 ..138 Figure 108- Measurement Setup and Test load for Idd and iddQ (optional) Figure 109--Correlation from simulated Channel IO Power to actual Channel IO Power..140 Measurements supported by iddo measurement 140 Figure 110--Illustration of nominal slew rate and tvac for setup time tIs (for ADD/CMD with respect to clock).. 186 Figure 111--Illustration of nominal slew rate for hold time tIH (for ADD/CMD with respect to clock).......... ,,,,,187 Figure 112--Illustration of tangent line for setup time tiS (for ADD/CMd with respect to clock .,,,,,,,,,,,188 Figure 113-lllustration of tangent line for for hold time tIh ( for Add/CMd with respect to clock 189 Figure 114--Illustration of nominal slew rate and tvac for setup time tDS (for dQ with t to strobe) 195 Figure 115--lllustration of nominal slew rate for hold time tDH (for dQ with respect to strobe 196 Figure 116--Illustration of tangent line for setup time tDS (for dQ with respect to strobe). 197 Figure 117-Illustration of tangent line for hold time tDH (for dQ with respect to strobe). 198 【实例截图】
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