USB 3_2 SPEC.pdf

【核心代码】

Contents
1 Introduction ................................................................................................................................................1
1.1 Background......................................................................................................................................1
1.2 Objective of the Specification ....................................................................................................1
1.3 Scope of the Document.................................................................................................................2
1.4 USB Product Compliance .............................................................................................................2
1.5 Document Organization ...............................................................................................................2
1.6 Design Goals ....................................................................................................................................2
1.7 Related Documents........................................................................................................................3
1.8 Conventions .....................................................................................................................................3
1.8.1 Precedence .......................................................................................................................3
1.8.2 Keywords ..........................................................................................................................3
1.8.2.1 Informative........................................................................................................................3
1.8.2.2 May........................................................................................................................................3
1.8.2.3 N/A........................................................................................................................................4
1.8.2.4 Normative ..........................................................................................................................4
1.8.2.5 Optional ..............................................................................................................................4
1.8.2.6 Reserved.............................................................................................................................4
1.8.2.7 Shall ......................................................................................................................................4
1.8.2.8 Should..................................................................................................................................4
1.8.2.9 Numbering.........................................................................................................................4
2 Terms and Abbreviations ........................................................................................................................5
3 Architectural Overview......................................................................................................................... 15
3.1 USB 3.2 System Description .................................................................................................... 15
3.1.1 USB 3.2 Mechanical ..................................................................................................... 17
3.1.2 USB 3.2 Power .............................................................................................................. 17
3.1.3 USB 3.2 System Configuration ................................................................................. 17
3.1.4 Architectural Differences between USB 3.2 and USB 2.0 ................................ 17
3.2 Enhanced SuperSpeed Bus Architecture ............................................................................. 18
3.2.1 Physical Layer .............................................................................................................. 20
3.2.1.1 Gen 1 Physical Layer ..................................................................................................21
3.2.1.2 Gen 2 Physical Layer ..................................................................................................21
3.2.1.3 Dual-Lane Operation..................................................................................................22
3.2.2 Link Layer ...................................................................................................................... 22
3.2.3 Protocol Layer .............................................................................................................. 23
3.2.3.1 SuperSpeed Protocol..................................................................................................24
3.2.3.2 SuperSpeedPlus Protocol.........................................................................................24
3.2.4 Robustness .................................................................................................................... 24
3.2.4.1 Error Detection.............................................................................................................25
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3.2.4.2 Error Handling..............................................................................................................25
3.2.5 Enhanced SuperSpeed Power Management ........................................................ 25
3.2.6 Devices ............................................................................................................................ 26
3.2.6.1 Peripheral Devices ......................................................................................................26
3.2.6.2 Hubs...................................................................................................................................28
3.2.7 Hosts................................................................................................................................ 30
3.3 Enhanced SuperSpeed Bus Data Flow Models ................................................................... 31
4 Enhanced SuperSpeed Data Flow Model ......................................................................................... 32
4.1 Implementer Viewpoints .......................................................................................................... 32
4.2 Enhanced SuperSpeed Communication Flow ..................................................................... 32
4.2.1 Pipes ................................................................................................................................ 32
4.3 Enhanced SuperSpeed Protocol Overview .......................................................................... 33
4.3.1 Differences from USB 2.0 .......................................................................................... 33
4.3.1.1 Comparing USB 2.0 and Enhanced SuperSpeed Transactions ................34
4.3.1.2 Introduction to Enhanced SuperSpeed Packets.............................................34
4.4 Generalized Transfer Description ......................................................................................... 35
4.4.1 Data Bursting ................................................................................................................ 36
4.4.2 IN Transfers .................................................................................................................. 36
4.4.3 OUT Transfers .............................................................................................................. 37
4.4.4 Power Management and Performance .................................................................. 38
4.4.5 Control Transfers ........................................................................................................ 39
4.4.5.1 Control Transfer Packet Size..................................................................................39
4.4.5.2 Control Transfer Bandwidth Requirements....................................................39
4.4.5.3 Control Transfer Data Sequences.........................................................................40
4.4.6 Bulk Transfers .............................................................................................................. 40
4.4.6.1 Bulk Transfer Data Packet Size .............................................................................40
4.4.6.2 Bulk Transfer Bandwidth Requirements..........................................................41
4.4.6.3 Bulk Transfer Data Sequences...............................................................................41
4.4.6.4 Bulk Streams..................................................................................................................41
4.4.7 Interrupt Transfers ..................................................................................................... 43
4.4.7.1 Interrupt Transfer Packet Size ..............................................................................44
4.4.7.2 Interrupt Transfer Bandwidth Requirements ................................................44
4.4.7.3 Interrupt Transfer Data Sequences.....................................................................45
4.4.8 Isochronous Transfers ............................................................................................... 45
4.4.8.1 Isochronous Transfer Packet Size........................................................................46
4.4.8.2 Isochronous Transfer Bandwidth Requirements..........................................46
4.4.8.3 Isochronous Transfer Data Sequences ..............................................................47
4.4.8.4 Special Considerations for Isochronous Transfers ......................................47
4.4.9 Device Notifications.................................................................................................... 49
4.4.10 Reliability....................................................................................................................... 49
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4.4.10.1 Physical Layer ...............................................................................................................49
4.4.10.2 Link Layer .......................................................................................................................49
4.4.10.3 Protocol Layer...............................................................................................................49
4.4.11 Efficiency........................................................................................................................ 49
5 Mechanical ................................................................................................................................................ 50
6 Physical Layer.......................................................................................................................................... 51
6.1 Physical Layer Overview .......................................................................................................... 51
6.2 Physical Layer Functions .......................................................................................................... 51
6.2.1 Measurement Overview............................................................................................. 55
6.2.2 Channel Overview ....................................................................................................... 56
6.3 Symbol Encoding......................................................................................................................... 56
6.3.1 Gen 1 Encoding............................................................................................................. 56
6.3.1.1 Serialization and Deserialization of Data..........................................................57
6.3.1.2 Normative 8b/10b Decode Rules for Gen 1 Operation...............................57
6.3.1.3 Gen 1 Data Scrambling..............................................................................................58
6.3.1.4 8b/10b Decode Errors for Gen 1 Operation....................................................59
6.3.2 Gen 2 Encoding............................................................................................................. 59
6.3.2.1 Serialization and Deserialization of Data..........................................................59
6.3.2.2 Normative 128b/132b Decode Rules.................................................................60
6.3.2.3 Data Scrambling for Gen 2 Operation.................................................................60
6.3.2.4 128b/132b Decode Errors ......................................................................................63
6.3.3 Special Symbols for Framing and Link Management........................................ 63
6.4 Link Initialization and Training ............................................................................................. 64
6.4.1 Link Training ................................................................................................................ 64
6.4.1.1 Gen 1 Operation ...........................................................................................................64
6.4.1.2 Gen 2 Operation ...........................................................................................................67
6.4.2 Lane Polarity Inversion ............................................................................................. 70
6.4.2.1 Gen 1 Operation ...........................................................................................................70
6.4.2.2 Gen 2 Operation ...........................................................................................................70
6.4.3 Elasticity Buffer and SKP Ordered Set .................................................................. 70
6.4.3.1 SKP Rules (Host/Device/Hub) for Gen 1x1 Operation...............................71
6.4.3.2 SKP Rules (Host/Device/Hub) for Gen 1x2 Operation...............................71
6.4.3.3 SKP Rules (Host/Device/Hub) for Gen 2 Operation....................................71
6.4.4 Compliance Pattern .................................................................................................... 73
6.4.4.1 Gen 2 Compliance Pattern CP9..............................................................................74
6.5 Clock and Jitter ............................................................................................................................ 74
6.5.1 Informative Jitter Budgeting .................................................................................... 74
6.5.2 Normative Clock Recovery Function ..................................................................... 75
6.5.3 Normative Spread Spectrum Clocking (SSC)....................................................... 77
6.5.4 Normative Slew Rate Limit....................................................................................... 78
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6.5.5 Reference Clock Requirements ............................................................................... 78
6.6 Signaling ........................................................................................................................................ 79
6.6.1 Eye Diagrams ................................................................................................................ 79
6.6.2 Voltage Level Definitions .......................................................................................... 80
6.6.3 Tx and Rx Input Parasitics ........................................................................................ 81
6.7 Transmitter Specifications....................................................................................................... 81
6.7.1 Transmitter Electrical Parameters ........................................................................ 81
6.7.2 Low Power Transmitter ............................................................................................ 83
6.7.3 Transmitter Eye ........................................................................................................... 84
6.7.4 Tx Compliance Reference Receiver Equalizer Function .................................. 85
6.7.5 Transmitter De-emphasis ......................................................................................... 85
6.7.5.1 Gen 1 (5GT/sec)...........................................................................................................85
6.7.5.2 Gen 2 (10GT/sec)........................................................................................................86
6.7.6 Entry into Electrical Idle, U1 ................................................................................... 89
6.8 Receiver Specifications ............................................................................................................. 89
6.8.1 Receiver Equalization Training............................................................................... 89
6.8.2 Informative Receiver CTLE Function .................................................................... 90
6.8.2.1 Gen 1 Reference CTLE ...............................................................................................90
6.8.2.2 Gen 2 Reference Equalizer Function...................................................................91
6.8.3 Receiver Electrical Parameters ............................................................................... 93
6.8.4 Receiver Loopback ...................................................................................................... 95
6.8.4.1 Loopback BERT for Gen 1 Operation..................................................................95
6.8.5 Normative Receiver Tolerance Compliance Test............................................... 96
6.9 Low Frequency Periodic Signaling (LFPS) .......................................................................... 98
6.9.1 LFPS Signal Definition................................................................................................ 98
6.9.2 Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3
Wakeup .........................................................................................................................100
6.9.3 Warm Reset .................................................................................................................103
6.9.4 SuperSpeedPlus Capability Declaration .............................................................103
6.9.4.1 Binary Representation of Polling.LFPS........................................................... 103
6.9.4.2 SCD1/SCD2 Definition and Transmission ..................................................... 104
6.9.5 SuperSpeedPlus LFPS Based PWM Message (LBPM)......................................105
6.9.5.1 Introduction to LFPS Based PWM Signaling (LBPS)................................. 105
6.9.5.2 LBPM Definition and Transmission ................................................................. 106
6.10 Transmitter and Receiver DC Specifications ....................................................................107
6.10.1 Informative ESD Protection ...................................................................................107
6.10.2 Informative Short Circuit Requirements ............................................................107
6.10.3 Normative High Impedance Reflections .............................................................107
6.11 Receiver Detection ...................................................................................................................107
6.11.1 Rx Detect Overview...................................................................................................107
6.11.2 Rx Detect Sequence ...................................................................................................108
6.11.3 Upper Limit on Channel Capacitance ..................................................................109
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6.12 Re-timers .....................................................................................................................................109
6.13 Dual-lane Requirements .........................................................................................................109
6.13.1 Operation .....................................................................................................................109
6.13.2 Capability Determination........................................................................................109
6.13.3 Lane Numbering.........................................................................................................109
6.13.4 Data Striping ...............................................................................................................109
6.13.5 Data Scrambling .........................................................................................................110
6.13.6 Ordered Set Rules ......................................................................................................110
6.13.7 Lane Polarity Inversion ...........................................................................................110
6.13.8 Lane-to-Lane Skew....................................................................................................110
6.13.9 Compliance Patterns.................................................................................................111
6.13.10 Receiver Detection ....................................................................................................111
6.13.11 Receiver Loopback ....................................................................................................111
6.13.12 LFPS ...............................................................................................................................111
6.13.13 Ux Exit...........................................................................................................................111
7 Link Layer ...............................................................................................................................................112
7.1 Byte Ordering.............................................................................................................................113
7.1.1 Gen 1 Line Code .........................................................................................................113
7.1.2 Gen 2 Line Code .........................................................................................................113
7.2 Link Management and Flow Control ...................................................................................114
7.2.1 Packets and Packet Framing ..................................................................................114
7.2.1.1 Header Packet Structure ....................................................................................... 114
7.2.1.2 Data Packet Payload Structure ........................................................................... 118
7.2.1.3 Gen 2 Packet Placement ........................................................................................ 122
7.2.2 Link Commands..........................................................................................................122
7.2.2.1 Link Command Structure...................................................................................... 122
7.2.2.2 Link Command Word Definition........................................................................ 123
7.2.2.3 Link Command Placement.................................................................................... 126
7.2.3 Logical Idle ..................................................................................................................127
7.2.4 Link Command Usage for Flow Control, Error Recovery, and Power
Management................................................................................................................127
7.2.4.1 Header Packet Flow Control and Error Recovery...................................... 127
7.2.4.2 Link Power Management and Flow.................................................................. 141
7.3 Link Error Rules/Recovery....................................................................................................146
7.3.1 Overview of Enhanced SuperSpeed Bit Errors .................................................146
7.3.2 Link Error Types, Detection, and Recovery.......................................................146
7.3.3 Link Error Statistics .................................................................................................147
7.3.3.1 Link Error Count....................................................................................................... 147
7.3.3.2 Soft Error Count........................................................................................................ 147
7.3.4 Header Packet Errors ...............................................................................................148
7.3.4.1 Packet Framing Error ............................................................................................. 148
7.3.4.2 Header Packet Error ............................................................................................... 149
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7.3.4.3 Rx Header Sequence Number Error................................................................. 149
7.3.5 Link Command Errors ..............................................................................................149
7.3.6 ACK Tx Header Sequence Number Error ............................................................150
7.3.7 Header Sequence Number Advertisement Error .............................................151
7.3.8 SuperSpeed Rx Header Buffer Credit Advertisement Error .........................151
7.3.9 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit Advertisement Error ..152
7.3.10 Training Sequence Error .........................................................................................152
7.3.11 Gen 1 8b/10b Errors ................................................................................................153
7.3.12 Gen 2x1 Block Header Errors ................................................................................153
7.3.13 Gen 2x2 Block Header Errors ................................................................................153
7.3.14 Summary of Error Types and Recovery ..............................................................154
7.4 PowerOn Reset and Inband Reset........................................................................................156
7.4.1 PowerOn Reset ...........................................................................................................156
7.4.2 Inband Reset ...............................................................................................................157
7.5 Link Training and Status State Machine (LTSSM) ..........................................................158
7.5.1 eSS.Disabled ................................................................................................................160
7.5.1.1 eSS.Disabled for Downstream Ports and Hub Upstream Ports............ 161
7.5.1.2 eSS.Disabled for Upstream Ports of Peripheral Devices ......................... 161
7.5.2 eSS.Inactive .................................................................................................................162
7.5.2.1 eSS.Inactive Substate Machines ......................................................................... 163
7.5.2.2 eSS.Inactive Requirements................................................................................... 163
7.5.2.3 eSS.Inactive.Quiet..................................................................................................... 163
7.5.2.4 eSS.Inactive.Disconnect.Detect........................................................................... 163
7.5.3 Rx.Detect ......................................................................................................................164
7.5.3.1 Rx.Detect Substate Machines .............................................................................. 164
7.5.3.2 Rx.Detect Requirements........................................................................................ 165
7.5.3.3 Rx.Detect.Reset.......................................................................................................... 165
7.5.3.4 Rx.Detect.Active ........................................................................................................ 165
7.5.3.5 Rx.Detect.Active Requirements.......................................................................... 165
7.5.3.6 Exit from Rx.Detect.Active.................................................................................... 166
7.5.3.7 Rx.Detect.Quiet.......................................................................................................... 166
7.5.4 Polling ...........................................................................................................................167
7.5.4.1 Polling Substate Machines.................................................................................... 167
7.5.4.2 Polling Requirements ............................................................................................. 168
7.5.4.3 Polling.LFPS ................................................................................................................ 168
7.5.4.4 Polling.LFPSPlus ....................................................................................................... 173
7.5.4.5 Polling.PortMatch..................................................................................................... 174
7.5.4.6 Polling.PortConfig .................................................................................................... 176
7.5.4.7 Polling.RxEQ ............................................................................................................... 179
7.5.4.8 Polling.Active.............................................................................................................. 180
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7.5.4.9 Polling.Configuration.............................................................................................. 181
7.5.4.10 Polling.Idle................................................................................................................... 183
7.5.5 Compliance Mode ......................................................................................................186
7.5.5.1 Compliance Mode Requirements ...................................................................... 187
7.5.5.2 Exit from Compliance Mode................................................................................. 187
7.5.6 U0 ...................................................................................................................................187
7.5.6.1 U0 Requirements...................................................................................................... 187
7.5.6.2 Exit from U0................................................................................................................ 188
7.5.7 U1 ...................................................................................................................................189
7.5.7.1 U1 Requirements...................................................................................................... 189
7.5.7.2 Exit from U1................................................................................................................ 190
7.5.8 U2 ...................................................................................................................................190
7.5.8.1 U2 Requirements...................................................................................................... 190
7.5.8.2 Exit from U2................................................................................................................ 191
7.5.9 U3 ...................................................................................................................................191
7.5.9.1 U3 Requirements...................................................................................................... 192
7.5.9.2 Exit from U3................................................................................................................ 192
7.5.10 Recovery.......................................................................................................................193
7.5.10.1 Recovery Substate Machines............................................................................... 193
7.5.10.2 Recovery Requirements ........................................................................................ 193
7.5.10.3 Recovery.Active......................................................................................................... 193
7.5.10.4 Recovery.Configuration......................................................................................... 195
7.5.10.5 Recovery.Idle.............................................................................................................. 196
7.5.11 Loopback ......................................................................................................................198
7.5.11.1 Loopback Substate Machines .............................................................................. 198
7.5.11.2 Loopback Requirements ....................................................................................... 199
7.5.11.3 Loopback.Active........................................................................................................ 199
7.5.11.4 Loopback.Exit............................................................................................................. 199
7.5.12 Hot Reset......................................................................................................................200
7.5.12.1 Hot Reset Substate Machines .............................................................................. 201
7.5.12.2 Hot Reset Requirements ....................................................................................... 201
7.5.12.3 Hot Reset.Active........................................................................................................ 201
7.5.12.4 Hot Reset.Exit............................................................................................................. 202
8 Protocol Layer .......................................................................................................................................204
8.1 Enhanced SuperSpeed Transactions ...................................................................................205
8.1.1 Transactions on a SuperSpeed Bus Instance.....................................................205
8.1.2 Transactions on a SuperSpeedPlus Bus Instance ............................................206
8.1.2.1 Simultaneous IN Transactions............................................................................ 206
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8.1.2.2 Transaction Reordering......................................................................................... 206
8.2 Packet Types ..............................................................................................................................206
8.3 Packet Formats ..........................................................................................................................207
8.3.1 Fields Common to all Headers ...............................................................................207
8.3.1.1 Reserved Values and Reserved Field Handling........................................... 207
8.3.1.2 Type Field .................................................................................................................... 208
8.3.1.3 CRC-16........................................................................................................................... 208
8.3.1.4 Link Control Word ................................................................................................... 208
8.4 Link Management Packet (LMP) ..........................................................................................209
8.4.1 Subtype Field ..............................................................................................................209
8.4.2 Set Link Function.......................................................................................................210
8.4.3 U2 Inactivity Timeout ..............................................................................................211
8.4.4 Vendor Device Test...................................................................................................211
8.4.5 Port Capabilities ........................................................................................................212
8.4.6 Port Configuration ....................................................................................................213
8.4.7 Port Configuration Response .................................................................................214
8.4.8 Precision Time Measurement ................................................................................215
8.4.8.1 PTM Bus Interval Boundary Counters ............................................................ 215
8.4.8.2 LDM Protocol.............................................................................................................. 216
8.4.8.3 LDM State Machines ................................................................................................ 218
8.4.8.4 LDM Link Delay ......................................................................................................... 223
8.4.8.5 PTM Bus Interval Boundary Device Calculation......................................... 224
8.4.8.6 PTM Bus Interval Boundary Host Calculation............................................. 225
8.4.8.7 PTM Hub ITP Regeneration ................................................................................. 225
8.4.8.8 Performance ............................................................................................................... 226
8.4.8.9 LDM Rules.................................................................................................................... 228
8.4.8.10 LDM and Hubs............................................................................................................ 229
8.4.8.11 Link Delay Measurement (LDM) LMP............................................................. 229
8.5 Transaction Packet (TP) .........................................................................................................230
8.5.1 Acknowledgement (ACK) Transaction Packet ..................................................231
8.5.2 Not Ready (NRDY) Transaction Packet...............................................................233
8.5.3 Endpoint Ready (ERDY) Transaction Packet ....................................................234
8.5.4 STATUS Transaction Packet ...................................................................................235
8.5.5 STALL Transaction Packet ......................................................................................235
8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet..................236
8.5.6.1 Function Wake Device Notification.................................................................. 237
8.5.6.2 Latency Tolerance Message (LTM) Device Notification.......................... 237
8.5.6.3 Bus Interval Adjustment Message Device Notification............................ 238
8.5.6.4 Function Wake Notification................................................................................. 238
8.5.6.5 Latency Tolerance Messaging............................................................................. 238
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8.5.6.6 Bus Interval Adjustment Message..................................................................... 239
8.5.6.7 Sublink Speed Device Notification.................................................................... 241
8.5.7 PING Transaction Packet.........................................................................................243
8.5.8 PING_RESPONSE Transaction Packet ..................................................................243
8.6 Data Packet (DP) .......................................................................................................................244
8.7 Isochronous Timestamp Packet (ITP) ................................................................................246
8.8 Addressing Triple .....................................................................................................................247
8.9 Route String Field .....................................................................................................................247
8.9.1 Route String Port Field ............................................................................................248
8.9.2 Route String Port Field Width ...............................................................................248
8.9.3 Port Number ...............................................................................................................248
8.10 Transaction Packet Usages ....................................................................................................248
8.10.1 Flow Control Conditions .........................................................................................248
8.10.2 Burst Transactions ....................................................................................................249
8.10.2.1 Enhanced SuperSpeed Burst Transactions................................................... 249
8.10.2.2 SuperSpeedPlus Burst Transactions................................................................ 250
8.10.3 Short Packets ..............................................................................................................250
8.10.4 SuperSpeedPlus Transaction Reordering ..........................................................251
8.11 TP or DP Responses .................................................................................................................253
8.11.1 Device Response to TP Requesting Data ............................................................254
8.11.2 Host Response to Data Received from a Device ...............................................254
8.11.3 Device Response to Data Received from the Host ...........................................255
8.11.4 Device Response to a SETUP DP ...........................................................................256
8.12 TP Sequences .............................................................................................................................257
8.12.1 Bulk Transactions......................................................................................................257
8.12.1.1 State Machine Notation Information ............................................................... 257
8.12.1.2 Bulk IN Transactions............................................................................................... 258
8.12.1.3 Bulk OUT Transactions .......................................................................................... 259
8.12.1.4 Bulk Streaming Protocol ....................................................................................... 261
8.12.2 Control Transfers ......................................................................................................287
8.12.2.1 Reporting Status Results....................................................................................... 290
8.12.2.2 Variable-length Data Stage................................................................................... 291
8.12.2.3 STALL TPs Returned by Control Pipes............................................................ 291
8.12.3 Bus Interval and Service Interval .........................................................................291
8.12.4 Interrupt Transactions ............................................................................................292
8.12.4.1 Interrupt IN Transactions..................................................................................... 292
8.12.4.2 Interrupt OUT Transactions ................................................................................ 295
8.12.5 Host Timing Information.........................................................................................298
8.12.6 Isochronous Transactions ......................................................................................299
8.12.6.1 Enhanced SuperSpeed Isochronous Transactions .................................... 299
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8.12.6.2 Host Flexibility in Performing SuperSpeed Isochronous
Transactions ............................................................................................................... 308
8.12.6.3 SuperSpeedPlus Isochronous Transactions ................................................. 309
8.12.6.4 Host Flexibility in Performing SuperSpeedPlus Isochronous
Transactions ............................................................................................................... 310
8.12.6.5 Device Response to Isochronous IN Transactions..................................... 311
8.12.6.6 Host Processing of Isochronous IN Transactions ...................................... 311
8.12.6.7 Device Response to an Isochronous OUT Data Packet ............................ 312
8.13 Timing Parameters ...................................................................................................................312
9 Device Framework ...............................................................................................................................316
9.1 USB Device States .....................................................................................................................316
9.1.1 Visible Device States.................................................................................................316
9.1.1.1 Attached........................................................................................................................ 319
9.1.1.2 Powered........................................................................................................................ 319
9.1.1.3 Default........................................................................................................................... 320
9.1.1.4 Address ......................................................................................................................... 320
9.1.1.5 Configured ................................................................................................................... 320
9.1.1.6 Suspended ................................................................................................................... 321
9.1.1.7 Error............................................................................................................................... 321
9.1.2 Bus Enumeration .......................................................................................................321
9.2 Generic Device Operations.....................................................................................................322
9.2.1 Dynamic Attachment and Removal ......................................................................322
9.2.2 Address Assignment .................................................................................................322
9.2.3 Configuration ..............................................................................................................322
9.2.4 Data Transfer ..............................................................................................................323
9.2.5 Power Management ..................................................................................................323
9.2.5.1 Power Budgeting ...................................................................................................... 323
9.2.5.2 Changing Device Suspend State ......................................................................... 324
9.2.5.3 Function Suspend..................................................................................................... 325
9.2.5.4 Changing Function Suspend State..................................................................... 325
9.2.6 Request Processing ...................................................................................................325
9.2.6.1 Request Processing Timing.................................................................................. 326
9.2.6.2 Reset/Resume Recovery Time ........................................................................... 326
9.2.6.3 Set Address Processing.......................................................................................... 326
9.2.6.4 Standard Device Requests .................................................................................... 326
9.2.6.5 Class-specific Requests .......................................................................................... 326
9.2.6.6 Speed Dependent Descriptors ............................................................................ 327
9.2.7 Request Error .............................................................................................................327
9.3 USB Device Requests ...............................................................................................................327
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9.3.1 bmRequestType .........................................................................................................328
9.3.2 bRequest.......................................................................................................................328
9.3.3 wValue ..........................................................................................................................328
9.3.4 wIndex ..........................................................................................................................329
9.3.5 wLength........................................................................................................................329
9.4 Standard Device Requests ......................................................................................................329
9.4.1 Clear Feature ..............................................................................................................332
9.4.2 Get Configuration ......................................................................................................333
9.4.3 Get Descriptor ............................................................................................................333
9.4.4 Get Interface ...............................................................................................................334
9.4.5 Get Status .....................................................................................................................335
9.4.6 Set Address ..................................................................................................................338
9.4.7 Set Configuration.......................................................................................................339
9.4.8 Set Descriptor .............................................................................................................339
9.4.9 Set Feature...................................................................................................................340
9.4.10 Set Interface ................................................................................................................341
9.4.11 Set Isochronous Delay..............................................................................................342
9.4.12 Set SEL ..........................................................................................................................342
9.4.13 Synch Frame................................................................................................................343
9.4.14 Events and Their Effect on Device Parameters ................................................343
9.5 Descriptors .................................................................................................................................344
9.6 Standard USB Descriptor Definitions .................................................................................345
9.6.1 Device............................................................................................................................345
9.6.2 Binary Device Object Store (BOS) ........................................................................347
9.6.2.1 USB 2.0 Extension .................................................................................................... 349
9.6.2.2 SuperSpeed USB Device Capability .................................................................. 350
9.6.2.3 Container ID................................................................................................................ 352
9.6.2.4 Platform Descriptor................................................................................................. 352
9.6.2.5 SuperSpeedPlus USB Device Capability.......................................................... 353
9.6.2.6 Precision Time Measurement............................................................................. 355
9.6.2.7 Configuration Summary Descriptor................................................................. 355
9.6.3 Configuration ..............................................................................................................355
9.6.4 Interface Association................................................................................................357
9.6.5 Interface .......................................................................................................................358
9.6.6 Endpoint.......................................................................................................................360
9.6.7 SuperSpeed Endpoint Companion ........................................................................362
9.6.8 SuperSpeedPlus Isochronous Endpoint Companion.......................................364
9.6.9 String .............................................................................................................................365
9.7 Device Class Definitions .........................................................................................................366
9.7.1 Descriptors ..................................................................................................................366
9.7.2 Interface(s)..................................................................................................................366
9.7.3 Requests .......................................................................................................................366
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9.8 Constants .....................................................................................................................................366
10 Hub, Host Downstream Port, and Device Upstream Port Specification ...............................367
10.1 Hub Feature Summary.............................................................................................................367
10.1.1 Connecting to an Enhanced SuperSpeed Capable Host..................................370
10.1.2 Connecting to a USB 2.0 Host.................................................................................371
10.1.3 Hub Connectivity .......................................................................................................371
10.1.3.1 Routing Information................................................................................................ 371
10.1.3.2 SuperSpeed Hub Packet Signaling Connectivity......................................... 373
10.1.3.3 SuperSpeedPlus Hub Packet Routing .............................................................. 373
10.1.4 Resume Connectivity ................................................................................................374
10.1.5 Hub Fault Recovery Mechanisms ..........................................................................374
10.1.6 Hub Buffer Architecture ..........................................................................................375
10.1.6.1 SuperSpeed Hub Buffer Architecture .............................................................. 375
10.1.6.2 SuperSpeedPlus Hub Buffer Architecture ..................................................... 376
10.2 Hub Power Management.........................................................................................................376
10.2.1 Link States ...................................................................................................................376
10.2.2 Hub Downstream Port U1/U2 Timers .................................................................376
10.2.3 Downstream/Upstream Port Link State Transitions ......................................377
10.3 Hub Downstream Facing Ports .............................................................................................377
10.3.1 Hub Downstream Facing Port State Descriptions ...........................................380
10.3.1.1 DSPORT.Powered-off.............................................................................................. 380
10.3.1.2 DSPORT.Disconnected (Waiting for eSS Connect)..................................... 381
10.3.1.3 DSPORT.Training...................................................................................................... 382
10.3.1.4 DSPORT.ERROR......................................................................................................... 382
10.3.1.5 DSPORT.Enabled....................................................................................................... 383
10.3.1.6 DSPORT.Resetting.................................................................................................... 383
10.3.1.7 DSPORT.Compliance ............................................................................................... 384
10.3.1.8 DSPORT.Loopback ................................................................................................... 384
10.3.1.9 DSPORT.Disabled...................................................................................................... 384
10.3.1.10 DSPORT.Powered-off-detect ............................................................................... 384
10.3.1.11 DSPORT.Powered-off-reset.................................................................................. 385
10.3.2 Disconnect Detect Mechanism...............................................................................385
10.3.3 Labeling ........................................................................................................................385
10.4 Hub Downstream Facing Port Power Management........................................................386
10.4.1 Downstream Facing Port PM Timers ...................................................................386
10.4.2 Hub Downstream Facing Port State Descriptions ...........................................388
10.4.2.1 Enabled U0 States..................................................................................................... 388
10.4.2.2 Attempt U0 – U1 Transition................................................................................. 389
10.4.2.3 Attempt U0 – U2 Transition................................................................................. 389
10.4.2.4 Link in U1..................................................................................................................... 390
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10.4.2.5 Link in U2..................................................................................................................... 390
10.4.2.6 Link in U3..................................................................................................................... 391
10.5 Hub Upstream Facing Ports ...................................................................................................391
10.5.1 Upstream Facing Port State Descriptions ..........................................................392
10.5.1.1 USPORT.Powered-off.............................................................................................. 392
10.5.1.2 USPORT.Powered-on .............................................................................................. 393
10.5.1.3 USPORT.Training...................................................................................................... 393
10.5.1.4 USPORT.Connected/Enabled .............................................................................. 393
10.5.1.5 USPORT.Error ............................................................................................................ 393
10.5.2 Hub Connect State Machine....................................................................................394
10.5.2.1 Hub Connect State Descriptions ........................................................................ 394
10.5.2.2 HCONNECT.Powered-off....................................................................................... 394
10.5.2.3 HCONNECT.Attempt ESS Connect..................................................................... 394
10.5.2.4 HCONNECT.Connected on ESS............................................................................ 395
10.6 Upstream Facing Port Power Management.......................................................................395
10.6.1 Upstream Facing Port PM Timer...........................................................................397
10.6.2 Hub Upstream Facing Port State Descriptions .................................................397
10.6.2.1 Enabled U0 States..................................................................................................... 397
10.6.2.2 Attempt U0 – U1 Transition................................................................................. 398
10.6.2.3 Attempt U0 – U2 Transition................................................................................. 399
10.6.2.4 Link in U1..................................................................................................................... 399
10.6.2.5 Link in U2..................................................................................................................... 399
10.6.2.6 Link in U3..................................................................................................................... 399
10.7 SuperSpeed Hub Header Packet Forwarding and Data Repeater ..............................400
10.7.1 SuperSpeed Hub Elasticity Buffer ........................................................................400
10.7.2 SKP Ordered Sets .......................................................................................................400
10.7.3 Interpacket Spacing ..................................................................................................400
10.7.4 SuperSpeed Header Packet Buffer Architecture ..............................................400
10.7.5 SuperSpeed Packet Connectivity ..........................................................................402
10.8 SuperSpeedPlus Store and Forward Behavior .................................................................402
10.8.1 Hub Elasticity Buffer ................................................................................................402
10.8.2 SKP Ordered Sets .......................................................................................................403
10.8.3 Interpacket Spacing ..................................................................................................403
10.8.4 Upstream Flowing Buffering ..................................................................................403
10.8.5 Downstream Flowing Buffering ............................................................................403
10.8.6 SuperSpeedPlus Hub Arbitration of Packets .....................................................404
10.8.6.1 Arbitration Weight................................................................................................... 404
10.8.6.2 Direction Independent Packet Selection........................................................ 405
10.8.6.3 Downstream Flowing Packet Reception and Selection ........................... 405
10.8.6.4 Upstream Flowing Packet Reception and Selection.................................. 405
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10.8.7 SuperSpeedPlus Upstream Flowing Packet Modifications ............................407
10.8.8 SuperSpeedPlus Downstream Controller ...........................................................408
10.9 Port State Machines .................................................................................................................408
10.9.1 Port Transmit State Machine .................................................................................408
10.9.2 Port Transmit State Descriptions .........................................................................410
10.9.2.1 Tx IDLE.......................................................................................................................... 410
10.9.2.2 Tx Header..................................................................................................................... 410
10.9.2.3 Tx Data .......................................................................................................................... 410
10.9.2.4 Tx Data Abort............................................................................................................. 410
10.9.2.5 Tx Link Command .................................................................................................... 410
10.9.3 Port Receive State Machine ....................................................................................411
10.9.4 Port Receive State Descriptions ............................................................................411
10.9.4.1 Rx Default..................................................................................................................... 411
10.9.4.2 Rx Data .......................................................................................................................... 412
10.9.4.3 Rx Header..................................................................................................................... 412
10.9.4.4 Process Header Packet........................................................................................... 412
10.9.4.5 Rx Link Command .................................................................................................... 417
10.9.4.6 Process Link Command ......................................................................................... 417
10.10 Suspend and Resume ...............................................................................................................418
10.11 Hub Upstream Port Reset Behavior ....................................................................................418
10.12 Hub Port Power Control .........................................................................................................419
10.12.1 Multiple Gangs (Only supported for downstream USB Standard-A
ports).............................................................................................................................419
10.13 Hub Controller ...........................................................................................................................420
10.13.1 Endpoint Organization.............................................................................................420
10.13.2 Hub Information Architecture and Operation ..................................................421
10.13.3 Port Change Information Processing...................................................................422
10.13.4 Hub and Port Status Change Bitmap....................................................................422
10.13.5 Over-current Reporting and Recovery................................................................423
10.13.6 Enumeration Handling.............................................................................................424
10.14 Hub Configuration ....................................................................................................................424
10.15 Descriptors .................................................................................................................................426
10.15.1 Standard Descriptors for Hub Class.....................................................................427
10.15.2 Class-specific Descriptors .......................................................................................432
10.15.2.1 Hub Descriptor .......................................................................................................... 432
10.16 Requests ......................................................................................................................................434
10.16.1 Standard Requests ....................................................................................................434
10.16.2 Class-specific Requests ............................................................................................434
10.16.2.1 Clear Hub Feature .................................................................................................... 436
10.16.2.2 Clear Port Feature.................................................................................................... 436
10.16.2.3 Get Hub Descriptor .................................................................................................. 437
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Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
10.16.2.4 Get Hub Status ........................................................................................................... 438
10.16.2.5 Get Port Error Count............................................................................................... 439
10.16.2.6 Get Port Status ........................................................................................................... 439
10.16.2.7 Set Hub Descriptor................................................................................................... 446
10.16.2.8 Set Hub Feature......................................................................................................... 446
10.16.2.9 Set Hub Depth ............................................................................................................ 446
10.16.2.10Set Port Feature ........................................................................................................ 447
10.17 Host Root (Downstream) Ports ............................................................................................450
10.18 Peripheral Device Upstream Ports ......................................................................................451
10.18.1 Peripheral Device Upstream Ports .......................................................................451
10.18.2 Peripheral Device Upstream Port State Machine.............................................452
10.18.2.1 USDPORT.Powered-off........................................................................................... 452
10.18.2.2 USDPORT.Powered on ........................................................................................... 452
10.18.2.3 USDPORT.Training................................................................................................... 453
10.18.2.4 USDPORT.Connected/Enabled........................................................................... 453
10.18.2.5 USDPORT.Error ......................................................................................................... 453
10.18.2.6 USDPORT.Disabled .................................................................................................. 453
10.18.2.7 USDPORT.Disabled_Error ..................................................................................... 454
10.19 Hub Chapter Parameters ........................................................................................................454
11 Interoperability and Power Delivery..............................................................................................457
11.1 USB 3.2 Host Support for USB 2.0........................................................................................457
11.2 USB 3.2 Hub Support for USB 2.0.........................................................................................457
11.3 USB 3.2 Device Support for USB 2.0....................................................................................458
11.4 Power Distribution...................................................................................................................458
11.4.1 Classes of Devices and Connections.....................................................................458
11.4.1.1 Self-powered Hubs................................................................................................... 459
11.4.1.2 Low-power Bus-powered Devices.................................................................... 460
11.4.1.3 High-power Bus-powered Devices ................................................................... 461
11.4.1.4 Self-powered Devices ............................................................................................. 461
11.4.2 Steady-State Voltage Drop Budget .......................................................................462
11.4.3 Power Control During Suspend/Resume ...........................................................463
11.4.4 Dynamic Attach and Detach ...................................................................................464
11.4.4.1 Inrush Current Limiting ........................................................................................ 464
11.4.4.2 Dynamic Detach ........................................................................................................ 465
11.4.5 VBUS Electrical Characteristics ..............................................................................465
A Gen 1 Symbol Encoding ......................................................................................................................466
B Symbol Scrambling...............................................................................................................................474
B.1 Data Scrambling ........................................................................................................................474
C Power Management..............................................................................................................................480
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D Example Packets ...................................................................................................................................481
E Repeaters ................................................................................................................................................484
E.1 Overview .....................................................................................................................................484
E.1.1 Term Definitions ........................................................................................................484
E.1.2 Scope of the Re-time Connectivity and Link Delay Budget...........................485
E.1.2.1 Re-timer Connectivity Models ............................................................................ 485
E.1.2.2 Link Delay Budget Requirement........................................................................ 486
E.2 Re-timer Architectural Overview and Requirement ......................................................487
E.2.1 Architectural Overview ...........................................................................................487
E.2.2 General Requirements .............................................................................................489
E.2.2.1 Physical Layer Requirements ............................................................................. 489
E.2.2.2 Link Layer Requirements ..................................................................................... 489
E.2.2.3 x2 Re-timer Requirements ................................................................................... 490
E.3 Re-timer Training and Status State Machine (RTSSM)..................................................490
E.3.1 Warm Reset .................................................................................................................491
E.3.2 Rx.Detect ......................................................................................................................492
E.3.2.1 Rx.Detect Requirements........................................................................................ 492
E.3.2.2 Exit from Rx.Detect.................................................................................................. 493
E.3.3 eSS.Disabled ................................................................................................................494
E.3.3.1 eSS.Disabled Requirements ................................................................................. 494
E.3.3.2 Exit from eSS.Disabled ........................................................................................... 494
E.3.4 Polling ...........................................................................................................................494
E.3.4.1 Polling.SpeedDetect................................................................................................. 495
E.3.4.2 Polling.PortConfig .................................................................................................... 496
E.3.4.3 Polling.RxEQ ............................................................................................................... 498
E.3.4.4 Polling.TSx ................................................................................................................... 499
E.3.4.5 Polling.Idle................................................................................................................... 504
E.3.5 Compliance Mode ......................................................................................................505
E.3.5.1 Compliance Mode Requirements ...................................................................... 505
E.3.5.2 Exit from Compliance Mode................................................................................. 506
E.3.6 BLR Compliance Mode .............................................................................................506
E.3.6.1 BLR Compliance Mode Requirements............................................................. 506
E.3.6.2 Exit from BLR Compliance Mode....................................................................... 506
E.3.7 U0 ...................................................................................................................................506
E.3.7.1 U0 Requirements...................................................................................................... 506
E.3.7.2 Exit from U0................................................................................................................ 507
E.3.8 U1 ...................................................................................................................................507
E.3.8.1 U1 Requirements...................................................................................................... 507
E.3.8.2 Exit from U1................................................................................................................ 508
Revision 1.0 - xxiii - Universal Serial Bus 3.2
September 22, 2017 Specification
Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
E.3.9 U2 ...................................................................................................................................509
E.3.9.1 U2 Requirements...................................................................................................... 509
E.3.9.2 Exit from U2................................................................................................................ 509
E.3.10 U3 ...................................................................................................................................509
E.3.10.1 U3 Requirements...................................................................................................... 509
E.3.10.2 Exit from U3................................................................................................................ 510
E.3.11 Recovery.......................................................................................................................511
E.3.11.1 Exit from Recovery.TSx.......................................................................................... 511
E.3.11.2 Recovery.TSx .............................................................................................................. 511
E.3.11.3 Recovery.Idle.............................................................................................................. 512
E.3.12 PassThrough Loopback............................................................................................513
E.3.12.1 PassThrough Loopback Requirements........................................................... 513
E.3.12.2 Exit from PassThrough Loopback..................................................................... 513
E.3.13 Local Loopback...........................................................................................................514
E.3.13.1 Local Loopback Requirements ........................................................................... 514
E.3.13.2 Exit from Local Loopback.Active ....................................................................... 514
E.3.13.3 Exit from Local Loopback.Exit............................................................................ 514
E.3.14 Hot Reset......................................................................................................................514
E.3.14.1 Hot Reset Requirements ....................................................................................... 514
E.3.14.2 Exit from Hot Reset.................................................................................................. 515
E.4 SRIS Re-timer Clock Offset Compensation ........................................................................515
E.4.1 Gen 1x1 Operation ....................................................................................................515
E.4.2 Gen 1x2 Operation ....................................................................................................515
E.4.3 Gen 2 Operation .........................................................................................................515
E.5 Bit-Level Re-timer Jitter Transfer Function .....................................................................516
E.6 Compliance .................................................................................................................................518
E.6.1 Host and Device Product Compliance .................................................................518
E.6.2 Component-Level Re-timer Compliance.............................................................518
Figures
Figure 2-1. Port and Link Pictorial .....................................................................................................................................14
Figure 3-1. USB 3.2 Dual Bus System Architecture .....................................................................................................16
Figure 3-2. USB 3.2 Terminology Reference Model ....................................................................................................19
Figure 3-3. Enhanced SuperSpeed Bus Communications Layers and Power Management Elements .20
Figure 3-4. Examples of Supported USB 3.2 USB Physical Device Topologies................................................27
Figure 3-5. SuperSpeed Only Enhanced SuperSpeed Peripheral Device Configuration.............................27
Figure 3-6. Enhanced SuperSpeed Device Configuration.........................................................................................28
Figure 3-7. Multiple SuperSpeed Bus Instances in an Enhanced SuperSpeed System................................29
Figure 4-1. Enhanced SuperSpeed IN Transaction Protocol...................................................................................37
Figure 4-2. Enhanced SuperSpeed OUT Transaction Protocol ..............................................................................38
Figure 4-3. Enhanced SuperSpeed IN Stream Example.............................................................................................42
Figure 6-1. SuperSpeed Physical Layer ............................................................................................................................51
Figure 6-2. Transmitter Block Diagram............................................................................................................................52
Revision 1.0 - xxiv - Universal Serial Bus 3.2
September 22, 2017 Specification
Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
Figure 6-3. Gen 1 Receiver Block Diagram......................................................................................................................53
Figure 6-4. Gen 2 Receiver Block Diagram......................................................................................................................54
Figure 6-5. Channel Models ...................................................................................................................................................55
Figure 6-6. Electrical Test Points ........................................................................................................................................56
Figure 6-7. Character to Symbol Mapping.......................................................................................................................57
Figure 6-8. Bit Transmission Order....................................................................................................................................57
Figure 6-9. LFSR with Scrambling Polynomial..............................................................................................................58
Figure 6-10. Gen 2 Serialization and Deserialization Order....................................................................................59
Figure 6-11. Gen 2 Bit Transmission Order and Framing ........................................................................................60
Figure 6-12. LFSR for use in Gen 2 operation................................................................................................................62
Figure 6-13. Jitter Filtering – “Golden PLL” and Jitter Transfer Functions.......................................................75
Figure 6-14. “Golden PLL” and Jitter Transfer Functions for Gen 1 Operation ..............................................76
Figure 6-15. “Golden PLL” and Jitter Transfer Functions for Gen 2 Operation ..............................................76
Figure 6-16. Example of Period Modulation from Triangular SSC.......................................................................78
Figure 6-17. Eye Masks............................................................................................................................................................79
Figure 6-18. Single-ended and Differential Voltage Levels .....................................................................................81
Figure 6-19. Device Termination Schematic ..................................................................................................................81
Figure 6-20. Tx Normative Setup with Reference Channel .....................................................................................85
Figure 6-21. De-Emphasis Waveform ...............................................................................................................................85
Figure 6-22. 3-tap Transmit Equalizer Structure.........................................................................................................86
Figure 6-23. Example Output Waveform for 3-tap Transmit Equalizer ............................................................87
Figure 6-24. Configuration for Measuring Transmitter Equalization.................................................................88
Figure 6-25. Example waveforms for measuring transmitter equalization.....................................................89
Figure 6-26. Frequency Spectrum of TSEQ.....................................................................................................................90
Figure 6-27. Gen 1 Tx Compliance Rx EQ Transfer Function..................................................................................91
Figure 6-28. Gen 2 Compliance Rx EQ Transfer Function........................................................................................92
Figure 6-29. Gen 2 reference DFE Function ...................................................................................................................93
Figure 6-30. Rx Jitter Tolerance Setup..............................................................................................................................97
Figure 6-31. Jitter Tolerance Curve....................................................................................................................................97
Figure 6-32. LFPS Signaling ...................................................................................................................................................99
Figure 6-33. U1 Exit, U2 Exit, and U3 Wakeup LFPS Handshake Timing Diagram ....................................101
Figure 6-34. Example of Warm Reset Out of U3........................................................................................................103
Figure 6-35. Example of Binary Representation based on Polling.LFPS ........................................................104
Figure 6-36. SCD1/SCD2 transmission..........................................................................................................................104
Figure 6-37. Logic Representation of LBPS .................................................................................................................106
Figure 6-38. LBPM Transmission Examples................................................................................................................106
Figure 6-39. Rx Detect Schematic ....................................................................................................................................108
Figure 6-40. Transmitter Data Striping Example......................................................................................................110
Figure 7-1. Link Layer ...........................................................................................................................................................112
Figure 7-2. Byte Ordering ....................................................................................................................................................113
Figure 7-3. Header Packet with HPSTART, Packet Header, and Link Control Word.................................115
Figure 7-4. Non-deferred Gen 2 DPH Format.............................................................................................................115
Figure 7-5. Packet Header ...................................................................................................................................................115
Figure 7-6. CRC-16 Remainder Generation .................................................................................................................116
Figure 7-7. Link Control Word...........................................................................................................................................117
Figure 7-8. CRC-5 Remainder Generation....................................................................................................................118
Figure 7-9. Data Packet Payload with CRC-32 and Framing ................................................................................119
Figure 7-10. CRC-32 Remainder Generation...............................................................................................................119
Figure 7-11. Data Packet with Data Packet Header Followed by Data Packet Payload ...........................121
Figure 7-12. Link Command Structure ..........................................................................................................................122
Figure 7-13. Link Command Word Structure .............................................................................................................123
Figure 7-14. State Diagram of the Link Training and Status State Machine..................................................160
Figure 7-15. eSS.Disabled Substate Machine ..............................................................................................................162
Figure 7-16. eSS.Inactive Substate Machine................................................................................................................164
Figure 7-17. Rx.Detect Substate Machine.....................................................................................................................167
Revision 1.0 - xxv - Universal Serial Bus 3.2
September 22, 2017 Specification
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Figure 7-18. Example Timing Diagrams of a SSP Port Switching to SS Operation.....................................171
Figure 7-19. Example Timing Diagrams of a SSP Port Switching to SS Operation in Polling.LFPSPlus
.................................................................................................................................................................................................174
Figure 7-20. Example Timing Diagrams of Two Ports in x2 Operation ..........................................................178
Figure 7-21. Polling Substate Machine ..........................................................................................................................186
Figure 7-22. U1.........................................................................................................................................................................190
Figure 7-23. U2.........................................................................................................................................................................191
Figure 7-24. U3.........................................................................................................................................................................193
Figure 7-25. Recovery Substate Machine .....................................................................................................................198
Figure 7-26. Loopback Substate Machine.....................................................................................................................200
Figure 7-27. Hot Reset Substate Machine.....................................................................................................................203
Figure 8-1. Protocol Layer Highlighted .........................................................................................................................204
Figure 8-2. Example Transaction Packet ......................................................................................................................207
Figure 8-3. Link Control Word Detail .............................................................................................................................208
Figure 8-4. Link Management Packet Structure ........................................................................................................209
Figure 8-5. Set Link Function LMP...................................................................................................................................210
Figure 8-6. U2 Inactivity Timeout LMP .........................................................................................................................211
Figure 8-7. Vendor Device Test LMP ..............................................................................................................................211
Figure 8-8. Port Capability LMP........................................................................................................................................212
Figure 8-9. Port Configuration LMP................................................................................................................................214
Figure 8-10. Port Configuration Response LMP ........................................................................................................215
Figure 8-11. Link Delay Measurement Protocol........................................................................................................217
Figure 8-12. PTM ITP Protocol..........................................................................................................................................218
Figure 8-13. LDM State Machine Notation ...................................................................................................................219
Figure 8-14. LDM Requester State Machine ................................................................................................................220
Figure 8-15. LDM Responder State Machine...............................................................................................................222
Figure 8-16. PTM Path Performance Contributors ..................................................................................................227
Figure 8-17. LDM LMP ..........................................................................................................................................................229
Figure 8-18. ACK Transaction Packet.............................................................................................................................231
Figure 8-19. NRDY Transaction Packet .........................................................................................................................234
Figure 8-20. ERDY Transaction Packet..........................................................................................................................234
Figure 8-21. STATUS Transaction Packet.....................................................................................................................235
Figure 8-22. STALL Transaction Packet........................................................................................................................235
Figure 8-23. Device Notification Transaction Packet..............................................................................................236
Figure 8-24. Function Wake Device Notification ......................................................................................................237
Figure 8-25. Latency Tolerance Message Device Notification.............................................................................237
Figure 8-26. Bus Interval Adjustment Message Device Notification ................................................................238
Figure 8-27. Sublink Speed Device Notification ........................................................................................................241
Figure 8-28. PING Transaction Packet...........................................................................................................................243
Figure 8-29. PING_RESPONSE Transaction Packet ..................................................................................................243
Figure 8-30. Example Data Packet...................................................................................................................................244
Figure 8-31. Isochronous Timestamp Packet.............................................................................................................246
Figure 8-32. Route String Detail .......................................................................................................................................248
Figure 8-33. Sample Concurrent BULK IN Transactions .......................................................................................252
Figure 8-34. Sample Concurrent BULK and Isochronous IN Transactions ...................................................253
Figure 8-35. Legend for State Machines........................................................................................................................258
Figure 8-36. Sample BULK IN Sequence........................................................................................................................260
Figure 8-37. Sample BULK OUT Sequence ...................................................................................................................261
Figure 8-38. General Stream Protocol State Machine (SPSM).............................................................................262
Figure 8-39. Device IN Stream Protocol State Machine (DISPSM)....................................................................265
Figure 8-40. Device IN Move Data State Machine (DIMDSM)..............................................................................268
Figure 8-41. Device OUT Stream Protocol State Machine (DOSPSM)..............................................................271
Figure 8-42. Device OUT Move Data State Machine (DOMDSM)........................................................................274
Figure 8-43. Host IN Stream Protocol State Machine (HISPSM) ........................................................................276
Figure 8-44. Host IN Move Data State Machine (HIMDSM)..................................................................................279
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Figure 8-45. Host OUT Stream Protocol State Machine (HOSPSM) ..................................................................282
Figure 8-46. Host OUT Move Data State Machine (HOMDSM)............................................................................285
Figure 8-47. Control Read Sequence...............................................................................................................................289
Figure 8-48. Control Write Sequence .............................................................................................................................290
Figure 8-49. Host Sends Interrupt IN Transaction in Each Service Interval.................................................293
Figure 8-50. Host Stops Servicing Interrupt IN Transaction Once NRDY is Received..............................293
Figure 8-51. Host Resumes IN Transaction after Device Sent ERDY................................................................294
Figure 8-52. Endpoint Sends STALL TP.........................................................................................................................294
Figure 8-53. Host Detects Error in Data and Device Resends Data...................................................................295
Figure 8-54. Host Sends Interrupt OUT Transaction in Each Service Interval ............................................296
Figure 8-55. Host Stops Servicing Interrupt OUT Transaction Once NRDY is Received .........................296
Figure 8-56. Host Resumes Sending Interrupt OUT Transaction After Device Sent ERDY....................297
Figure 8-57. Device Detects Error in Data and Host Resends Data...................................................................297
Figure 8-58. Endpoint Sends STALL TP.........................................................................................................................297
Figure 8-59. Multiple Active Isochronous Endpoints with Aligned Service Interval Boundaries.......299
Figure 8-60. Enhanced SuperSpeed Isochronous IN Transaction Format.....................................................300
Figure 8-61. Enhanced SuperSpeed Isochronous OUT Transaction Format................................................300
Figure 8-62. Sample Enhanced SuperSpeed Isochronous IN Transaction.....................................................302
Figure 8-63. Sample Enhanced SuperSpeed Isochronous OUT Transaction ................................................303
Figure 8-64. Sample Enhanced SuperSpeed Isochronous IN Transaction.....................................................304
Figure 8-65. Sample Enhanced SuperSpeed Isochronous OUT Transaction ................................................305
Figure 8-66. Sample Smart Enhanced SuperSpeed Isochronous IN Transaction.......................................307
Figure 8-67. Sample Smart Enhanced SuperSpeed Isochronous OUT Transaction...................................308
Figure 8-68. Sample Pipeline Isochronous IN Transactions ................................................................................310
Figure 9-1. Peripheral State Diagram and Hub State Diagram (Enhanced SuperSpeed Portion Only)
.................................................................................................................................................................................................317
Figure 9-2. wIndex Format when Specifying an Endpoint....................................................................................329
Figure 9-3. wIndex Format when Specifying an Interface ....................................................................................329
Figure 9-4. Information Returned by a Standard GetStatus() Request to a Device...................................336
Figure 9-5. Information Returned by a Standard GetStatus() Request to an Interface ...........................336
Figure 9-6. Information Returned by a Standard GetStatus() Request to an Endpoint...........................337
Figure 9-7. Information Returned by a PTM GetStatus() Request to an Endpoint ....................................337
Figure 9-8. Example of Feedback Endpoint Relationships ...................................................................................362
Figure 10-1. USB Hub Architecture.................................................................................................................................367
Figure 10-2. SuperSpeed Portion of the USB Hub Architecture .........................................................................368
Figure 10-3. SuperSpeedPlus Portion of the Hub Architecture..........................................................................369
Figure 10-4. Simple USB Topology ..................................................................................................................................370
Figure 10-5 Route String Example .................................................................................................................................372
Figure 10-6. SuperSpeed Hub Signaling Connectivity ............................................................................................373
Figure 10-7. Resume Connectivity...................................................................................................................................374
Figure 10-8. Typical SuperSpeed Hub Header Packet Buffer Architecture...................................................375
Figure 10-9. SuperSpeed Hub Data Buffer Traffic (Header Packet Buffer Only Shown for DS Port 1)
.................................................................................................................................................................................................376
Figure 10-10. Downstream Facing Hub Port State Machine................................................................................378
Figure 10-11. Downstream Facing Hub Port Power Management State Machine.....................................387
Figure 10-12. Upstream Facing Hub Port State Machine ......................................................................................392
Figure 10-13. Hub Connect (HCONNECT) State Machine .....................................................................................394
Figure 10-14. Upstream Facing Hub Port Power Management State Machine ...........................................396
Figure 10-15. Example SS Hub Header Packet Buffer Architecture - Downstream Traffic....................401
Figure 10-16. Example SS Hub Header Packet Buffer Architecture - Upstream Traffic ..........................401
Figure 10-17. Logical Representation of Upstream Flowing Buffers ...............................................................403
Figure 10-18. Logical Representation of Downstream Flowing Buffers ........................................................404
Figure 10-19. Port Transmit State Machine ................................................................................................................409
Figure 10-20. Upstream Facing Port Rx State Machine..........................................................................................411
Figure 10-21. Example Hub Controller Organization .............................................................................................420
Revision 1.0 - xxvii - Universal Serial Bus 3.2
September 22, 2017 Specification
Copyright © 2017 USB 3.0 Promoter Group. All rights reserved.
Figure 10-22. Relationship of Status, Status Change, and Control Information to Device States........421
Figure 10-23. Port Status Handling Method................................................................................................................422
Figure 10-24. Hub and Port Status Change Bitmap .................................................................................................423
Figure 10-25. Example Hub and Port Change Bit Sampling.................................................................................423
Figure 10-26. Peripheral Upstream Device Port State Machine.........................................................................452
Figure 11-1. Compound Self-powered Hub.................................................................................................................460
Figure 11-2. Low-power Bus-powered Function......................................................................................................461
Figure 11-3. High-power Bus-powered Function.....................................................................................................461
Figure 11-4. Self-powered Function ...............................................................................................................................462
Figure 11-5. Worst-case System Equivalent Resistance........................................................................................463
Figure 11-6. Typical Suspend Current Averaging Profile......................................................................................464
Figure D-1. Sample ERDY Transaction Packet............................................................................................................481
Figure D-2. Sample Data Packet........................................................................................................................................481
Figure D-3. Example placement of Gen 2 SKP Block, Idle Symbols, Link Command and Header Packet
.................................................................................................................................................................................................482
Figure D-4. Example placement of Gen 2 Data Packets and Idle Symbols .....................................................483
Figure E-1. Link Segment Definition...............................................................................................................................485
Figure E-2. Example Link Configuration of a 3-µs Host with a 10-µs Device ...............................................486
Figure E-3. Example Link Configuration of a 10-µs Host with a 10-µs Device.............................................486
Figure E-4. Link Delay Budget in 3-re-timer Connectivity Model......................................................................487
Figure E-5. Example Re-timer Architectures ..............................................................................................................488
Figure E-6. Re-timer Training and Status State Machine ......................................................................................491
Figure E-7. Polling Substate Machine.............................................................................................................................494
Figure E-8. Illustration of Re-timer Presence Announcement............................................................................497
Figure E-9. Sequential Bit-Level Re-timer Clock Switching..................................................................................500
Figure E-10. Sequential Bit-Level Re-timer Clock Switching Based on TS1A OS and TS1B OS...........502
Figure E-11. Example of Four Bit-Level Re-timer Performing Sequential Clock Switching .................503
Figure E-12. Standalone Bit-Level Re-timer Compliance Test Setup...............................................................506
Figure E-13. Recovery Substate Machine .....................................................................................................................513
Figure E-14. Example Block Diagram of a Re-timer Operating in Gen 2 Mode............................................515
Figure E-15. Block Diagram for Example Bit-Level Re-timer Clocking Architecture................................516
Figure E-16. Jitter Transfer Illustration ........................................................................................................................517
Figure E-17. Jitter Transfer Reference Curves ...........................................................................................................518