STM32F7和 STM32H7 的完整编程指南

【实例简介】
编程手册为应用程序和系统级软件开发人员提供信息。它给一个完整的描述STM32F7系列和STM32H7系列皮层®m7处理器编程模型,指令集和核心外围设备
PM0253 Contents 2.5 Fault handling ,,,47 2.5.1 Fault types 2.5.2 Fault escalation and hard faults 48 2.5.3 Synchronous and Asynchronous bus faults 49 2.5.4 Fault status registers and fault address registers ..49 2.5.5 Lockup 49 2.6 Power management 50 2.6.1 Entering sleep mode ..50 2.6.2 Wakeup from sleep mode 5 2.6.3 The external event input 2.6.4 Power management programming hints The Cortex-M7 instruction set ,,,,,,,,,,,,.,52 3.1 Instruction set summary 52 3.1. 1 Binary compatibility with other Cortex processors 61 3.2 CMSIS functions 62 3.3 About the instruction descriptions 63 3.3.1 Operands .63 3.3.2 Restrictions when using PC or SP 63 3.3.3 Flexible second operand 64 3.3.4 Shift operations 3.3.5 Address alignment 68 3.3.6 PC-relative expressions 68 3.3.7 Conditional execution 68 3.3.8 nstruction width selection 3.4 Memory access instructions 72 3.4.1ADR 73 3.42 lDR and str immediate offset 3.4.3 LDR and STR, register offset 3.4.4 LDR and STR, unprivileged 3.4.5 LDR. PC-relative 78 3. 4. 6 LDM and stm .....79 3.4.7PLD 3.4.8 PUSH and Pop 82 3.4.9 LDREX and stREX .83 3.4.10 CLREX 84 Docl D028474 Rev 4 3/252 Contents PM025 3.5 General data processing instructions 85 3.5.1 ADD ADC, SUB SBC and rsB 3.5.2 AND. ORR. EOR BIC and ORN 89 3.5.3 ASR LSL LSRRoR and rrX 90 3.5.4 CLZ 91 3.5.5 CMP and cmn 92 3.5.6 MOV and mvn 93 3.5.7 MOVT 94 3.5.8 REV, REV16, REVSH, and rbIt 95 3.5.9 SADD16 and SADD ...96 3.5.10 SHADD16 and shadD8 ...97 3.5.11 SHASX and SHSAX .98 3.5.12 SHSUB16 and shsuB8 99 3.5.13 SSUB16 and ssuB8 100 3.5.14 SASX and SSAX ,,,.101 3.5. 15 TST and TEQ .102 3.5.16 UADD 16 and UADD8 103 3.5.17 UASX and USAX 104 3.5.18 UHADD16 and UHADD8 105 3.5.19 UHASX and UHSaX 106 3.5.20 UHSUB16 and UHSUB8 107 3.5.21SEL 108 3.5.22UsAD8 108 3.5.23 USADA8 ,,,.,109 3. 5.24 USUB16 and USUB8 3.6 Multiply and divide instructions 111 3.6.1 MUL MLA, and mls 112 3. 6.2 UMULL, UMAAL UMLAI 3.6.3 SMLA and SMAw ,,,,,,,,,,,,,,,,,115 3.6.4 SMLAD 116 3.6.5 SMLAL and smlald 117 3.6.6 SMLSD and smlsld 119 3.6.7 SMMLA and smmls 121 3.6.8 SMMUL 122 3.6.9 SMUAD and SMUSD 123 3. 6.10 SMUL and SMULW 124 3.6.11 UMULL. UMLAL, SMULL, and smal ..126 4/252 Docl D028474 Rev 4 / PM0253 Contents 3.6.12 SDIV and DIV 127 3.7 Saturating instructions ■■■ 128 3.71 SSAT and USat ....129 3. 7.2 SSAT16 and USAT16 130 3.7.3 QADD and QsUB 13 3.7.4 QASX and QSAX ...132 3.7.5 QDADD and QDSUB 133 3.7.6 UQASX and UQSAX 134 3.7.7 UQADD and UQSUB .,,,,,,,,,,,,,,,.136 3.8 Packing and unpacking instructions 137 3.8.1 PKHbt and PKhtb 138 3.8.2 SXT and UXT 139 3.8.3 SXTA and UXTA 140 3.9 Bit field instructions 14 3. 9.1 BFC and bfl 142 3.9.2 SBFX and UBFX 43 14 3.9.3 SXT and UXt 144 3. 10 Branch and control instructions 145 3.10.1 B BL BX and BlX 145 3.10.2 CBZ and cbnz 147 3.10.3|T 148 3.10.4 TBB and tbh 150 3.11 Floating-point instructions ,,,,15 3.11.1VABs,,.,,,,,,,,, 153 3.11.2 VADD ,,.153 3.11.3 VCMP VCMPE 154 3.11.4 VCVT, VCVTR between floating-point and integer 155 3.11.5 CvT between floating-point and fixed-point 3.11.6 VCVTB. VCVTT 157 3.11.7VDV 157 3.118 VEMA, VEMS ...,158 3.119 VENMA. VENMS 159 3.11.10VLDM ..159 3.11.11∨LDR ...,160 3.11.12 VMLA. VMLS 3.11.13 VMOV immediate 162 Docl D028474 Rev 4 5/252 Contents PM0253 3.11. 14 VMOV register ...162 3.11.15 VMOV scalar to Arm core register .163 3. 11.16 VMOV Arm core register to single-precision 163 3. 11.17 VMOV two Arm core registers to two single-precision registers 164 3.11.18 VMoV two Arm core registers and a double-precision register...164 3.11. 19 VMOV Arm core register to scalar .165 3.11.20∨MRS .,165 3.11.21VMsR 166 3.11.22VMUL 166 3.11.23∨NEG 3. 11.24 VNMLA VNMLS, VNMUL .,,..167 3.11.25VPOP .168 3.11.26 VPUSH,,,..,,,, ...169 3.11.27 VSQRT 169 3.11.28VsTM 170 3.11.29VsTR 170 3.11.30VSUB 171 3.11.31VSEL 172 3.11.32 VMAXNM VMINNM 172 3. 1133 VCVTA. VCVTN, VCVTP VCVTM 173 3.11.34∨R|NTR, VRINTX ....173 3.11.35 VRINTA. VRINTN, VRINTP VRINTM VRINTZ ,,,174 3.12 Miscellaneous instructions 175 3.12.1BKPT 175 3.12.2cPS ...176 3.12.3DMB 177 3.12.4DSB. 177 3.12.5|SB 178 3.12.6MRs 178 3.12.7MsR 179 3.128NOP ...180 3.129SEV 180 3.12.10SVC. 181 3.12.11WFE 181 3.12.12WF 182 Cortex-M7 peripherals 183 6/252 Docl D028474 Rev 4 / PM0253 Contents 4.1 About the Cortex-M7 peripherals 183 4.2 Nested Vectored Interrupt Controller 184 4.2.1 Accessing the Cortex-M7 NVIC registers using CMSIS 185 4.2.2 Interrupt set-enable registers 185 4.2.3 Interrupt clear-enable registers ..186 4.2.4 Interrupt set-pending registers 186 4.2.5 Interrupt clear-pending registers ..187 4.2.6 Interrupt active bit registers 188 4.2.7 Interrupt priority registers 188 4.2.8 Software trigger interrupt register 189 4.2. 9 Level-sensitive and pulse interrupts 190 4.2. 10 NVic design hints and tips 4.3 System control block 192 4.3. 1 Auxiliary control register 193 4.3.2 CPUid base register 194 4.3.3 Interrupt control and state register 194 4.3. 4 Vector table offset register 197 4.3.5 Application interrupt and reset control register ,,,,..197 4.3.6 System control register 4.3.7 Configuration and control register 200 4.3.8 System handler priority registers 202 4.3.9 System handler control and state register 204 4.3.10 Configurable fault status register 205 43.11 Hard Fault sta ter 210 4.3. 12 Mem Manage fault address register .,,,,211 4.3.13 BusFault address register .,,212 4.3. 14 System control block design hints and tips 212 4.4 System timer, SysTick 212 4.4.1 Sys Tick control and status register 213 4.4.2 Sys Tick reload value registe 214 4.4.3 Sys Tick current value register 214 4.4. 4 Sys Tick calibration value register 215 4.4.5 Sys Tick design hints and ti 216 4.5 Processor features 217 4.5.1 Cache level ID registe 217 4.5.2 Cache type register 218 Docl D028474 Rev 4 7/252 Contents PM0253 4.5.3 Cache size Id register 219 4.5.4 Cache size selection register 220 4.6 Memory protection unit 221 4.6. 1 MPU type register 223 4.6.2 MPU control register 223 4.6.3 MPU region number register 225 4.6.4 MPU region base address register 225 4.6.5 MPU region attribute and size register 226 4.6.6 MPU access permission attributes 228 4.6.7 MPU mismatch 4.6.8 Updating an MPU region .230 4.6.9 MPU design hints and tips 232 4.7 Floating-point unit 233 4.7.1 Coprocessor access control register .233 4.7.2 Floating-point context control register .234 4.7.3 Floating-point context address register .....236 4.7.4 Floating-point status control register ....236 4.7.5 Floating-point default status control register .,,237 4.7.6 Enabling the FPU 238 4.8 Cache maintenance operations 238 4.8.1 Full instruction cache operation 239 4.8.2 Instruction and data cache operations by address 239 4.8.3 Data cache operations by set-way 239 4.8.4 Cortex -M7 cache maintenance operations using cmsis .,.,240 4.8.5 Initializing and enabling the L1-cache 240 4.8.6 Faults handling considerations 242 4.8.7 Cache maintenance design hints and tips 242 49 Access control 243 4. 9. 1 Instruction and data tightly-coupled memory control registers ... 244 4.9.2 AHBP control register 246 4.9. 3 Auxiliary cache control register ..247 4.9.4 AHB slave control register ....248 4.9.5 Auxiliary bus fault status register 249 5 Revision history 251 8/252 Docl D028474 Rev 4 / PM0253 List of tables List of tables Table 1. Summary of processor mode, execution privilege level, and stack use options 20 Table 2. Core register set summary Table 3. PSR register combinations 22 Table 4. APSR bit assignments 23 Table 5. IPSR bit assignments 24 Table 6. EPSR bit assignments 24 Table 7. PRiMASK register bit assignments 26 Table 8. FAULTMASK register bit assignments 26 Table 9 BASEPRI register bit assignments 27 Table 10. Control register bit assignments Table 11. STM32F746xX/STM32F756xx Cortex -M7 configuration 30 Table 12. STM32F76xXX/STM32F77xxX Cortex -M7 configuration 30 Table 13. STM32F72XXX/STM32F73xXX Cortex-M7 configuration Table 14. STM32H7 Series Cortex -M7 configuration Table 15. Ordering of memory accesses .34 Table 16. Memory access behavior 34 share he poli 35 Table 18. Cmsis functions for exclusive access instructions 38 Table 19. Properties of the different exception types 40 Table 20. Exception return behavior .46 Table 21. faults Table 22. Fault status and fault address registers 49 Table 23. Cortex -M7 instructions 52 Table 24. CMSIS functions to generate some Cortex -M7 processor instructions 62 Table 25. CMSIS functions to access the special registers 63 Table 26, Condition code suffixes .70 Table 27. Memory access instructions Table 28. Offset ranges 75 Table 29. Offset ranges 78 Table 30. Data processing instructions. 85 Table 31. multiply and divide instructions 11 Table 32. Saturating instructions 128 Table 33. Packing and unpacking instructions 137 Table 34. Packing and unpacking instructions ,,,141 Table 35. Branch and control instructions 145 Table 36. Branch ranges 146 Table 37. Floating-point instructions 151 Table 38. Miscellaneous instructions 175 T able 39. Core peripheral register regions 18 Table 40. NViC register summary ..184 Table 41. CMsis access Nvic functions 185 Table 42. SeR bit assignments .,,.185 Table 43. ICER bit assignments 186 Table 44. ISPR bit assignments Table 45. ICPR bit assignments ..187 Table 46. lAbR bit assignments 188 Table 47. IPR bit assignments 189 Table 48. stir bit assignments 189 Docl D028474 Rev 4 9/252 List of tables PM0253 Table 49. Cmsis functions for nvic control T able 50. Summary of the system control block registers 192 Table 51. actor bit assignments .,.193 Table 52. CPUid bit assignments ...,,..,194 Table 53. ICSR bit assignments ...195 Table 54 TOR bit assignments .197 Table 55. AIRCR bit assignments 198 Table 56. Priority grouping 198 Table 5/. scr bit assignments 199 Table 58. Ccr bit assignments 20 Table 59. System fault handler priority fields 202 Table 60. SHPR 1 register bit assignments ...203 Table 61. SHPR2 register bit assignments 203 Table 62. SHPR3 register bit assignments 203 Table 63. SHCSR bit assignments 204 Table 64. MMFSr bit assignments 206 Table 65. BFSR bit assignments 208 Table 66. UFSR bit assignments .209 Table 67. HFSR bit assignments 211 Table 68. MMFaR bit assignments 211 Table 69. BFAR bit assignments 212 Table 70. CMsiS function for system control 212 Table 71 System timer registers summary 213 Table 72. Sys Tick sYsT Csr bit assignments Table 73. SYsT RVr bit assignments 214 Table 74. SYSt CVR bit assignments 215 Table 75. SYST CALIB bit assignments 215 Table 76. CMSIS functions for Sys Tick control Table 77 Identification space summary 217 Table 78. CIdr bit assignments :· Table 79. CtR bit assignments 218 Table 80. CCSidR bit assignments ..219 Table 81. CCSIDR encodings 220 Table 82. CSSELR bit assignments 220 Table 83. Memory attributes summary 221 Table 84. MPU registers summary 222 Table 85 YPE bit assignments 223 Table 86. MPU CTRL bit assignments 224 Table 87. MPU RNR bit assignments 国 225 Table 88. MPU RbaR bit assignments ..226 Table 89. MPu Rasr bit assignments 227 Table 90. EXample SIZE field values 228 Table 91. TEX, C, B, and s encoding 228 Table 92. Cache policy for memory attribute encoding 229 Table 93 AP encoding 229 Table 94. Cortex -M7 floating-point system registers 233 Table 95. Cpac bit assignments 234 Table 96. FPccr bit assignments 234 Table 97. FPCAR bit assignments Table 98. FPScR bit assignments 236 Table 99. FPDSCR bit assignments 237 Table 100. Cache maintenance space register summary .,238 10/252 Docl D028474 Rev 4 / 【实例截图】
【核心代码】