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JESD79-4.pdf

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  • 发布时间：2020-09-10
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  • 发 布 人：sakurazzz
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 相关标签： JESD79 JESD79-4
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1. Scope ......................................................................................................................................................................... 1
2. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 2
2.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................2
2.2 DDR4 SDRAM Ball Pitch........................................................................................................................................2
2.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................2
2.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 2
2.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................3
2.6 Pinout Description ..................................................................................................................................................5
2.7 DDR4 SDRAM Addressing.....................................................................................................................................7
3. Functional Description ...............................................................................................................................................8
3.1 Simplified State Diagram ....................................................................................................................................8
3.2 Basic Functionality..................................................................................................................................................9
3.3 RESET and Initialization Procedure .....................................................................................................................10
3.3.1 Power-up Initialization Sequence .............................................................................................................10
3.3.2 Reset Initialization with Stable Power ......................................................................................................11
3.4 Register Definition ................................................................................................................................................12
3.4.1 Programming the mode registers .............................................................................................................12
3.5 Mode Register ......................................................................................................................................................13
4. DDR4 SDRAM Command Description and Operation ............................................................................................. 24
4.1 Command Truth Table ..........................................................................................................................................24
4.2 CKE Truth Table ...................................................................................................................................................25
4.3 Burst Length, Type and Order ..............................................................................................................................26
4.3.1 BL8 Burst order with CRC Enabled .........................................................................................................26
4.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................27
4.4.1 DLL on/off switching procedure ...............................................................................................................27
4.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................27
4.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................28
4.5 DLL-off Mode........................................................................................................................................................29
4.6 Input Clock Frequency Change ............................................................................................................................30
4.7 Write Leveling.......................................................................................................................................................31
4.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................32
4.7.2 Procedure Description .............................................................................................................................33
4.7.3 Write Leveling Mode Exit .........................................................................................................................34
4.8 Temperature controlled Refresh modes ...............................................................................................................34
4.8.1 Normal temperature mode .......................................................................................................................34
4.8.2 Extended temperature mode ................................................................................................................... 34
4.9 Fine Granularity Refresh Mode ............................................................................................................................35
4.9.1 Mode Register and Command Truth Table ..............................................................................................35
4.9.2 tREFI and tRFC parameters ....................................................................................................................35
4.9.3 Changing Refresh Rate ...........................................................................................................................36
4.9.4 Usage with Temperature Controlled Refresh mode................................................................................. 36
4.9.5 Self Refresh entry and exit .......................................................................................................................37
4.10 Multi Purpose Register .......................................................................................................................................37
4.10.1 DQ Training with MPR ...........................................................................................................................37
4.10.2 MR3 definition ........................................................................................................................................37
4.10.3 MPR Reads............................................................................................................................................ 38
4.10.4 MPR Writes............................................................................................................................................ 40
4.10.5 MPR Read Data format ..........................................................................................................................43
4.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS.......................................................................................48
4.12 ZQ Calibration Commands .................................................................................................................................50
DDR4 SDRAM STANDARD
(From JEDEC Board Ballot JCB-12-40, formulated under the cognizance of the JC-42.3 Subcommittee on
-iDRAM Memories.)
Contents
JEDEC Standard No. 79-4
4.12.1 ZQ Calibration Description .................................................................................................................... 50
4.13 DQ Vref Training ................................................................................................................................................ 51
4.14 Per DRAM Addressability .................................................................................................................................. 56
4.15 CAL Mode (CS_n to Command Address Latency) ............................................................................................ 59
4.15.1 CAL Mode Description .......................................................................................................................... 59
4.16 CRC ................................................................................................................................................................... 61
4.16.1 CRC Polynomial and logic equation ...................................................................................................... 61
4.16.2 CRC data bit mapping for x8 devices .................................................................................................... 63
4.16.3 CRC data bit mapping for x4 devices.................................................................................................... 63
4.16.4 CRC data bit mapping for x16 devices.................................................................................................. 63
4.16.5 Write CRC for x4, x8 and x16 devices .................................................................................................. 64
4.16.6 CRC Error Handling .............................................................................................................................. 64
4.16.7 CRC Frame format with BC4 ................................................................................................................. 65
4.16.8 Simultaneous DM and CRC Functionality ............................................................................................. 68
4.17 Command Address Parity( CA Parity ) ............................................................................................................. 68
4.17.1 CA Parity Error Log Readout ................................................................................................................. 74
4.18 Control Gear Down Mode .................................................................................................................................. 74
4.19 DDR4 Key Core Timing...................................................................................................................................... 77
4.20 Programmable Preamble ................................................................................................................................... 80
4.20.1 Write Preamble ...................................................................................................................................... 80
4.20.2 Read Preamble ..................................................................................................................................... 81
4.20.3 Read Preamble Training ....................................................................................................................... 82
4.21 Postamble .......................................................................................................................................................... 82
4.21.1 Read Postamble.................................................................................................................................... 82
4.21.2 Write Postamble .................................................................................................................................... 82
4.22 ACTIVATE Command ........................................................................................................................................ 82
4.23 Precharge Command......................................................................................................................................... 83
4.24 Read Operation.................................................................................................................................................. 83
4.24.1 READ Timing Definitions ....................................................................................................................... 83
4.24.1.1 READ Timing; Clock to Data Strobe relationship .......................................................................... 85
4.24.1.2 READ Timing; Data Strobe to Data relationship ............................................................................ 86
4.24.1.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .................................................................... 87
4.24.1.4 tRPRE Calculation........................................................................................................................ 88
4.24.1.5 tRPST Calculation ........................................................................................................................ 89
4.24.2 READ Burst Operation .......................................................................................................................... 90
4.24.3 Burst Read Operation followed by a Precharge .................................................................................. 101
4.24.4 Burst Read Operation with Read DBI (Data Bus Inversion) ................................................................ 103
4.24.5 Burst Read Operation with Command/Address Parity ........................................................................ 104
4.24.6 Read to Write with Write CRC ............................................................................................................. 105
4.24.7 Read to Read with CS to CA Latency ................................................................................................. 106
4.25 Write Operation................................................................................................................................................ 107
4.25.1 Write Burst Operation .......................................................................................................................... 107
4.26 Refresh Command........................................................................................................................................... 123
4.27 Self refresh Operation...................................................................................................................................... 124
4.27.1 Low Power Auto Self Refresh ............................................................................................................. 126
4.28 Power down Mode ........................................................................................................................................... 127
4.28.1 Power-Down Entry and Exit ................................................................................................................ 127
4.28.2 Power-Down clarifications ................................................................................................................... 132
4.29 Maximum Power Saving Mode ........................................................................................................................ 132
4.29.1 Maximum power saving mode............................................................................................................. 132
4.29.2 Mode entry .......................................................................................................................................... 132
4.29.3 CKE transition during the mode .......................................................................................................... 133
4.29.4 Mode exit ............................................................................................................................................. 134
4.29.5 Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 134
4.30 Connectivity Test Mode.................................................................................................................................... 135
4.30.1 Introduction .......................................................................................................................................... 135
4.30.2 Pin Mapping ........................................................................................................................................ 135
4.30.3 Logic Equations ................................................................................................................................... 136
4.30.3.1 Min Term Equations .................................................................................................................... 136
-ii-
JEDEC Standard No. 79-4
4.30.3.2 Output equations for x16 devices ................................................................................................ 136
4.30.3.3 Output equations for x8 devices .................................................................................................. 136
4.30.3.4 Output equations for x4 devices .................................................................................................. 136
4.30.4 Timing Requirement ............................................................................................................................ 137
4.31 CLK to Read DQS timing parameters.............................................................................................................. 137
5. On-Die Termination ............................................................................................................................................... 139
5.1 ODT Mode Register and ODT State Table......................................................................................................... 139
5.2 Synchronous ODT Mode ................................................................................................................................... 141
5.2.1 ODT Latency and Posted ODT ............................................................................................................. 142
5.2.2 Timing Parameters ................................................................................................................................ 142
5.2.3 ODT during Reads: ............................................................................................................................... 143
5.3 Dynamic ODT .................................................................................................................................................... 144
5.3.1 Functional Description ........................................................................................................................... 144
5.3.2 ODT Timing Diagrams ........................................................................................................................... 145
5.4 Asynchronous ODT mode.................................................................................................................................. 146
5.5 ODT buffer disabled mode for Power down....................................................................................................... 147
5.6 ODT Timing Definitions ...................................................................................................................................... 148
5.6.1 Test Load for ODT Timings ................................................................................................................... 148
5.6.2 ODT Timing Definitions ......................................................................................................................... 148
6. Absolute Maximum Ratings ................................................................................................................................... 150
7. AC & DC Operating Conditions ............................................................................................................................. 151
7.1 AC and DC Input Measurement Levels: VREF Tolerances ............................................................................... 151
7.2 AC and DC Logic Input Levels for Differential Signals....................................................................................... 152
7.2.1 Differential signal definition ................................................................................................................... 152
7.2.2 Differential swing requirements for clock (CK_t - CK_c) ........................................................................ 152
7.2.3 Single-ended requirements for differential signals ................................................................................ 153
7.2.4 Address and Control Overshoot and Undershoot specifications ........................................................... 153
7.2.5 Clock Overshoot and Undershoot Specifications .................................................................................. 154
7.2.6 Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 154
7.3 Slew Rate Definitions for Differential Input Signals (CK) ................................................................................... 155
7.4 Differential Input Cross Point Voltage ................................................................................................................ 156
7.5 CMOS rail to rail Input Levels ............................................................................................................................ 158
7.5.1 CMOS rail to rail Input Levels for RESET_n .......................................................................................... 158
8. AC and DC output Measurement levels ................................................................................................................ 159
8.1 Output Driver DC Electrical Characteristics ....................................................................................................... 159
8.1.1 Alert_n output Drive Characteristic ........................................................................................................ 160
8.2 Single-ended AC & DC Output Levels ............................................................................................................... 161
8.3 Differential AC & DC Output Levels ................................................................................................................... 161
8.4 Single-ended Output Slew Rate......................................................................................................................... 161
8.5 Differential Output Slew Rate............................................................................................................................. 162
9. Speed Bin .............................................................................................................................................................. 163
9.0.1 Speed Bin Table Note ........................................................................................................................... 167
10. IDD and IDDQ Specification Parameters and Test conditions ........................................................................... 168
10.1 IDD, IPP and IDDQ Measurement Conditions ................................................................................................. 168
10.2 IDD Specifications............................................................................................................................................ 183
11. Input/Output Capacitance.................................................................................................................................... 185
12. Electrical Characteristics & AC Timing ................................................................................................................ 187
12.1 Reference Load for AC Timing and Output Slew Rate ................................................................................... 187
12.2 tREFI................................................................................................................................................................ 187
12.3 Timing Parameters by Speed Grade................................................................................................................ 188
12.4 The DQ input receiver compliance mask for voltage and timing is shown in the figure below......................... 198
12.5 DDR4 Function Matrix...................................................................................................................................... 20

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