minipack-ocp-specification.pdf

minipack-ocp-specification， facebook, OCP

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Facebook Minipack 128x 100GE Switch System Specification 

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4 Table of Content
1 Revision History .....................................................................................................................2
2 License ......................................................................................................................................3
3 Scope..........................................................................................................................................5
4 Table of Content .....................................................................................................................6
5 Table of Figures ................................................................................................................... 15
6 Table of Tables..................................................................................................................... 17
7 Introduction ......................................................................................................................... 19
7.1 System Overview....................................................................................................................... 19
7.2 Common Terms ......................................................................................................................... 20
7.3 Chassis ......................................................................................................................................... 21
8 System Components ........................................................................................................... 26
8.1 System Hardware Architecture............................................................................................. 27
8.2 Switch Main Board (SMB) ....................................................................................................... 28
8.2.1 Block Diagram of SMB................................................................................................................................ 28
8.2.2 SMB components.......................................................................................................................................... 29
8.2.3 SMB I2C Connections ................................................................................................................................. 30
8.2.4 TH3 Power / VR............................................................................................................................................ 32
8.3 PIM-16Q 16x 100G Port Interface Module......................................................................... 32
8.3.1 Block Diagram of PIM-16Q...................................................................................................................... 32
8.3.2 PIM-16Q QSFP28 Ports ............................................................................................................................. 34
8.3.3 PIM-16Q QSFP28 Control......................................................................................................................... 34
8.3.4 PIM-16Q I2C Diagram................................................................................................................................ 36
8.3.5 PIM-16Q SPI Architecture........................................................................................................................ 38
8.3.6 PIM-16Q MDIO Architecture .................................................................................................................. 39
8.4 PIM-4DD 4x 400G Port Interface Module........................................................................... 40
8.4.1 Block Diagram of PIM-4DD ..................................................................................................................... 40
8.4.2 PIM-4DD I2C Architecture....................................................................................................................... 42
8.4.3 PIM-4DD SPI Architecture....................................................................................................................... 44
8.4.4 PIM-4DD MDIO Architecture.................................................................................................................. 45
8.5 System Control Module ........................................................................................................... 46
8.5.1 System Control Module Block Diagram............................................................................................ 46
8.5.2 PCIe Bus............................................................................................................................................................. 48
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8.5.3 MDIO Control Bus ........................................................................................................................................ 49
8.5.4 SCM and SMB I2C Bus ................................................................................................................................ 49
8.5.5 SPI Bus of SCM ............................................................................................................................................... 51
8.5.6 SCM and SMB USB Architecture ........................................................................................................... 52
8.5.7 10G-KR Interface .......................................................................................................................................... 52
8.5.8 Hot Swap Design of SCM........................................................................................................................... 53
8.5.9 COM-Express CPU Module....................................................................................................................... 53
8.6 Fan Control Module (FCM) and Fan-tray............................................................................ 56
8.6.1 Fan Control...................................................................................................................................................... 57
8.6.2 I2C Architecture of FCM............................................................................................................................ 63
8.7 Power Distribution Boards (PDB)........................................................................................ 65
9 Functional Descriptions .................................................................................................... 66
9.1 Orthogonal Direct Architecture............................................................................................ 66
9.1.1 Direct Mated Orthogonal Connector .................................................................................................. 67
9.2 Data Plane................................................................................................................................... 68
9.2.1 Switch Element.............................................................................................................................................. 68
9.2.2 Port Mapping between SMB and PIM ................................................................................................ 69
9.2.2.1 General PIM Card Port Assignment.......................................................................................................70
9.2.2.2 PIM-16Q Port Mapping to SMB...............................................................................................................70
9.2.2.3 Port Mapping of PIM-4DD to SMB..........................................................................................................86
9.3 Control Plane.............................................................................................................................. 98
9.4 Chassis Management Plane..................................................................................................101
9.5 Power Plane..............................................................................................................................102
9.5.1 Power Distribution System...................................................................................................................104
9.5.2 PSU.....................................................................................................................................................................105
9.6 Thermal Design .......................................................................................................................109
9.6.1 Fan Tray ..........................................................................................................................................................109
9.6.2 Temperature Sensing and Fan Speed Control.............................................................................112
9.7 FRU and Module Numbering................................................................................................112
9.7.1 FRU Name.......................................................................................................................................................112
9.7.2 Slot ID for PIM and SCM..........................................................................................................................112
9.7.3 PIM Board ID ................................................................................................................................................113
9.8 System LED ...............................................................................................................................114
9.8.1 System Information LED (SIM LED).................................................................................................114
9.8.2 PIM LED...........................................................................................................................................................117
9.8.2.1 DOM FPGA Offset 0x80: STS_LED (Read & Write)......................................................................... 118
9.8.3 SCM LED..........................................................................................................................................................119
9.8.3.1 SCM CPLD Offset 0x08: SYS_LED (Read & Write).......................................................................... 119
9.8.3.2 SCM CPLD Offset 0x09 OOB_LED (Read& Write)........................................................................... 121
9.8.4 Fan-Tray LED................................................................................................................................................121
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9.8.4.1 FCM CPLD Offset 0x24, 0x34, 0x44, 0x54: FAN1/2/3/4_LED (Read & Write).................... 122
9.8.5 PSU LED...........................................................................................................................................................122
9.9 Port LED.....................................................................................................................................124
9.9.1.1 PIM#1 QSFP_LED Control Register..................................................................................................... 125
9.9.1.2 PIM#1 LED_COLOR_1_RG Color Profile Register ........................................................................... 125
9.9.1.3 PIM#1 LED_COLOR_1_B Color Profile Register .............................................................................. 126
9.9.1.4 PIM#1 P1_P2_LED.................................................................................................................................... 127
9.10 IOB FPGA ...................................................................................................................................128
9.10.1 Architecture ..................................................................................................................................................128
9.10.2 Major Modules .............................................................................................................................................129
9.10.2.1 PCIe Core ..................................................................................................................................................... 129
9.10.2.2 I2C Slave ...................................................................................................................................................... 130
9.10.2.3 Wishbone Mux........................................................................................................................................... 131
9.10.2.4 SLPC............................................................................................................................................................... 131
9.10.3 Interrupt.........................................................................................................................................................133
9.11 DOM FPGA.................................................................................................................................134
9.11.1 Architecture ..................................................................................................................................................134
9.11.2 Major Modules .............................................................................................................................................135
9.11.2.1 SLPC............................................................................................................................................................... 135
9.11.2.2 I2C Slave ...................................................................................................................................................... 137
9.11.2.3 Wishbone Mux........................................................................................................................................... 137
9.11.2.4 DOM Engine................................................................................................................................................ 137
9.11.2.5 I2C Master Core......................................................................................................................................... 143
9.11.2.6 Port LED Control....................................................................................................................................... 143
9.11.3 Interrupt.........................................................................................................................................................145
10 Programming Interfaces .............................................................................................146
10.1 SMB System CPLD Register Descriptions .........................................................................146
10.1.1 Offset 0x00: Board Info (Read Only)................................................................................................146
10.1.2 Offset 0x01: CPLD Version (Read Only).........................................................................................146
10.1.3 Offset 0x02: CPLD Sub version (Read)............................................................................................146
10.1.4 Offset 0x03: Power Module Status-L (Read Only).....................................................................146
10.1.5 Offset 0x04: Power Module Status-R (Read Only)....................................................................147
10.1.6 Offset 0x05: System Reset-1 (Read & Write)...............................................................................147
10.1.7 Offset 0x06 System Reset-2: (Read & Write)...............................................................................148
10.1.8 Offset 0x07: System Reset-3 (Read & Write)...............................................................................148
10.1.9 Offset 0x08: System Reset-4 (Read & Write)...............................................................................149
10.1.10 Offset 0x09: System Reset-5 (Read & Write)..........................................................................150
10.1.11 Offset 0x0A: System Reset-6 (Read & Write).........................................................................151
10.1.12 Offset 0x0B: System Reset-7 (Read & Write).........................................................................152
10.1.13 Offset 0x0C: System Reset-8 (Read Only).................................................................................152
10.1.14 Offset 0x0D: System Reset Lock / Unlock (Read & Write)(Reserved)......................152
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10.1.15 Offset 0x10: Interrupt Status-1 (Read Only)...........................................................................153
10.1.16 Offset 0x11: Interrupt Status-2 (Read Only)...........................................................................153
10.1.17 Offset 0x12: Interrupt Status-3 (Read Only)...........................................................................154
10.1.18 Offset 0x13: Interrupt Status-4 (Read Only)...........................................................................155
10.1.19 Offset 0x20: Interrupt Mask-1 (Read & Write)......................................................................155
10.1.20 Offset 0x21: Interrupt Mask-2 (Read & Write)......................................................................156
10.1.21 Offset 0x22: Interrupt Mask-3 (Read & Write)......................................................................157
10.1.22 Offset 0x23: Interrupt Mask-4 (Read & Write)......................................................................157
10.1.23 Offset 0x30: PIM FPGA Present Interrupt Status (Read Only).......................................158
10.1.24 Offset 0x31: PIM FPGA Present Interrupt Mask (Read& Write)...................................158
10.1.25 Offset 0x32: PIM FPGA Present Status (Read Only)............................................................159
10.1.26 Offset 0x33: SCM and FCM Present Interrupt Status (Read Only)...............................160
10.1.27 Offset 0x34: SCM and FCM Present Interrupt Mask (Read & Write)..........................160
10.1.28 Offset 0x35: SCM and FCM Present Status (Read Only)....................................................161
10.1.29 Offset 0x40: System BMC (Read & Write)................................................................................161
10.1.30 Offset 0x41: System MISC-1 (Read & Write)...........................................................................162
10.1.31 Offset 0x42: System MISC-2 (Read & Write)...........................................................................162
10.1.32 Offset 0x43: System Power (Read Only)...................................................................................162
10.1.33 Offset 0x44: System Power (Read & Only)..............................................................................162
10.1.34 Offset 0x45: System PCA9543 Power (Read & Write).......................................................163
10.1.35 Offset 0x46: System MAC ROV (Read Only)............................................................................163
10.1.36 Offset 0x47: System CP2112A GPIO (Read & Write)..........................................................164
10.1.37 Offset 0x48: System SPI MUX-1 (Read & Write)...................................................................164
10.1.38 Offset 0x49: System SPI MUX-2 (Read & Write)...................................................................164
10.1.39 Offset 0x4A: System Reserve-1 (Read Only)...........................................................................165
10.1.40 Offset 0x4B: System Misc-3 (Read Only)..................................................................................165
10.2 SCM CPLD Register Descriptions ........................................................................................165
10.2.1 Offset 0x00: Board Info (Read Only)................................................................................................165
10.2.2 Offset 0x01: CPLD Version (Read Only).........................................................................................166
10.2.3 Offset 0x02: CPLD Sub Version (Read Only)................................................................................166
10.2.4 Offset 0x08: LED_TEST (Read & Write)..........................................................................................166
10.2.5 Offset 0x09: SYSTEM_LED (Read & Write)...................................................................................167
10.2.6 Offset 0x0A: SYSTEM_LED (Read Only)..........................................................................................167
10.2.7 Offset 0x0C: Watch Dog (Read Only)...............................................................................................167
10.2.8 Offset 0x10: COMe_RST_CTRL (Read & Write)...........................................................................167
10.2.9 Offset 0x11: COMe_STA (Read Only)................................................................................................168
10.2.10 Offset 0x12: COMe_BIOS_DIS_CTRL (Read & Write)...........................................................168
10.2.11 Offset 0x14: COME_PWR_CTRL_REG (Read & Write)........................................................168
10.2.12 Offset 0x15: SPI_FLASH_SEL_CTRL (Read & Write)............................................................168
10.2.13 Offset 0x21: SYSTEM_INTERRUPT (Read Only)....................................................................169
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10.2.14 Offset 0x28: SYSTEM_INTERRUPT_MASK (Read & Write)..............................................169
10.2.15 Offset 0x30: SYSTEM_POWER_STATUS (Read Only)..........................................................169
10.2.16 Offset 0x31: SYSTEM_POWER_ENABLE (Read & Write)..................................................170
10.2.17 Offset 0x32: SYSTEM_ISO_1 (Read & Write)...........................................................................170
10.2.18 Offset 0x33: SYSTEM_ISO_2 (Read & Write)...........................................................................171
10.2.19 Offset 0x34: THERMAL2 (Read Only).........................................................................................171
10.2.20 Offset 0x35: SYSTEM_MISC_1 (Read & Write).......................................................................171
10.2.21 Offset 0x36: SYSTEM_MISC_2 (Read & Write).......................................................................171
10.2.22 Offset 0x37: SYSTEM_MISC_3 (Read Only)..............................................................................172
10.2.23 Offset 0x38: UART_SEL (Read Only)...........................................................................................172
10.2.24 Offset 0x39: SYSTEM_MISC_4 (Read Only)..............................................................................172
10.2.25 Offset 0x3A: SYSTEM_MISC_5 (Read Only)..............................................................................172
10.2.26 Offset 0x3B: SYSTEM_MISC_6 (Read Only)..............................................................................173
10.2.27 Offset 0x3C: SYSTEM_MISC_7 (Read / Write)........................................................................173
10.2.28 Offset 0x40: REPEATER_ENABLE (Read / Write)................................................................173
10.2.29 Offset 0x41: SFP_STATUS (Read Only)......................................................................................174
10.2.30 Offset 0x42: SFP_STATUS (Read / Write).................................................................................174
10.3 FCM CPLD Register Descriptions ........................................................................................174
10.3.1 Offset 0x00: BOARD_VERSION (Read Only).................................................................................174
10.3.2 Offset 0x01: CPLD Version (Read Only).........................................................................................174
10.3.3 Offset 0x02: CPLD_SUB_VERSION (Read Only)..........................................................................174
10.3.4 Offset 0x06: FAN_BLOCK_VERSION (Read Only).......................................................................175
10.3.5 Offset 0x07: TEMP_SENSOR (Read Only)......................................................................................175
10.3.6 Offset 0x08: FAN_INT_TRIG_MOD (Read & Write)...................................................................175
10.3.7 Offset 0x09: FAN_INT_RPT (Read Only).........................................................................................175
10.3.8 Offset 0x0A: BMC_WDT_TRIGGER (Read & Write)...................................................................176
10.3.9 Offset 0x0F: FCB_EEPROM_WP (Read & Write).........................................................................176
10.3.10 Offset 0x10: FAN_ENABLE_REG (Read & Write)..................................................................176
10.3.11 Offset 0x11: ADM1278 Alert Register (Read Only).............................................................176
10.3.12 Offset 0x12: ADM1278 Alert Register (Read & Write)......................................................177
10.3.13 Offset 0x11: ADM1278 Alert Register (Read Only).............................................................177
10.3.14 Offset 0x12: ADM1278 Alert Register_MASK (Read & Write).......................................178
10.3.15 Offset 0x20: FAN1_TACH_F_N (Read Only).............................................................................178
10.3.16 Offset 0x21: FAN1_TACH_B_N (Read Only).............................................................................178
10.3.17 Offset 0x22: FAN1_PWM (Read & Write).................................................................................178
10.3.18 Offset 0x24: FAN1_LED (Read & Write)....................................................................................179
10.3.19 Offset 0x25: FAN1_EEPROM_WP (Read & Write)................................................................179
10.3.20 Offset 0x28: FAN1_PRESENT (Read Only)...............................................................................179
10.3.21 Offset 0x29: FAN1_INT_MASK (Read & Write)......................................................................179
10.3.22 Offset 0x2A: FAN1_INT_STA (Read & Write)..........................................................................180
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10.4 PDB CPLD Register Descriptions ........................................................................................180
10.4.1 Offset 0x00: Board Info (Read Only)................................................................................................180
10.4.2 Offset 0x01: CPLD version (Read Only)..........................................................................................180
10.4.3 Offset 0x02: CPLD Sub Version (Read Only)................................................................................181
10.4.4 Offset 0x10: SYSTEM_MISC_1 (Read & Write)............................................................................181
10.4.5 Offset 0x11: SYSTEM_MISC_2 (Read Only)...................................................................................181
10.4.6 Offset 0x20: TIMER_BASE_SETTING (Read & Write)..............................................................181
10.4.7 Offset 0x21: TIMER_COUNTER_SETTING (Read & Write)....................................................181
10.4.8 Offset 0x22: TIMER_COUNTER_STATE (Read Only)................................................................181
10.4.9 Offset 0x23: TIMER_MISC (Read & Write)....................................................................................182
10.5 IOB FPGA Register Definition ..............................................................................................182
10.5.1 PCI Configuration Space Registers ....................................................................................................182
10.5.2 PCI register mapping................................................................................................................................183
10.5.3 General Registers .......................................................................................................................................184
10.5.3.1 Revision ....................................................................................................................................................... 184
10.5.3.2 Scratch_Pad................................................................................................................................................. 185
10.5.3.3 System_LED................................................................................................................................................ 185
10.5.3.4 Up_Time....................................................................................................................................................... 185
10.5.3.5 MSI_Debug................................................................................................................................................... 185
10.5.3.6 Latency_Debug........................................................................................................................................... 185
10.5.3.7 Logic Reset.................................................................................................................................................. 186
10.5.3.8 Thread Control Register......................................................................................................................... 186
10.5.3.9 Interrupt INTA Summary/MSI Interrupt Status ............................................................................ 186
10.5.4 IOB Specific Registers ..............................................................................................................................186
10.5.4.1 PIM Status ................................................................................................................................................... 186
10.5.4.2 PIM Present Interrupt Mask.................................................................................................................. 187
10.5.4.3 SLPC Parity Enable................................................................................................................................... 187
10.5.4.4 SLPC Parity Interrupt Status................................................................................................................. 187
10.5.4.5 SLPC Parity Error Count......................................................................................................................... 187
10.5.4.6 SLPC Timeout Error Count.................................................................................................................... 188
10.5.4.7 PCIE Debug Control.................................................................................................................................. 188
10.5.4.8 PCIE Error Counter 0............................................................................................................................... 188
10.5.4.9 PCIE Error Counter 1............................................................................................................................... 188
10.5.4.10 PCIE Access Counter........................................................................................................................... 188
10.5.4.11 PCIE Debug TLP Registers ................................................................................................................ 188
10.5.5 BMC Registers..............................................................................................................................................188
10.6 DOM FPGA Register Definition............................................................................................190
10.6.1 SLPC register mapping ............................................................................................................................190
10.6.2 General Registers .......................................................................................................................................193
10.6.2.1 Revision ....................................................................................................................................................... 193
10.6.2.2 Scratch_Pad................................................................................................................................................. 193
10.6.2.3 System_LED................................................................................................................................................ 193
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10.6.2.4 Up_Time....................................................................................................................................................... 194
10.6.2.5 MSI_Debug................................................................................................................................................... 194
10.6.2.6 Latency_Debug........................................................................................................................................... 194
10.6.2.7 Logic Reset.................................................................................................................................................. 194
10.6.2.8 Thread Control Register......................................................................................................................... 195
10.6.2.9 Interrupt INTA Summary/MSI Interrupt Status ............................................................................ 195
10.6.3 QSFP Management Registers ...............................................................................................................195
10.6.3.1 QSFP GPIO................................................................................................................................................... 195
10.6.3.2 DOM MAX Temperature ......................................................................................................................... 196
10.6.3.3 QSFP Present Register ............................................................................................................................ 196
10.6.3.4 QSFP Present Interrupt Register ......................................................................................................... 196
10.6.3.5 QSFP Present Interrupt Mask Register.............................................................................................. 196
10.6.3.6 QSFP Interrupt Register ......................................................................................................................... 196
10.6.3.7 QSFP Interrupt Mask Register.............................................................................................................. 196
10.6.3.8 QSFP Reset Register................................................................................................................................. 196
10.6.3.9 QSFP LPmode Register ........................................................................................................................... 197
10.6.4 DOM1 REG2...................................................................................................................................................197
10.6.4.1 SLPC Slave Parity...................................................................................................................................... 197
10.6.4.2 PHY FW Load Control/Status ............................................................................................................... 197
10.6.4.3 Device Interrupt Status........................................................................................................................... 197
10.6.4.4 Device Interrupt Mask ............................................................................................................................ 198
10.6.4.5 Device Power Bad Status........................................................................................................................ 198
10.6.4.6 Device Power Good Mask....................................................................................................................... 198
10.6.4.7 Device Power Control.............................................................................................................................. 199
10.6.4.8 Device Reset Control ............................................................................................................................... 199
10.6.4.9 PIM Status ................................................................................................................................................... 200
10.6.5 Logic Analyzer..............................................................................................................................................200
10.6.5.1 ILA Trigger Data Pattern and Mask 1................................................................................................. 200
10.6.5.2 ILA Trigger Data Pattern and Mask 2................................................................................................. 200
10.6.5.3 ILA Trigger Data Pattern and Mask 3................................................................................................. 200
10.6.5.4 ILA Trigger Data Pattern and Mask 4................................................................................................. 201
10.6.5.5 ILA Sieve Data Pattern ............................................................................................................................ 201
10.6.5.6 ILA Command Register........................................................................................................................... 201
10.6.5.7 ILA Status Register................................................................................................................................... 202
10.6.5.8 ILA Reset...................................................................................................................................................... 202
10.6.5.9 ILA RAM Data............................................................................................................................................. 202
10.6.6 MDIO Controller..........................................................................................................................................202
10.6.6.1 MDIO Configuration Register ............................................................................................................... 202
10.6.6.2 MDIO Command Register....................................................................................................................... 203
10.6.6.3 MDIO Write Data Register ..................................................................................................................... 203
10.6.6.4 MDIO Read Data Register....................................................................................................................... 203
10.6.6.5 MDIO Status Register .............................................................................................................................. 203
10.6.6.6 MDIO Interrupt Mask .............................................................................................................................. 204
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10.6.7 Port LED Control Register .....................................................................................................................204
10.6.7.1 Color Profile 0_1........................................................................................................................................ 204
10.6.7.2 Color Profile 2_3........................................................................................................................................ 204
10.6.7.3 Color Profile 4_5........................................................................................................................................ 205
10.6.7.4 Color Profile 6_7........................................................................................................................................ 205
10.6.7.5 Port LED control ....................................................................................................................................... 205
10.6.8 QSFP I2C Controller ..................................................................................................................................206
10.6.8.1 DOM Registers ........................................................................................................................................... 206
10.6.8.2 QSFP Real Time Access Registers........................................................................................................ 213
10.6.8.3 I2C RTC Data Block .................................................................................................................................. 215
10.6.9 DOM Data Block ..........................................................................................................................................216
10.6.10 BMC Registers.........................................................................................................................................219
11 Optics Transceivers Supported.................................................................................221
11.1 100G optics ...............................................................................................................................221
11.2 200G optics ...............................................................................................................................221
11.3 400G optics ...............................................................................................................................221
11.4 40G optics..................................................................................................................................221
12 Host CPU and BMC Functional Features..................................................................222
12.1 COM-Express CPU BIOS Feature List..................................................................................222
12.2 BMC Feature Support.............................................................................................................224
13 Mechanical Architecture .............................................................................................225
13.1 Chassis .......................................................................................................................................225
14 Regulatory Compliance, Environmental, and Reliability Requirements.......229
14.1 Regulatory Compliance Requirements .............................................................................229
14.2 Materials of Concern Requirements..................................................................................232
14.3 Environmental Requirements.............................................................................................234
14.4 Mean Time Between Failures (MTBF) Requirements ..................................................234
15 Labels and Markings.....................................................................................................235
15.1 PCBA Labels and Markings...................................................................................................235
15.2 Chassis Labels and Markings ...............................................................................................235
16 Appendix A: Facebook Panel Indicator Specification (For Information Only)
236
1 License (OWFa 1.0)...........................................................................................................238
Table of Contents ......................................................................................................................240
4.1 Indicator Colors 251..................................................................................................................................... 240
4.2 Indicator Intensity 251................................................................................................................................ 240
4.3 Indicator Behaviors 252.............................................................................................................................. 240
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4.4 Indicator Placement 252............................................................................................................................. 240
4.5 Indicator Nomenclature 253...................................................................................................................... 240
6.1 System Power Control/Status 256 .......................................................................................................... 240
6.2 System General Status 257......................................................................................................................... 240
6.3 Generic Module/Compute Node Status 257......................................................................................... 240
6.4 PSU Status 258................................................................................................................................................ 240
6.5 BBU Status 260............................................................................................................................................... 240
6.6 QSFP Module Status 260 ............................................................................................................................. 240
6.7 HDD 261............................................................................................................................................................ 240
6.8 Fan Module 261.............................................................................................................................................. 240
7.1 Equipment 263............................................................................................................................................... 240
7.2 Procedure 263 ................................................................................................................................................ 240
2 Introduction .........................................................................................................................241
3 Guiding Principles ...............................................................................................................242
4 General Rules .......................................................................................................................243
4.1 Indicator Colors.......................................................................................................................243
4.2 Indicator Intensity..................................................................................................................243
4.3 Indicator Behaviors ..................................................................................................................244
4.4 Indicator Placement...............................................................................................................244
4.5 Indicator Nomenclature ...........................................................................................................245
5 Permitted Indicator States .................................................................................................247
6 Indicator States as Applied to Specific Hardware ..........................................................248
6.1 System Power Control/Status.................................................................................................248
6.2 System General Status ..............................................................................................................249
6.3 Generic Module/Compute Node Status .................................................................................249
6.4 PSU Status...................................................................................................................................250
6.5 BBU Status..................................................................................................................................252
6.6 QSFP Module Status ..................................................................................................................252
6.7 HDD.............................................................................................................................................253
6.8 Fan Module ...............................................................................................................................253
7 LED Brightness and Wavelength Test Procedure...........................................................255
7.1 Equipment..................................................................................................................................255
7.2 Procedure ...................................................................................................................................255