s32v234 datesheet(S32V234RM.pdf)

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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 121
1.2 Organization..................................................................................................................................................................121
1.2.1 Attachments................................................................................................................................................. 121
1.3 Module descriptions......................................................................................................................................................121
1.3.1 Example: chip-specific information that clarifies content in the same chapter........................................... 122
1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 123
1.4 Register descriptions.....................................................................................................................................................124
1.5 Conventions.................................................................................................................................................................. 125
1.5.1 Notes, Cautions, and Warnings....................................................................................................................125
1.5.2 Numbering systems......................................................................................................................................125
1.5.3 Typographic notation................................................................................................................................... 126
1.5.4 Special terms................................................................................................................................................ 126
Chapter 2
Introduction
2.1 Introduction...................................................................................................................................................................129
2.1.1 Target applications.......................................................................................................................................130
2.1.2 Block diagram.............................................................................................................................................. 130
2.1.3 Device Configuration...................................................................................................................................130
2.1.4 Feature Set....................................................................................................................................................134
Chapter 3
Embedded Memory Overview
3.1 Memory structure..........................................................................................................................................................137
3.2 Attached peripheral memory map.................................................................................................................................139
3.3 VSEQ memory map......................................................................................................................................................139
3.4 Validation of error correction/detection........................................................................................................................139
Chapter 4
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Memory Map
4.1 Peripheral Memory Map...............................................................................................................................................141
4.2 Private Peripheral Bus (PPB) memory map..................................................................................................................141
4.3 Interrupt Map................................................................................................................................................................ 142
Chapter 5
Signal Description
5.1 Signal Description.........................................................................................................................................................145
5.1.1 Miscellaneous Pins.......................................................................................................................................145
5.1.2 I/O Behavior During Reset.......................................................................................................................... 146
5.2 RESET pin behaviour during selftest........................................................................................................................... 146
Chapter 6
ARM Modules
6.1 Glossary........................................................................................................................................................................ 147
6.2 Platform components.................................................................................................................................................... 147
6.3 Cortex-A53 cluster complex.........................................................................................................................................149
6.3.1 ARM Cortex-A53 MPCore..........................................................................................................................150
6.3.2 ARM Generic Interrupt Controller (GIC-400).............................................................................................152
6.3.3 ARM CoreLink CCI-400 Cache Coherent Interconnect..............................................................................154
6.4 Cortex-M4 processor.................................................................................................................................................... 156
6.5 CoreLink Network Interconnect NIC-301....................................................................................................................156
6.6 Extended Resource Domain Controller (XRDC)......................................................................................................... 157
6.7 Operational Details....................................................................................................................................................... 157
6.7.1 Cluster reset..................................................................................................................................................157
6.7.2 Cluster clock gating..................................................................................................................................... 157
Chapter 7
Enhanced Direct Memory Access (eDMA)
7.1 Chip specific eDMA information................................................................................................................................. 159
7.2 Introduction...................................................................................................................................................................159
7.2.1 eDMA system block diagram...................................................................................................................... 159
7.2.2 Block parts................................................................................................................................................... 160
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7.2.3 Features........................................................................................................................................................ 161
7.3 Modes of operation....................................................................................................................................................... 162
7.4 Memory map/register definition................................................................................................................................... 163
7.4.1 TCD memory............................................................................................................................................... 163
7.4.2 TCD initialization........................................................................................................................................ 163
7.4.3 TCD structure...............................................................................................................................................163
7.4.4 Reserved memory and bit fields...................................................................................................................164
7.4.5 Control Register (DMA_CR).......................................................................................................................186
7.4.6 Error Status Register (DMA_ES)................................................................................................................ 189
7.4.7 Enable Request Register (DMA_ERQ)....................................................................................................... 192
7.4.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................195
7.4.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 199
7.4.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 200
7.4.11 Clear Enable Request Register (DMA_CERQ)........................................................................................... 200
7.4.12 Set Enable Request Register (DMA_SERQ)............................................................................................... 201
7.4.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 202
7.4.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 203
7.4.15 Clear Error Register (DMA_CERR)............................................................................................................204
7.4.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 205
7.4.17 Interrupt Request Register (DMA_INT)......................................................................................................206
7.4.18 Error Register (DMA_ERR)........................................................................................................................ 209
7.4.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 213
7.4.20 General-Purpose Output Register (DMA_GPORn).....................................................................................219
7.4.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 220
7.4.22 Channel n Master ID Register (DMA_DCHMIDn).................................................................................... 221
7.4.23 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................222
7.4.24 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................222
7.4.25 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................222
7.4.26 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 223
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7.4.27 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 224
7.4.28 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 225
7.4.29 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................226
7.4.30 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................227
7.4.31 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................227
7.4.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................228
7.4.33 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 229
7.4.34 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 230
7.4.35 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 230
7.4.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................233
7.4.37 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 234
7.5 Functional description...................................................................................................................................................234
7.5.1 eDMA basic data flow................................................................................................................................. 235
7.5.2 Fault reporting and handling........................................................................................................................ 237
7.5.3 Channel preemption..................................................................................................................................... 240
7.6 Initialization/application information........................................................................................................................... 240
7.6.1 eDMA initialization..................................................................................................................................... 240
7.6.2 Programming errors..................................................................................................................................... 243
7.6.3 Arbitration mode considerations..................................................................................................................244
7.6.4 Performing DMA transfers.......................................................................................................................... 245
7.6.5 Monitoring transfer descriptor status........................................................................................................... 249
7.6.6 Channel Linking...........................................................................................................................................251
7.6.7 Dynamic programming................................................................................................................................ 252
7.6.8 Suspend/resume a DMA channel with active hardware service requests....................................................255
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Chapter 8
Direct Memory Access Multiplexer (DMAMUX)
8.1 Chip specific DMAMUX information..........................................................................................................................257
8.1.1 DMAMUX instantiation information.......................................................................................................... 257
8.1.2 DMA Request Source Slot Mapping........................................................................................................... 257
8.1.3 DMAMUX Trigger Channel Assignment....................................................................................................259
8.2 Introduction...................................................................................................................................................................260
8.2.1 Overview......................................................................................................................................................260
8.2.2 Features........................................................................................................................................................ 261
8.2.3 Modes of operation...................................................................................................................................... 261
8.3 External signal description............................................................................................................................................261
8.4 Memory map/register definition................................................................................................................................... 262
8.4.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 262
8.5 Functional description...................................................................................................................................................263
8.5.1 DMA channels with periodic triggering capability......................................................................................263
8.5.2 DMA channels with no triggering capability...............................................................................................266
8.5.3 Always-enabled DMA sources.................................................................................................................... 266
8.6 Initialization/application information........................................................................................................................... 266
8.6.1 Reset.............................................................................................................................................................266
8.6.2 Enabling and configuring sources................................................................................................................267
Chapter 9
NIC301
9.1 CoreLink Network Interconnect NIC-301....................................................................................................................271
9.2 Overview.......................................................................................................................................................................271
9.3 Features.........................................................................................................................................................................271
9.4 NIC301 Physical Structure and Programming Model.................................................................................................. 272
9.4.1 NIC301 Physical Structure...........................................................................................................................272
9.4.2 NIC301 Programming Model...................................................................................................................... 275
9.4.3 NIC-301 register summary...........................................................................................................................276
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9.4.4 NIC301 Special Software Setup Requirements........................................................................................... 314
9.4.5 NIC301 Bus Arbitration...............................................................................................................................314
Chapter 10
Crossbar Switch (AXBS)
10.1 Chip specific AXBS information..................................................................................................................................317
10.1.1 AXBS configuration.................................................................................................................................... 317
10.1.2 XBAR master assignments.......................................................................................................................... 319
10.1.3 XBAR slave assignments.............................................................................................................................319
10.1.4 AXBS Connectivity .................................................................................................................................... 320
10.1.5 Unimplemented PRSn and CRSn registers..................................................................................................320
10.2 Introduction...................................................................................................................................................................320
10.2.1 Features........................................................................................................................................................ 321
10.3 Memory Map / Register Definition...............................................................................................................................321
10.3.1 Priority Registers Slave (AXBS_PRSn)...................................................................................................... 323
10.3.2 Control Register (AXBS_CRSn)................................................................................................................. 326
10.3.3 Master General Purpose Control Register (AXBS_MGPCRn)................................................................... 328
10.4 Functional Description..................................................................................................................................................329
10.4.1 General operation.........................................................................................................................................329
10.4.2 Register coherency.......................................................................................................................................330
Chapter 11
Extended Resource Domain Controller (XRDC)
11.1 Chip specific XRDC information................................................................................................................................. 331
11.1.1 XRDC memory map.................................................................................................................................... 331
11.1.2 Register configuration..................................................................................................................................358
11.2 Introduction...................................................................................................................................................................360
11.2.1 Features........................................................................................................................................................ 361
11.2.2 Block diagram.............................................................................................................................................. 362
11.2.3 Modes of operation...................................................................................................................................... 363
11.3 External signal description............................................................................................................................................364
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11.4 Register definition.........................................................................................................................................................364
11.4.1 Control Register (XRDC_CR)..................................................................................................................... 365
11.4.2 Hardware Configuration Register 0 (XRDC_HWCFG0)............................................................................367
11.4.3 Hardware Configuration Register 1 (XRDC_HWCFG1)............................................................................368
11.4.4 Hardware Configuration Register 2 (XRDC_HWCFG2)............................................................................368
11.4.5 Master Domain Assignment Configuration Register (XRDC_MDACFGn)...............................................373
11.4.6 Memory Region Configuration Register (XRDC_MRCFGn).....................................................................374
11.4.7 Domain Error Location Register (XRDC_DERRLOCn)............................................................................ 375
11.4.8 Domain Error Word0 Register (XRDC_DERR_W0_n)..............................................................................376
11.4.9 Domain Error Word1 Register (XRDC_DERR_W1_n)..............................................................................377
11.4.10 Domain Error Word2 Register (XRDC_DERR_W2_n)..............................................................................378
11.4.11 Domain Error Word3 Register (XRDC_DERR_W3_n)..............................................................................379
11.4.12 Process Identifier (XRDC_PIDn)................................................................................................................ 379
11.4.13 Master Domain Assignment Wm,n (DFMT=0) (XRDC_MDA_Wm_n)....................................................382
11.4.14 Master Domain Assignment Wm,n (DFMT=1) (XRDC_MDA_Wm_n)....................................................385
11.4.15 Peripheral Domain Access Control W0 (XRDC_PDAC_W0_n)................................................................387
11.4.16 Peripheral Domain Access Control W1 (XRDC_PDAC_W1_n)................................................................389
11.4.17 Memory Region Descriptor W0 (XRDC_MRGD_W0_n).......................................................................... 389
11.4.18 Memory Region Descriptor W1 (XRDC_MRGD_W1_n).......................................................................... 391
11.4.19 Memory Region Descriptor W2 (XRDC_MRGD_W2_n).......................................................................... 391
11.4.20 Memory Region Descriptor W3 (XRDC_MRGD_W3_n).......................................................................... 393
11.4.21 S32V234 specific MRC instance for SRAM controller memory protection............................................... 393
11.5 Functional description...................................................................................................................................................398
11.5.1 Manager (XRDC_MGR)..............................................................................................................................398
11.5.2 Master Domain Assignment Controller (XRDC_MDAC).......................................................................... 399
11.5.3 DxACP evaluation....................................................................................................................................... 400
11.5.4 Hardware semaphores and dynamic access rights....................................................................................... 401
11.5.5 Memory Region Controller (XRDC_MRC)................................................................................................ 402
11.5.6 Peripheral Access Controller (XRDC_PAC)...............................................................................................406
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11.6 Initialization information.............................................................................................................................................. 408
11.7 Application information................................................................................................................................................409
11.7.1 Master domain assignments......................................................................................................................... 409
11.7.2 Cache coherency interconnect (CCI)........................................................................................................... 410
11.7.3 Memory region descriptor management...................................................................................................... 412
11.7.4 Domain error capture management..............................................................................................................413
Chapter 12
Semaphores2 (SEMA42)
12.1 Introduction...................................................................................................................................................................415
12.1.1 Features........................................................................................................................................................ 415
12.2 Memory map/register definition................................................................................................................................... 417
12.2.1 Gate Register (SEMA42_GATEn).............................................................................................................. 418
12.2.2 Reset Gate Write (SEMA42_RSTGT_W)...................................................................................................419
12.2.3 Reset Gate Read (SEMA42_RSTGT_R).....................................................................................................421
12.3 Functional description...................................................................................................................................................421
Chapter 13
Local Memory (LMEM) Controller
13.1 Introduction...................................................................................................................................................................425
13.1.1 Block diagram.............................................................................................................................................. 425
13.1.2 Cache features.............................................................................................................................................. 427
13.2 Memory map/register definition................................................................................................................................... 428
13.2.1 Processor Code Cache Control Register (LMEM_PCCCR)........................................................................429
13.2.2 Processor Code Cache Line Control Register (LMEM_PCCLCR).............................................................430
13.2.3 Processor Code Cache Search Address Register (LMEM_PCCSAR)........................................................ 433
13.2.4 Processor Code Cache Read/Write Value Register (LMEM_PCCCVR)....................................................434
13.2.5 Processor System Cache Control Register (LMEM_PSCCR).....................................................................434
13.2.6 Processor System Cache Line Control Register (LMEM_PSCLCR)..........................................................436
13.2.7 Processor System Cache Search Address Register (LMEM_PSCSAR)..................................................... 438
13.2.8 Processor System Cache Read/Write Value Register (LMEM_PSCCVR)................................................. 439
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13.3 Functional description...................................................................................................................................................439
13.3.1 LMEM function........................................................................................................................................... 439
13.3.2 SRAM function............................................................................................................................................ 440
13.3.3 Cache function............................................................................................................................................. 442
13.3.4 Cache control............................................................................................................................................... 442
Chapter 14
Error Reporting Module (ERM)
14.1 Chip-specific ERM information................................................................................................................................... 447
14.1.1 ERM memory channels................................................................................................................................447
14.1.2 Memory error event sources and captured information............................................................................... 447
14.2 Introduction...................................................................................................................................................................448
14.2.1 Overview......................................................................................................................................................448
14.2.2 Features........................................................................................................................................................ 448
14.3 Memory map and register definition.............................................................................................................................449
14.3.1 ERM Configuration Register (ERM_CR)....................................................................................................450
14.3.2 ERM Status Register (ERM_SR).................................................................................................................453
14.3.3 ERM Memory n Error Address Register (ERM_EARn)............................................................................. 456
14.3.4 ERM Memory n Syndrome Register (ERM_SYNn)................................................................................... 457
14.4 Functional description...................................................................................................................................................457
14.4.1 Single-bit correction events......................................................................................................................... 457
14.4.2 Non-correctable error events........................................................................................................................458
14.5 Initialization.................................................................................................................................................................. 459
Chapter 15
Error Injection Module (EIM)
15.1 Chip-specific EIM information.....................................................................................................................................461
15.1.1 EIM channels............................................................................................................................................... 461
15.1.2 EIM channel assignments............................................................................................................................ 461
15.1.3 EIM_EICHDn_WORD register bit mapping...............................................................................................462
15.2 Introduction...................................................................................................................................................................464
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15.2.1 Overview......................................................................................................................................................464
15.2.2 Features........................................................................................................................................................ 465
15.3 Memory map and register definition.............................................................................................................................466
15.3.1 Error Injection Module Configuration Register (EIM_EIMCR)................................................................. 469
15.3.2 Error Injection Channel Enable register (EIM_EICHEN)...........................................................................469
15.3.3 Error Injection Channel Descriptor, Word0 (EIM_EICHDn_WORD0)..................................................... 473
15.3.4 Error Injection Channel Descriptor, Word1 (EIM_EICHDn_WORD1)..................................................... 474
15.3.5 Error Injection Channel Descriptor, Word2 (EIM_EICHDn_WORD2)..................................................... 475
15.4 Functional description...................................................................................................................................................475
15.4.1 Error injection scenarios.............................................................................................................................. 476
Chapter 16
Interrupt Monitor (INTM)
16.1 Introduction...................................................................................................................................................................477
16.2 Block diagram...............................................................................................................................................................478
16.3 Features.........................................................................................................................................................................478
16.4 INTM Register Descriptions.........................................................................................................................................479
16.4.1 INTM Memory Map.................................................................................................................................... 479
16.4.2 Monitor Mode (INTM_MM)....................................................................................................................... 479
16.4.3 Interrupt Acknowledge (INTM_IACK).......................................................................................................480
16.4.4 Interrupt Request Select a (INTM_IRQSELa).............................................................................................481
16.4.5 Latency a (INTM_LATENCYa)..................................................................................................................482
16.4.6 Timer a (INTM_TIMERa)........................................................................................................................... 483
16.4.7 Status a (INTM_STATUSa)........................................................................................................................ 485
16.5 Functional description...................................................................................................................................................486
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................489
17.1.1 Features........................................................................................................................................................ 489
17.2 Memory map/register descriptions............................................................................................................................... 489
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17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................490
17.2.2 Control Register (MCM_CR)...................................................................................................................... 491
17.2.3 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 492
17.2.4 Fault address register (MCM_FADR)......................................................................................................... 495
17.2.5 Fault attributes register (MCM_FATR).......................................................................................................496
17.2.6 Fault data register (MCM_FDR)..................................................................................................................497
Chapter 18
Miscellaneous System Control Module (MSCM)
18.1 Introduction...................................................................................................................................................................499
18.2 Memory map and register definition.............................................................................................................................499
18.2.1 CPU configuration registers.........................................................................................................................499
18.2.2 On-chip memory (OCMEM) configuration registers.................................................................................. 500
18.2.3 Interrupt router configuration registers........................................................................................................ 500
18.2.4 Burst optimization control register.............................................................................................................. 501
18.2.5 Processor x Type Register (MSCM_CPXTYPE)........................................................................................ 511
18.2.6 Processor x Number Register (MSCM_CPXNUM)....................................................................................512
18.2.7 Processor x Master Number Register (MSCM_CPXMASTER).................................................................513
18.2.8 Processor x Count Register (MSCM_CPXCOUNT)...................................................................................513
18.2.9 Processor x Configuration 0 Register (MSCM_CPXCFG0)....................................................................... 514
18.2.10 Processor x Configuration 1 Register (MSCM_CPXCFG1)....................................................................... 516
18.2.11 Processor x Configuration 2 Register (MSCM_CPXCFG2)....................................................................... 517
18.2.12 Processor x Configuration 3 Register (MSCM_CPXCFG3)....................................................................... 519
18.2.13 Processor 0 Type Register (MSCM_CP0TYPE)......................................................................................... 520
18.2.14 Processor 0 Number Register (MSCM_CP0NUM).....................................................................................521
18.2.15 Processor 0 Master Number Register (MSCM_CP0MASTER)..................................................................522
18.2.16 Processor 0 Count Register (MSCM_CP0COUNT)....................................................................................523
18.2.17 Processor 0 Configuration 0 Register (MSCM_CP0CFG0)........................................................................ 524
18.2.18 Processor 0 Configuration 1 Register (MSCM_CP0CFG1)........................................................................ 525
18.2.19 Processor 0 Configuration 2 Register (MSCM_CP0CFG2)........................................................................ 526
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18.2.20 Processor 0 Configuration 3 Register (MSCM_CP0CFG3)........................................................................ 528
18.2.21 Processor 1 Type Register (MSCM_CP1TYPE)......................................................................................... 530
18.2.22 Processor 1 Number Register (MSCM_CP1NUM).....................................................................................530
18.2.23 Processor 1 Master Number Register (MSCM_CP1MASTER)..................................................................531
18.2.24 Processor 1 Count Register (MSCM_CP1COUNT)....................................................................................532
18.2.25 Processor 1 Configuration 0 Register (MSCM_CP1CFG0)........................................................................ 533
18.2.26 Processor 1 Configuration 1 Register (MSCM_CP1CFG1)........................................................................ 534
18.2.27 Processor 1 Configuration 2 Register (MSCM_CP1CFG2)........................................................................ 535
18.2.28 Processor 1 Configuration 3 Register (MSCM_CP1CFG3)........................................................................ 537
18.2.29 On-Chip Memory Descriptor Register (MSCM_OCMDRn)...................................................................... 539
18.2.30 Generic Tightly Coupled Memory Descriptor Register (MSCM_TCMDR0).............................................544
18.2.31 Core Parity Checking Enable Register 0 (MSCM_CPCE0)........................................................................546
18.2.32 Interrupt Router CP0 Interrupt Register (MSCM_IRCP0IR)...................................................................... 547
18.2.33 Interrupt Router CP1 Interrupt Register (MSCM_IRCP1IR)...................................................................... 549
18.2.34 Interrupt Router CPU Generate Interrupt Register (MSCM_IRCPGIR).....................................................550
18.2.35 Interrupt Router Shared Peripheral Routing Control Register (MSCM_IRSPRCn)................................... 551
18.2.36 Interconnect Parity Checking Global Enable Register (MSCM_IPCGE)................................................... 552
18.2.37 Interconnect Parity Checking Enable Register 0 (MSCM_IPCE0)............................................................. 553
18.2.38 Interconnect Parity Checking Enable Register 1 (MSCM_IPCE1)............................................................. 557
18.2.39 Interconnect Parity Checking Enable Register 2 (MSCM_IPCE2)............................................................. 561
18.2.40 Interconnect Parity Checking Enable Register 3 (MSCM_IPCE3)............................................................. 564
18.2.41 Interconnect Parity Checking Global Injection Enable Register (MSCM_IPCGIE)...................................567
18.2.42 Interconnect Parity Checking Injection Enable Register 0 (MSCM_IPCIE0)............................................ 568
18.2.43 Interconnect Parity Checking Injection Enable Register 1 (MSCM_IPCIE1)............................................ 573
18.2.44 Interconnect Parity Checking Injection Enable Register 2 (MSCM_IPCIE2)............................................ 577
18.2.45 Interconnect Parity Checking Injection Enable Register 3 (MSCM_IPCIE3)............................................ 580
18.3 Chip configuration and boot......................................................................................................................................... 583
18.4 Interrupt steering and semaphores................................................................................................................................ 584
18.4.1 Interrupt handling overview.........................................................................................................................584
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18.4.2 MSCM interrupt router functional description............................................................................................ 585
Chapter 19
Crossbar Integrity Checker (XBIC)
19.1 Overview.......................................................................................................................................................................589
19.2 Features.........................................................................................................................................................................589
19.3 Block diagram...............................................................................................................................................................589
19.4 External signal description............................................................................................................................................590
19.5 Memory map and register definition.............................................................................................................................590
19.5.1 XBIC Module Control Register (XBIC_MCR)........................................................................................... 591
19.5.2 XBIC Error Injection Register (XBIC_EIR)............................................................................................... 593
19.5.3 XBIC Error Status Register (XBIC_ESR)................................................................................................... 593
19.5.4 XBIC Error Address Register (XBIC_EAR)............................................................................................... 596
19.6 Functional description...................................................................................................................................................597
Chapter 20
System Integration Unit Lite2 (SIUL2)
20.1 Introduction...................................................................................................................................................................599
20.1.1 Overview......................................................................................................................................................599
20.1.2 Features........................................................................................................................................................ 601
20.2 Memory map and register description.......................................................................................................................... 602
20.2.1 SIUL2 MCU ID Register #1 (SIUL2_MIDR1)........................................................................................... 647
20.2.2 SIUL2 MCU ID Register #2 (SIUL2_MIDR2)........................................................................................... 648
20.2.3 SIUL2 DMA/Interrupt Status Flag Register0 (SIUL2_DISR0).................................................................. 649
20.2.4 SIUL2 DMA/Interrupt Request Enable Register0 (SIUL2_DIRER0)........................................................ 654
20.2.5 SIUL2 DMA/Interrupt Request Select Register0 (SIUL2_DIRSR0).......................................................... 657
20.2.6 SIUL2 Interrupt Rising-Edge Event Enable Register 0 (SIUL2_IREER0).................................................661
20.2.7 SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0)................................................ 664
20.2.8 SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)......................................................................... 668
20.2.9 SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCRn)..................................................... 671
20.2.10 SIUL2 Interrupt Filter Clock Prescaler Register (SIUL2_IFCPR)..............................................................672
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20.2.11 SIUL2 Multiplexed Signal Configuration (SIUL2_MSCRn)......................................................................673
20.2.12 SIUL2 Input Multiplexed Signal Configuration Register (SIUL2_IMCRn)............................................... 679
20.2.13 SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)......................................................................... 680
20.2.14 SIUL2 GPIO Pad Data Input Register (SIUL2_GPDIn)............................................................................. 682
20.2.15 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO1)...............................................................684
20.2.16 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO0)...............................................................685
20.2.17 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO3)...............................................................686
20.2.18 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO2)...............................................................687
20.2.19 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO5)...............................................................688
20.2.20 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO4)...............................................................689
20.2.21 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO7)...............................................................690
20.2.22 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO6)...............................................................691
20.2.23 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO9)...............................................................692
20.2.24 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO8)...............................................................693
20.2.25 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDO10).............................................................694
20.2.26 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI1)...................................................................695
20.2.27 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI0)...................................................................695
20.2.28 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI3)...................................................................696
20.2.29 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI2)...................................................................697
20.2.30 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI5)...................................................................698
20.2.31 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI4)...................................................................698
20.2.32 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI7)...................................................................699
20.2.33 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI6)...................................................................700
20.2.34 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI9)...................................................................701
20.2.35 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI8)...................................................................701
20.2.36 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI10).................................................................702
20.2.37 SIUL2 Masked Parallel GPIO Pad Data Out Register (SIUL2_MPGPDOn)............................................. 703
20.3 Functional description...................................................................................................................................................704
20.3.1 General......................................................................................................................................................... 704
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20.3.2 Pad Control.................................................................................................................................................. 704
20.3.3 General Purpose Input and Output pads...................................................................................................... 705
20.3.4 External interrupts/DMA requests (EIRQ Pins).......................................................................................... 706
Chapter 21
Wakeup Unit (WKPU)
21.1 Chip specific WKPU information.................................................................................................................................711
21.1.1 WKPU configuration................................................................................................................................... 711
21.2 Introduction...................................................................................................................................................................712
21.3 Features.........................................................................................................................................................................712
21.4 WKPU memory map and register definition................................................................................................................ 713
21.4.1 NMI Status Flag Register (WKPU_NSR)................................................................................................... 713
21.4.2 NMI Configuration Register (WKPU_NCR).............................................................................................. 715
21.5 Functional description...................................................................................................................................................717
21.5.1 Non-maskable interrupts.............................................................................................................................. 717
21.6 Initialization Information..............................................................................................................................................719
21.6.1 Glitch Filter and Pad Configuration.............................................................................................................719
21.6.2 Non-Maskable Interrupts............................................................................................................................. 719
Chapter 22
Clocking
22.1 Introduction...................................................................................................................................................................721
22.2 Clock Generation.......................................................................................................................................................... 724
22.2.1 MC_CGM Registers.................................................................................................................................... 728
22.2.2 System clock frequency limitations............................................................................................................. 730
22.3 Clock sources................................................................................................................................................................732
22.3.1 PLLs............................................................................................................................................................. 732
22.3.2 FXOSC.........................................................................................................................................................738
22.3.3 FIRC.............................................................................................................................................................739
22.3.4 Clock sources — memory map....................................................................................................................739
22.4 Default clock configuration.......................................................................................................................................... 740
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22.5 Clock Gating................................................................................................................................................................. 740
22.6 Clock Monitoring..........................................................................................................................................................743
22.6.1 Introduction..................................................................................................................................................743
22.6.2 CMU configuration...................................................................................................................................... 743
22.6.3 Clock input sources......................................................................................................................................745
22.6.4 CMU Memory Map..................................................................................................................................... 746
22.6.5 CMU registers and field availability ...........................................................................................................746
22.6.6 CMU register write protection..................................................................................................................... 747
22.7 Peripheral clocking ...................................................................................................................................................... 747
22.7.1 Safety modules.............................................................................................................................................749
22.7.2 Memory system............................................................................................................................................751
22.7.3 CPU timer modules......................................................................................................................................754
22.7.4 Communication interface modules.............................................................................................................. 756
22.7.5 Generic modules.......................................................................................................................................... 765
22.7.6 Video Processing Modules...........................................................................................................................766
22.7.7 Analog Modules...........................................................................................................................................773
22.7.8 Boot modules............................................................................................................................................... 775
22.7.9 Compute and bus modules........................................................................................................................... 775
22.8 LBIST Clocking............................................................................................................................................................779
Chapter 23
Clock Generation Module (MC_CGM)
23.1 Introduction...................................................................................................................................................................781
23.1.1 Overview......................................................................................................................................................781
23.1.2 Features........................................................................................................................................................ 782
23.2 Memory map and register definition.............................................................................................................................783
23.3 MC_CGM_0 registers...................................................................................................................................................783
23.3.1 PCS Switch Duration Register (MC_CGM_0_PCS_SDUR)...................................................................... 786
23.3.2 PCS Divider Change Register 2 (MC_CGM_0_PCS_DIVC2)...................................................................786
23.3.3 PCS Divider End Register 2 (MC_CGM_0_PCS_DIVE2).........................................................................787
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23.3.4 PCS Divider Start Register 2 (MC_CGM_0_PCS_DIVS2)........................................................................ 788
23.3.5 Divider Update Type Register (MC_CGM_0_DIV_UPD_TYPE)............................................................. 788
23.3.6 Divider Update Trigger Register (MC_CGM_0_DIV_UPD_TRIG).......................................................... 790
23.3.7 Divider Update Status Register (MC_CGM_0_DIV_UPD_STAT)............................................................790
23.3.8 System Clock Select Status Register (MC_CGM_0_SC_SS)..................................................................... 792
23.3.9 System Clock Divider 0 Configuration Register (MC_CGM_0_SC_DC0)................................................793
23.3.10 System Clock Divider 1 Configuration Register (MC_CGM_0_SC_DC1)................................................794
23.3.11 System Clock Divider 2 Configuration Register (MC_CGM_0_SC_DC2)................................................795
23.3.12 Auxiliary Clock 0 Select Control Register (MC_CGM_0_AC0_SC)......................................................... 796
23.3.13 Auxiliary Clock 0 Select Status Register (MC_CGM_0_AC0_SS)............................................................797
23.3.14 Auxiliary Clock 0 Divider 0 Configuration Register (MC_CGM_0_AC0_DC0).......................................798
23.3.15 Auxiliary Clock 1 Select Control Register (MC_CGM_0_AC1_SC)......................................................... 798
23.3.16 Auxiliary Clock 1 Select Status Register (MC_CGM_0_AC1_SS)............................................................799
23.3.17 Auxiliary Clock 1 Divider 0 Configuration Register (MC_CGM_0_AC1_DC0).......................................800
23.3.18 Auxiliary Clock 2 Select Control Register (MC_CGM_0_AC2_SC)......................................................... 801
23.3.19 Auxiliary Clock 2 Select Status Register (MC_CGM_0_AC2_SS)............................................................802
23.3.20 Auxiliary Clock 2 Divider 0 Configuration Register (MC_CGM_0_AC2_DC0).......................................803
23.3.21 Auxiliary Clock 3 Select Control Register (MC_CGM_0_AC3_SC)......................................................... 804
23.3.22 Auxiliary Clock 3 Select Status Register (MC_CGM_0_AC3_SS)............................................................804
23.3.23 Auxiliary Clock 3 Divider 0 Configuration Register (MC_CGM_0_AC3_DC0).......................................805
23.3.24 Auxiliary Clock 4 Select Control Register (MC_CGM_0_AC4_SC)......................................................... 806
23.3.25 Auxiliary Clock 4 Select Status Register (MC_CGM_0_AC4_SS)............................................................807
23.3.26 Auxiliary Clock 4 Divider 0 Configuration Register (MC_CGM_0_AC4_DC0).......................................808
23.3.27 Auxiliary Clock 5 Select Control Register (MC_CGM_0_AC5_SC)......................................................... 809
23.3.28 Auxiliary Clock 5 Select Status Register (MC_CGM_0_AC5_SS)............................................................810
23.3.29 Auxiliary Clock 5 Divider 0 Configuration Register (MC_CGM_0_AC5_DC0).......................................811
23.3.30 Auxiliary Clock 5 Divider 1 Configuration Register (MC_CGM_0_AC5_DC1).......................................811
23.3.31 Auxiliary Clock 6 Select Control Register (MC_CGM_0_AC6_SC)......................................................... 812
23.3.32 Auxiliary Clock 6 Select Status Register (MC_CGM_0_AC6_SS)............................................................813
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23.3.33 Auxiliary Clock 6 Divider 0 Configuration Register (MC_CGM_0_AC6_DC0).......................................814
23.3.34 Auxiliary Clock 7 Select Control Register (MC_CGM_0_AC7_SC)......................................................... 815
23.3.35 Auxiliary Clock 7 Select Status Register (MC_CGM_0_AC7_SS)............................................................815
23.3.36 Auxiliary Clock 7 Divider 1 Configuration Register (MC_CGM_0_AC7_DC1).......................................816
23.3.37 Auxiliary Clock 8 Select Control Register (MC_CGM_0_AC8_SC)......................................................... 817
23.3.38 Auxiliary Clock 8 Select Status Register (MC_CGM_0_AC8_SS)............................................................818
23.3.39 Auxiliary Clock 8 Divider 0 Configuration Register (MC_CGM_0_AC8_DC0).......................................819
23.3.40 Auxiliary Clock 8 Divider 1 Configuration Register (MC_CGM_0_AC8_DC1).......................................819
23.3.41 Auxiliary Clock 9 Select Control Register (MC_CGM_0_AC9_SC)......................................................... 820
23.3.42 Auxiliary Clock 9 Select Status Register (MC_CGM_0_AC9_SS)............................................................821
23.3.43 Auxiliary Clock 9 Divider 0 Configuration Register (MC_CGM_0_AC9_DC0).......................................822
23.3.44 Auxiliary Clock 9 Divider 1 Configuration Register (MC_CGM_0_AC9_DC1).......................................823
23.3.45 Auxiliary Clock 10 Select Control Register (MC_CGM_0_AC10_SC)..................................................... 824
23.3.46 Auxiliary Clock 10 Select Status Register (MC_CGM_0_AC10_SS)........................................................825
23.3.47 Auxiliary Clock 10 Divider 0 Configuration Register (MC_CGM_0_AC10_DC0)...................................825
23.3.48 Auxiliary Clock 10 Divider 1 Configuration Register (MC_CGM_0_AC10_DC1)...................................826
23.3.49 Auxiliary Clock 11 Select Control Register (MC_CGM_0_AC11_SC)..................................................... 827
23.3.50 Auxiliary Clock 11 Select Status Register (MC_CGM_0_AC11_SS)........................................................828
23.3.51 Auxiliary Clock 11 Divider 0 Configuration Register (MC_CGM_0_AC11_DC0)...................................829
23.3.52 Auxiliary Clock 12 Select Control Register (MC_CGM_0_AC12_SC)..................................................... 830
23.3.53 Auxiliary Clock 12 Select Status Register (MC_CGM_0_AC12_SS)........................................................831
23.3.54 Auxiliary Clock 12 Divider 0 Configuration Register (MC_CGM_0_AC12_DC0)...................................831
23.3.55 Auxiliary Clock 13 Select Control Register (MC_CGM_0_AC13_SC)..................................................... 832
23.3.56 Auxiliary Clock 13 Select Status Register (MC_CGM_0_AC13_SS)........................................................833
23.3.57 Auxiliary Clock 13 Divider 0 Configuration Register (MC_CGM_0_AC13_DC0)...................................834
23.3.58 Auxiliary Clock 14 Select Control Register (MC_CGM_0_AC14_SC)..................................................... 835
23.3.59 Auxiliary Clock 14 Select Status Register (MC_CGM_0_AC14_SS)........................................................836
23.3.60 Auxiliary Clock 14 Divider 0 Configuration Register (MC_CGM_0_AC14_DC0)...................................837
23.3.61 Auxiliary Clock 15 Select Control Register (MC_CGM_0_AC15_SC)..................................................... 838
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23.3.62 Auxiliary Clock 15 Select Status Register (MC_CGM_0_AC15_SS)........................................................839
23.3.63 Auxiliary Clock 15 Divider 0 Configuration Register (MC_CGM_0_AC15_DC0)...................................839
23.4 MC_CGM_1 registers...................................................................................................................................................840
23.4.1 PCS Switch Duration Register (MC_CGM_1_PCS_SDUR)...................................................................... 841
23.4.2 PCS Divider Change Register 2 (MC_CGM_1_PCS_DIVC2)...................................................................841
23.4.3 PCS Divider End Register 2 (MC_CGM_1_PCS_DIVE2).........................................................................842
23.4.4 PCS Divider Start Register 2 (MC_CGM_1_PCS_DIVS2)........................................................................ 843
23.4.5 Divider Update Type Register (MC_CGM_1_DIV_UPD_TYPE)............................................................. 843
23.4.6 Divider Update Trigger Register (MC_CGM_1_DIV_UPD_TRIG).......................................................... 844
23.4.7 Divider Update Status Register (MC_CGM_1_DIV_UPD_STAT)............................................................845
23.4.8 System Clock Select Status Register (MC_CGM_1_SC_SS)..................................................................... 846
23.4.9 System Clock Divider 0 Configuration Register (MC_CGM_1_SC_DC0)................................................848
23.4.10 System Clock Divider 1 Configuration Register (MC_CGM_1_SC_DC1)................................................849
23.4.11 System Clock Divider 2 Configuration Register (MC_CGM_1_SC_DC2)................................................850
23.5 MC_CGM_2 registers...................................................................................................................................................851
23.5.1 PCS Switch Duration Register (MC_CGM_2_PCS_SDUR)...................................................................... 852
23.5.2 PCS Divider Change Register 2 (MC_CGM_2_PCS_DIVC2)...................................................................852
23.5.3 PCS Divider End Register 2 (MC_CGM_2_PCS_DIVE2).........................................................................853
23.5.4 PCS Divider Start Register 2 (MC_CGM_2_PCS_DIVS2)........................................................................ 854
23.5.5 Divider Update Type Register (MC_CGM_2_DIV_UPD_TYPE)............................................................. 854
23.5.6 Divider Update Trigger Register (MC_CGM_2_DIV_UPD_TRIG).......................................................... 855
23.5.7 Divider Update Status Register (MC_CGM_2_DIV_UPD_STAT)............................................................856
23.5.8 System Clock Select Status Register (MC_CGM_2_SC_SS)..................................................................... 857
23.5.9 System Clock Divider 0 Configuration Register (MC_CGM_2_SC_DC0)................................................859
23.5.10 Auxiliary Clock 0 Select Control Register (MC_CGM_2_AC0_SC)......................................................... 860
23.5.11 Auxiliary Clock 0 Select Status Register (MC_CGM_2_AC0_SS)............................................................861
23.5.12 Auxiliary Clock 0 Divider 0 Configuration Register (MC_CGM_2_AC0_DC0).......................................861
23.5.13 Auxiliary Clock 2 Select Control Register (MC_CGM_2_AC2_SC)......................................................... 862
23.5.14 Auxiliary Clock 2 Select Status Register (MC_CGM_2_AC2_SS)............................................................863
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23.5.15 Auxiliary Clock 2 Divider 0 Configuration Register (MC_CGM_2_AC2_DC0).......................................864
23.5.16 Auxiliary Clock 3 Select Control Register (MC_CGM_2_AC3_SC)......................................................... 865
23.5.17 Auxiliary Clock 3 Select Status Register (MC_CGM_2_AC3_SS)............................................................865
23.5.18 Auxiliary Clock 3 Divider 0 Configuration Register (MC_CGM_2_AC3_DC0).......................................866
23.5.19 Auxiliary Clock 4 Select Control Register (MC_CGM_2_AC4_SC)......................................................... 867
23.5.20 Auxiliary Clock 4 Select Status Register (MC_CGM_2_AC4_SS)............................................................868
23.5.21 Auxiliary Clock 4 Divider 0 Configuration Register (MC_CGM_2_AC4_DC0).......................................869
23.6 MC_CGM_3 registers...................................................................................................................................................870
23.6.1 PCS Switch Duration Register (MC_CGM_3_PCS_SDUR)...................................................................... 871
23.6.2 PCS Divider Change Register 2 (MC_CGM_3_PCS_DIVC2)...................................................................871
23.6.3 PCS Divider End Register 2 (MC_CGM_3_PCS_DIVE2).........................................................................872
23.6.4 PCS Divider Start Register 2 (MC_CGM_3_PCS_DIVS2)........................................................................ 873
23.6.5 Divider Update Type Register (MC_CGM_3_DIV_UPD_TYPE)............................................................. 873
23.6.6 Divider Update Trigger Register (MC_CGM_3_DIV_UPD_TRIG).......................................................... 874
23.6.7 Divider Update Status Register (MC_CGM_3_DIV_UPD_STAT)............................................................875
23.6.8 System Clock Select Status Register (MC_CGM_3_SC_SS)..................................................................... 876
23.6.9 System Clock Divider 0 Configuration Register (MC_CGM_3_SC_DC0)................................................878
23.6.10 System Clock Divider 1 Configuration Register (MC_CGM_3_SC_DC1)................................................879
23.7 Functional description...................................................................................................................................................880
23.7.1 System clock generation.............................................................................................................................. 880
23.7.2 Dividers functional description....................................................................................................................884
23.7.3 Aux Divider Programming...........................................................................................................................887
Chapter 24
PLL Digital Interface (PLLDIG)
24.1 Introduction...................................................................................................................................................................889
24.2 Block Diagram..............................................................................................................................................................889
24.3 Features.........................................................................................................................................................................889
24.4 Modes of operation....................................................................................................................................................... 889
24.4.1 Normal mode with reference, PLL enabled................................................................................................. 890
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24.5 Memory map and register definition.............................................................................................................................890
24.5.1 PLLDIG PLL Control Register (PLLDIG_PLLCR)................................................................................... 891
24.5.2 PLLDIG PLL Status Register (PLLDIG_PLLSR)...................................................................................... 893
24.5.3 PLLDIG PLL Divider Register (PLLDIG_PLLDV)................................................................................... 895
24.5.4 PLLDIG PLL Frequency Modulation Register (PLLDIG_PLLFM)...........................................................897
24.5.5 PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD)....................................................................899
24.5.6 PLL Calibration Register 1 (PLLDIG_PLLCAL1)..................................................................................... 901
24.6 Functional description...................................................................................................................................................902
24.6.1 Input clock frequency...................................................................................................................................902
24.6.2 Clock configuration......................................................................................................................................902
24.6.3 Loss of lock..................................................................................................................................................903
24.6.4 Frequency modulation..................................................................................................................................903
24.7 Initialization information.............................................................................................................................................. 905
Chapter 25
Digital Frequency Synthesizer (DFS)
25.1 Introduction...................................................................................................................................................................907
25.2 Features.........................................................................................................................................................................907
25.3 Memory map and register definition.............................................................................................................................907
25.3.1 DFS DLL Program Register 1 (DFS_DLLPRG1).......................................................................................908
25.3.2 DFS Clockout Enable Register (DFS_CLKOUTEN)..................................................................................910
25.3.3 DFS Port Status Register (DFS_PORTSR)................................................................................................. 910
25.3.4 DFS Port Loss of Lock Status Register (DFS_PORTLOLSR)....................................................................911
25.3.5 DFS Port Reset register (DFS_PORTRESET)............................................................................................ 911
25.3.6 DFS Control Register (DFS_CTRL)............................................................................................................912
25.3.7 DFS Divide Register Portn (DFS_DVPORTn)........................................................................................... 913
25.4 Functional Description..................................................................................................................................................913
Chapter 26
Fast OSC Digital Interface (FXOSC)
26.1 Introduction...................................................................................................................................................................915
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26.2 Functional description...................................................................................................................................................915
26.2.1 Oscillator startup delay................................................................................................................................ 916
26.2.2 Oscillator clock available interrupt.............................................................................................................. 916
26.2.3 Oscillator bypass mode................................................................................................................................ 916
26.3 Memory map and register definition.............................................................................................................................917
26.3.1 FXOSC Control Register (FXOSC_CTL)................................................................................................... 917
Chapter 27
Clock Monitor Unit (CMU)
27.1 Introduction...................................................................................................................................................................921
27.1.1 Main features................................................................................................................................................922
27.2 Block diagram...............................................................................................................................................................922
27.3 Signals...........................................................................................................................................................................922
27.4 Register description and memory map......................................................................................................................... 923
27.4.1 CMU Control Status Register (CMU_CSR)................................................................................................924
27.4.2 CMU Frequency Display Register (CMU_FDR)........................................................................................ 925
27.4.3 CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)...................................................926
27.4.4 CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)....................................................926
27.4.5 CMU Interrupt Status Register (CMU_ISR)............................................................................................... 927
27.4.6 CMU Measurement Duration Register (CMU_MDR)................................................................................ 928
27.5 Functional description...................................................................................................................................................929
27.5.1 Frequency meter...........................................................................................................................................929
27.5.2 CLKMN0_RMT supervisor.........................................................................................................................929
27.5.3 CLKMN1 supervisor....................................................................................................................................930
Chapter 28
Reset Overview
28.1 Introduction...................................................................................................................................................................933
28.1.1 Global Reset.................................................................................................................................................933
28.1.2 Local Reset...................................................................................................................................................933
28.1.3 Reset sources................................................................................................................................................933
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28.2 Global Reset Process.....................................................................................................................................................935
28.2.1 Overview......................................................................................................................................................935
28.2.2 Reset Process Modules.................................................................................................................................935
28.2.3 Reset Process Sequences..............................................................................................................................938
28.2.4 Reset Process State Transitions....................................................................................................................939
28.2.5 Module Status During Reset Process........................................................................................................... 948
Chapter 29
System Reset Controller (SRC)
29.1 Overview.......................................................................................................................................................................949
29.2 Memory map and register definition.............................................................................................................................949
29.2.1 Boot Mode Register 1 (SRC_BMR1).......................................................................................................... 951
29.2.2 Boot Mode Register 2 (SRC_BMR2).......................................................................................................... 951
29.2.3 General Purpose Register 1 For Boot (SRC_GPR1_BOOT).......................................................................953
29.2.4 General Purpose Register 1 (SRC_GPR1)...................................................................................................954
29.2.5 General Purpose Register 2 (SRC_GPR2)...................................................................................................955
29.2.6 General Purpose Register 3 (SRC_GPR3)...................................................................................................956
29.2.7 General Purpose Register 4 (SRC_GPR4)...................................................................................................958
29.2.8 General Purpose Register 5 (SRC_GPR5)...................................................................................................958
29.2.9 General Purpose Register 6 (SRC_GPR6)...................................................................................................961
29.2.10 General Purpose Register 8 (SRC_GPR8)...................................................................................................963
29.2.11 General Purpose Register 10 (SRC_GPR10)...............................................................................................964
29.2.12 General Purpose Register 11 (SRC_GPR11)...............................................................................................965
29.2.13 General Purpose Register 12 (SRC_GPR12)...............................................................................................967
29.2.14 General Purpose Register 13 (SRC_GPR13)...............................................................................................968
29.2.15 General Purpose Register 14 (SRC_GPR14)...............................................................................................970
29.2.16 General Purpose Register 15 (SRC_GPR15)...............................................................................................972
29.2.17 General Purpose Register 16 (SRC_GPR16)...............................................................................................973
29.2.18 General Purpose Register 18 (SRC_GPR18)...............................................................................................975
29.2.19 General Purpose Register 19 (SRC_GPR19)...............................................................................................975
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29.2.20 General Purpose Register 20 (SRC_GPR20)...............................................................................................976
29.2.21 General Purpose Register 21 (SRC_GPR21)...............................................................................................976
29.2.22 General Purpose Register 22 (SRC_GPR22)...............................................................................................977
29.2.23 DDR_MEMORY_ACCESS_SECURE (SRC_GPR23)..............................................................................977
29.2.24 DDR_MEMORY_ACCESS_NON_SECURE (SRC_GPR24)................................................................... 977
29.2.25 SRAM_MEMORY_ACCESS_SECURE (SRC_GPR25)...........................................................................978
29.2.26 SRAM_MEMORY_ACCESS_NON_SECURE (SRC_GPR26)................................................................ 978
29.2.27 SELFTEST CONFIGURATION REGISTER (SRC_GPR27)....................................................................979
29.2.28 PCIe Configuration1 register (SRC_PCIE_CONFIG_1)............................................................................ 980
29.2.29 DDR Self Refresh Control register (SRC_DDR_SELF_REF_CTRL)........................................................983
29.2.30 PCIe Configuration0 register (SRC_PCIE_CONFIG_0)............................................................................ 985
29.2.31 SOC_MISC_CONFIG REGISTER 2 (SRC_SOC_MISC_CONFIG2)...................................................... 987
Chapter 30
System Boot
30.1 Introduction...................................................................................................................................................................989
30.2 Boot Modes...................................................................................................................................................................990
30.2.1 Boot vector in AARCH64 (default mode)................................................................................................... 990
30.2.2 Boot Modes Pin Settings..............................................................................................................................991
30.2.3 High Level Boot Sequence.......................................................................................................................... 991
30.2.4 Boot from Fuses........................................................................................................................................... 994
30.2.5 Serial Download Mode................................................................................................................................ 994
30.2.6 Boot from RCON......................................................................................................................................... 994
30.3 Device Configuration....................................................................................................................................................995
30.3.1 Boot eFuse Descriptions.............................................................................................................................. 995
30.3.2 GPIO Boot Config Select.............................................................................................................................997
30.4 Device Initialization......................................................................................................................................................998
30.4.1 Internal ROM and RAM Memory Map....................................................................................................... 999
30.4.2 Boot block activation................................................................................................................................... 1001
30.4.3 Clocks at boot time...................................................................................................................................... 1001
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30.4.4 Enabling Caches...........................................................................................................................................1002
30.4.5 Error Logging...............................................................................................................................................1002
30.4.6 Exception Handling......................................................................................................................................1005
30.4.7 Interrupt Handling........................................................................................................................................1006
30.4.8 NMI Handling.............................................................................................................................................. 1006
30.4.9 Fast Reboot.................................................................................................................................................. 1006
30.5 Boot Device (Internal Boot)..........................................................................................................................................1007
30.5.1 QuadSPI Serial Flash Memory Boot............................................................................................................1007
30.5.2 Expansion Device (SD/MMC/eMMC) Boot............................................................................................... 1015
30.6 Program Image..............................................................................................................................................................1026
30.6.1 Image Vector Table and Boot Data..............................................................................................................1026
30.6.2 Device Configuration Data.......................................................................................................................... 1028
30.6.3 Self Test Image............................................................................................................................................ 1034
30.7 Serial Downloader........................................................................................................................................................ 1035
30.7.1 Serial Download Protocol............................................................................................................................ 1036
30.7.2 FlexCAN Boot............................................................................................................................................. 1038
30.7.3 UART Boot.................................................................................................................................................. 1039
30.8 Application Boot...........................................................................................................................................................1040
30.8.1 Boot Cortex-A53[0] Mode...........................................................................................................................1041
30.8.2 Application boot address validation.............................................................................................................1042
Chapter 31
Reset Generation Module (MC_RGM)
31.1 Introduction...................................................................................................................................................................1043
31.1.1 Overview......................................................................................................................................................1043
31.1.2 Features........................................................................................................................................................ 1044
31.1.3 Reset Sources............................................................................................................................................... 1045
31.2 External signal description............................................................................................................................................1046
31.3 Memory map and register definition.............................................................................................................................1047
31.3.1 'Destructive' Event Status Register (MC_RGM_DES)................................................................................1048
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31.3.2 'Functional' Event Status Register (MC_RGM_FES)..................................................................................1050
31.3.3 'Functional' Event Reset Disable Register (MC_RGM_FERD).................................................................. 1052
31.3.4 'Functional' Bidirectional Reset Enable Register (MC_RGM_FBRE)........................................................1053
31.3.5 Functional' Event Short Sequence Register (MC_RGM_FESS)................................................................. 1055
31.3.6 DDR Handshake Enable Register (MC_RGM_DDR_HE)......................................................................... 1057
31.3.7 DDR Handshake Status Register (MC_RGM_DDR_HS)...........................................................................1059
31.3.8 Functional Reset Handshake Enable (MC_RGM_FRHE)...........................................................................1060
31.3.9 Functional Reset Escalation Counter (MC_RGM_FREC).......................................................................... 1061
31.3.10 'Functional' Reset Escalation Threshold Register (MC_RGM_FRET)....................................................... 1062
31.3.11 'Destructive' Reset Escalation Threshold Register (MC_RGM_DRET)..................................................... 1063
31.4 Functional description...................................................................................................................................................1063
31.4.1 Reset state machine......................................................................................................................................1063
31.4.2 'Destructive' resets........................................................................................................................................1066
31.4.3 Bi-directional External reset........................................................................................................................ 1067
31.4.4 'Functional' resets......................................................................................................................................... 1067
31.4.5 'Functional' reset escalation..........................................................................................................................1068
31.4.6 'Destructive' reset escalation........................................................................................................................ 1068
Chapter 32
On-Chip One Time Programmable (OCOTP) Controller
32.1 Introduction...................................................................................................................................................................1071
32.2 Overview of On-Chip OTP (OCOTP) controller..........................................................................................................1071
32.3 Top-level symbol and functional overview.................................................................................................................. 1072
32.3.1 Operation......................................................................................................................................................1072
32.3.2 OTP read/write timing parameters...............................................................................................................1078
32.3.3 Behavior During Reset.................................................................................................................................1079
32.4 Memory map and register definition.............................................................................................................................1079
32.4.1 OTP Controller Control Register (OCOTP_CTRLn).................................................................................. 1085
32.4.2 OTP Controller Timing Register (OCOTP_TIMING)................................................................................ 1087
32.4.3 OTP Controller Write Data Register (OCOTP_DATA)..............................................................................1088
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32.4.4 OTP Controller Read Control Register (OCOTP_READ_CTRL).............................................................. 1089
32.4.5 OTP Controller Read Data Register (OCOTP_READ_FUSE_DATA)...................................................... 1090
32.4.6 Sticky bit Register (OCOTP_SW_STICKY)...............................................................................................1090
32.4.7 OTP Controller CRC test address (OCOTP_CRC_ADDR)........................................................................ 1091
32.4.8 OTP Controller CRC Value Register (OCOTP_CRC_VALUE)................................................................ 1091
32.4.9 OTP Controller Version Register (OCOTP_VERSION).............................................................................1092
32.4.10 Value of OTP Bank4 Word2 (MAC Address0) (OCOTP_MAC0).............................................................1092
32.4.11 Value of OTP Bank4 Word3 (MAC Address) (OCOTP_MAC1)...............................................................1093
32.4.12 Value of OTP Bank4 Word6 (HW Capabilities) (OCOTP_GP1)............................................................... 1093
32.4.13 Value of OTP Bank4 Word7 (HW Capabilities) (OCOTP_GP2)............................................................... 1094
32.4.14 Value of OTP Bank5 Word2 (OCOTP_MISC_CONF).............................................................................. 1094
32.4.15 Value of OTP Bank5 Word3 (OCOTP_FIELD_RTN)................................................................................1095
32.4.16 Value of OTP Bank5 Word4 (OCOTP_MISC2)......................................................................................... 1096
32.4.17 Value of OTP Bank5 Word5 (CRC0) (OCOTP_CRC0)............................................................................. 1096
32.4.18 Value of OTP Bank5 Word6 (CRC1) (OCOTP_CRC1)............................................................................. 1096
32.4.19 Value of OTP Bank5 Word7 (CRC2) (OCOTP_CRC2)............................................................................. 1097
32.4.20 Value of OTP Bank6 Word0 (CRC3) (OCOTP_CRC3)............................................................................. 1097
32.4.21 Value of OTP Bank6 Word1 (CRC4) (OCOTP_CRC4)............................................................................. 1098
32.4.22 Value of OTP Bank6 Word2 (CRC5) (OCOTP_CRC5)............................................................................. 1098
32.4.23 ECC Fuse words (OCOTP_ECC_FUSEn).................................................................................................. 1099
32.4.24 Redundant Fuse words (OCOTP_REDUNDANT_FUSEn)........................................................................1099
32.4.25 Single Bit ECC Error status (OCOTP_SEC0)............................................................................................. 1100
32.4.26 Single Bit ECC Error status (OCOTP_SEC1)............................................................................................. 1101
32.4.27 Single Bit ECC Error status (OCOTP_DEC0)............................................................................................ 1102
32.4.28 Double Bit ECC Error status (OCOTP_DEC1)...........................................................................................1103
Chapter 33
Quad Serial Peripheral Interface (QuadSPI)
33.1 Introduction...................................................................................................................................................................1105
33.1.1 Features........................................................................................................................................................ 1105
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33.1.2 Block Diagram............................................................................................................................................. 1106
33.1.3 QuadSPI Modes of Operation...................................................................................................................... 1107
33.1.4 Acronyms and Abbreviations.......................................................................................................................1108
33.1.5 Glossary for QuadSPI module..................................................................................................................... 1108
33.2 External Signal Description.......................................................................................................................................... 1110
33.2.1 Driving External Signals..............................................................................................................................1111
33.3 Memory Map and Register Definition..........................................................................................................................1113
33.3.1 Register Write Access..................................................................................................................................1113
33.3.2 Peripheral Bus Register Descriptions.......................................................................................................... 1114
33.3.3 Serial Flash Address Assignment................................................................................................................ 1158
33.3.4 AMBA Bus Register Memory Map............................................................................................................. 1158
33.3.5 AHB Bus Register Memory Map Descriptions........................................................................................... 1160
33.4 Interrupt Signals............................................................................................................................................................1166
33.5 Functional Description..................................................................................................................................................1167
33.5.1 Serial Flash Access Schemes....................................................................................................................... 1167
33.5.2 Modes of Operation..................................................................................................................................... 1168
33.5.3 Normal Mode............................................................................................................................................... 1168
33.6 Initialization/Application Information..........................................................................................................................1191
33.6.1 Power Up and Reset.....................................................................................................................................1191
33.6.2 Available Status/Flag Information............................................................................................................... 1191
33.6.3 Exclusive Access to Serial Flash for AHB Commands............................................................................... 1194
33.6.4 Command Arbitration ................................................................................................................................. 1195
33.6.5 Flash Device Selection.................................................................................................................................1196
33.6.6 DMA Usage................................................................................................................................................. 1196
33.6.7 Parallel mode................................................................................................................................................1200
33.7 Byte Ordering - Endianness..........................................................................................................................................1202
33.7.1 Programming Flash Data............................................................................................................................. 1203
33.7.2 Reading Flash Data into the RX Buffer....................................................................................................... 1204
33.7.3 Reading Flash Data into the AHB Buffer.................................................................................................... 1205
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33.8 Serial Flash Devices......................................................................................................................................................1205
33.8.1 Example Sequences......................................................................................................................................1205
33.8.2 Dual Die Flashes.......................................................................................................................................... 1211
33.8.3 Boot initialization sequence......................................................................................................................... 1212
33.9 Sampling of Serial Flash Input Data.............................................................................................................................1213
33.9.1 Basic Description......................................................................................................................................... 1213
33.9.2 Supported read modes..................................................................................................................................1214
33.9.3 Data Strobe (DQS) sampling method.......................................................................................................... 1215
33.10 Data Input Hold Requirement of Flash.........................................................................................................................1220
Chapter 34
Multi Mode DDR Controller (MMDC)
34.1 Chip-specific MMDC information............................................................................................................................... 1223
34.1.1 MMDC Configuration..................................................................................................................................1223
34.1.2 MMDC Core AXI Re-ordering Control Register (MAARCR) Settings..................................................... 1224
34.1.3 DDR memory contents retention on a functional reset................................................................................1224
34.1.4 DDR memory contents retention across selftest.......................................................................................... 1225
34.1.5 MASTER AXI ID programming for using MMDC profiling feature......................................................... 1226
34.2 Overview.......................................................................................................................................................................1227
34.2.1 MMDC feature summary............................................................................................................................. 1228
34.3 External Signals............................................................................................................................................................ 1231
34.4 Functional Description..................................................................................................................................................1231
34.4.1 Write/Read data flow................................................................................................................................... 1231
34.4.2 MMDC initialization ...................................................................................................................................1233
34.4.3 Configuring the MMDC registers................................................................................................................ 1234
34.4.4 MMDC Address Space................................................................................................................................ 1235
34.4.5 LPDDR2 and DDR3 pin mux mapping....................................................................................................... 1240
34.4.6 Power Saving and Clock Frequency Change modes................................................................................... 1241
34.4.7 Reset ............................................................................................................................................................1243
34.4.8 Refresh Scheme............................................................................................................................................1244
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34.4.9 Burst Length options towards DDR ............................................................................................................1245
34.4.10 Exclusive accesses handling........................................................................................................................ 1246
34.4.11 AXI Error Handling..................................................................................................................................... 1247
34.5 Performance.................................................................................................................................................................. 1247
34.5.1 Arbitration and reordering mechanism........................................................................................................ 1247
34.5.2 Prediction mechanism.................................................................................................................................. 1250
34.5.3 Special Optimization for accesses towards DDR3...................................................................................... 1250
34.6 MMDC Debug ............................................................................................................................................................. 1251
34.6.1 Hardware debug monitor............................................................................................................................. 1251
34.6.2 Step By Step (SBS) software monitor..........................................................................................................1251
34.7 MMDC Profiling...........................................................................................................................................................1252
34.8 LPDDR2 Refresh Rate Update and Timing Derating...................................................................................................1253
34.9 DLL Off mode.............................................................................................................................................................. 1254
34.10 ODT Configuration ......................................................................................................................................................1255
34.11 Calibration Process....................................................................................................................................................... 1256
34.11.1 Delay-line.....................................................................................................................................................1257
34.11.2 ZQ calibration ............................................................................................................................................. 1258
34.11.3 Read DQS Gating Calibration......................................................................................................................1261
34.11.4 Read Calibration.......................................................................................................................................... 1267
34.11.5 Write Calibration..........................................................................................................................................1272
34.11.6 Write leveling Calibration............................................................................................................................1275
34.11.7 Read fine tuning........................................................................................................................................... 1279
34.12 MMDC Memory Map/Register Definition...................................................................................................................1279
34.12.1 MMDC Core Control Register (MMDC_MDCTL).................................................................................... 1283
34.12.2 MMDC Core Power Down Control Register (MMDC_MDPDC).............................................................. 1284
34.12.3 MMDC Core ODT Timing Control Register (MMDC_MDOTC)..............................................................1287
34.12.4 MMDC Core Timing Configuration Register 0 (MMDC_MDCFG0)........................................................ 1288
34.12.5 MMDC Core Timing Configuration Register 1 (MMDC_MDCFG1)........................................................ 1290
34.12.6 MMDC Core Timing Configuration Register 2 (MMDC_MDCFG2)........................................................ 1293
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34.12.7 MMDC Core Miscellaneous Register (MMDC_MDMISC)....................................................................... 1295
34.12.8 MMDC Core Special Command Register (MMDC_MDSCR)................................................................... 1298
34.12.9 MMDC Core Refresh Control Register (MMDC_MDREF)....................................................................... 1301
34.12.10 MMDC Core Read/Write Command Delay Register (MMDC_MDRWD)................................................ 1303
34.12.11 MMDC Core Out of Reset Delays Register (MMDC_MDOR).................................................................. 1305
34.12.12 MMDC Core MRR Data Register (MMDC_MDMRR)..............................................................................1306
34.12.13 MMDC Core Timing Configuration Register 3 (MMDC_MDCFG3LP)................................................... 1307
34.12.14 MMDC Core MR4 Derating Register (MMDC_MDMR4).........................................................................1309
34.12.15 MMDC Core Address Space Partition Register (MMDC_MDASP).......................................................... 1310
34.12.16 MMDC Core AXI Reordering Control Regsiter (MMDC_MAARCR)......................................................1311
34.12.17 MMDC Core Power Saving Control and Status Register (MMDC_MAPSR)............................................1314
34.12.18 MMDC Core Exclusive ID Monitor Register0 (MMDC_MAEXIDR0).....................................................1316
34.12.19 MMDC Core Exclusive ID Monitor Register1 (MMDC_MAEXIDR1).....................................................1317
34.12.20 MMDC Core Debug and Profiling Control Register 0 (MMDC_MADPCR0)...........................................1318
34.12.21 MMDC Core Debug and Profiling Control Register 1 (MMDC_MADPCR1)...........................................1319
34.12.22 MMDC Core Debug and Profiling Status Register 0 (MMDC_MADPSR0)..............................................1320
34.12.23 MMDC Core Debug and Profiling Status Register 1 (MMDC_MADPSR1)..............................................1320
34.12.24 MMDC Core Debug and Profiling Status Register 2 (MMDC_MADPSR2)..............................................1321
34.12.25 MMDC Core Debug and Profiling Status Register 3 (MMDC_MADPSR3)..............................................1321
34.12.26 MMDC Core Debug and Profiling Status Register 4 (MMDC_MADPSR4)..............................................1322
34.12.27 MMDC Core Debug and Profiling Status Register 5 (MMDC_MADPSR5)..............................................1322
34.12.28 MMDC Core Step By Step Address Register (MMDC_MASBS0)............................................................ 1323
34.12.29 MMDC Core Step By Step Address Attributes Register (MMDC_MASBS1)........................................... 1323
34.12.30 MMDC Core General Purpose Register (MMDC_MAGENP)................................................................... 1324
34.12.31 MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL).......................................................... 1325
34.12.32 MMDC PHY ZQ SW control register (MMDC_MPZQSWCTRL)............................................................1328
34.12.33 MMDC PHY Write Leveling Configuration and Error Status Register (MMDC_MPWLGCR)............... 1330
34.12.34 MMDC PHY Write Leveling Delay Control Register 0 (MMDC_MPWLDECTRL0)..............................1333
34.12.35 MMDC PHY Write Leveling Delay Control Register 1 (MMDC_MPWLDECTRL1)..............................1335
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34.12.36 MMDC PHY Write Leveling delay-line Status Register (MMDC_MPWLDLST).................................... 1338
34.12.37 MMDC PHY ODT control register (MMDC_MPODTCTRL)...................................................................1339
34.12.38 MMDC PHY Read DQ Byte0 Delay Register (MMDC_MPRDDQBY0DL)............................................ 1341
34.12.39 MMDC PHY Read DQ Byte1 Delay Register (MMDC_MPRDDQBY1DL)............................................ 1344
34.12.40 MMDC PHY Read DQ Byte2 Delay Register (MMDC_MPRDDQBY2DL)............................................ 1347
34.12.41 MMDC PHY Read DQ Byte3 Delay Register (MMDC_MPRDDQBY3DL)............................................ 1349
34.12.42 MMDC PHY Read DQS Gating Control Register 0 (MMDC_MPDGCTRL0)......................................... 1352
34.12.43 MMDC PHY Read DQS Gating Control Register 1 (MMDC_MPDGCTRL1)......................................... 1354
34.12.44 MMDC PHY Read DQS Gating delay-line Status Register (MMDC_MPDGDLST0)..............................1357
34.12.45 MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL)....................................1358
34.12.46 MMDC PHY Read delay-lines Status Register (MMDC_MPRDDLST)................................................... 1360
34.12.47 MMDC PHY Write delay-lines Configuration Register (MMDC_MPWRDLCTL).................................. 1361
34.12.48 MMDC PHY Write delay-lines Status Register (MMDC_MPWRDLST)..................................................1362
34.12.49 MMDC ZQ LPDDR2 HW Control Register (MMDC_MPZQLP2CTL)....................................................1363
34.12.50 MMDC PHY Read Delay HW Calibration Control Register (MMDC_MPRDDLHWCTL).....................1365
34.12.51 MMDC PHY Write Delay HW Calibration Control Register (MMDC_MPWRDLHWCTL)................... 1367
34.12.52 MMDC PHY Read Delay HW Calibration Status Register 0 (MMDC_MPRDDLHWST0)..................... 1368
34.12.53 MMDC PHY Read Delay HW Calibration Status Register 1 (MMDC_MPRDDLHWST1)..................... 1369
34.12.54 MMDC PHY Write Delay HW Calibration Status Register 0 (MMDC_MPWRDLHWST0)................... 1370
34.12.55 MMDC PHY Write Delay HW Calibration Status Register 1 (MMDC_MPWRDLHWST1)................... 1371
34.12.56 MMDC PHY Write Leveling HW Error Register (MMDC_MPWLHWERR).......................................... 1372
34.12.57 MMDC PHY Read DQS Gating HW Status Register 0 (MMDC_MPDGHWST0)...................................1372
34.12.58 MMDC PHY Read DQS Gating HW Status Register 1 (MMDC_MPDGHWST1)...................................1373
34.12.59 MMDC PHY Read DQS Gating HW Status Register 2 (MMDC_MPDGHWST2)...................................1373
34.12.60 MMDC PHY Read DQS Gating HW Status Register 3 (MMDC_MPDGHWST3)...................................1374
34.12.61 MMDC PHY Pre-defined Compare Register 1 (MMDC_MPPDCMPR1)................................................. 1375
34.12.62 MMDC PHY Pre-defined Compare and CA delay-line Configuration Register
(MMDC_MPPDCMPR2)............................................................................................................................ 1376
34.12.63 MMDC PHY SW Dummy Access Register (MMDC_MPSWDAR0)........................................................1378
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34.12.64 MMDC PHY SW Dummy Read Data Register 0 (MMDC_MPSWDRDR0).............................................1379
34.12.65 MMDC PHY SW Dummy Read Data Register 1 (MMDC_MPSWDRDR1).............................................1380
34.12.66 MMDC PHY SW Dummy Read Data Register 2 (MMDC_MPSWDRDR2).............................................1380
34.12.67 MMDC PHY SW Dummy Read Data Register 3 (MMDC_MPSWDRDR3).............................................1380
34.12.68 MMDC PHY SW Dummy Read Data Register 4 (MMDC_MPSWDRDR4).............................................1381
34.12.69 MMDC PHY SW Dummy Read Data Register 5 (MMDC_MPSWDRDR5).............................................1381
34.12.70 MMDC PHY SW Dummy Read Data Register 6 (MMDC_MPSWDRDR6).............................................1382
34.12.71 MMDC PHY SW Dummy Read Data Register 7 (MMDC_MPSWDRDR7).............................................1382
34.12.72 MMDC PHY Measure Unit Register (MMDC_MPMUR0)........................................................................1383
34.12.73 MMDC Duty Cycle Control Register (MMDC_MPDCCR)....................................................................... 1384
Chapter 35
MMDC ECC and Debug Watchpoint (MEW)
35.1 Chip-specific MEW information.................................................................................................................................. 1387
35.2 Introduction...................................................................................................................................................................1387
35.3 Features.........................................................................................................................................................................1387
35.4 Block Diagram..............................................................................................................................................................1389
35.5 Memory Map................................................................................................................................................................ 1390
35.5.1 AXI ECC Global Control Register (MEW_AXI_ECC_GLBL_CTRL)..................................................... 1392
35.5.2 AXI ECC Maximum ECC protected address register (MEW_AXI_ECC_MX_EPA)............................... 1393
35.5.3 AXI ECC Minimum ECC protected address register (MEW_AXI_ECC_MN_EPA)................................1393
35.5.4 AXI ECC Lock Pattern Register (MEW_AXI_ECC_LK_PTN).................................................................1393
35.5.5 AXI ECC Unlock Pattern Register (MEW_AXI_ECC_ULK_PTN).......................................................... 1394
35.5.6 ECC Error Report Address Register (MEW_AXI_ECC_EERAR).............................................................1395
35.5.7 AXI ECC Error Report Data and Syndrome Register (MEW_AXI_ECC_EERDSRn)..............................1395
35.5.8 AXI ECC error interrupt enable (MEW_AXI_ECC_ERR_IE)...................................................................1396
35.5.9 AXI ECC error Interupt status and clear register (MEW_AXI_ECC_ERR_IN_STCLR)..........................1398
35.5.10 AXI EDC Error interrupt enable register (MEW_AXI_EDC_ERR_IE).....................................................1400
35.5.11 AXI EDC Error Interrupt Status and Clear register (MEW_AXI_EDC_ERR_IN_STCLR)......................1402
35.5.12 Shadow Control, RW path Status and Status Clear Register (MEW_AXI_ECC_SHD_STAT_CTRL).... 1403
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35.5.13 Correctable and un-correctable bit error counter (MEW_AXI_ECC_CBL_UNCBL_BIT_EC)................1406
35.5.14 Correctable and un-correctable beat error counter (MEW_AXI_ECC_CBL_UCBL_BEAT_EC)............ 1408
35.5.15 Debug and Debug Control Register (MEW_AXI_ECC_DBG_CTRL)...................................................... 1409
35.6 ECC(Error Correcting Code)........................................................................................................................................ 1410
35.6.1 ECC Features............................................................................................................................................... 1410
35.6.2 Hamming code for SEC-DED-TED............................................................................................................ 1410
35.6.3 ECC encoder................................................................................................................................................ 1413
35.6.4 ECC decoder................................................................................................................................................ 1414
35.7 Error Injection Logic.....................................................................................................................................................1415
35.8 Steps to configure and use............................................................................................................................................ 1416
35.9 Limitations / Deviations from standard ....................................................................................................................... 1418
35.10 Watchpoint....................................................................................................................................................................1418
35.10.1 Introduction..................................................................................................................................................1418
35.10.2 Features........................................................................................................................................................ 1419
35.10.3 Detailed Description of Watchpoint............................................................................................................ 1419
Chapter 36
FlexTimer Module (FTM)
36.1 Chip-specific FTM information....................................................................................................................................1437
36.1.1 Configuration............................................................................................................................................... 1437
36.1.2 FTM Global Time Base............................................................................................................................... 1438
36.1.3 FTM Trigger implmentation........................................................................................................................ 1438
36.1.4 ENET-FTM connection............................................................................................................................... 1439
36.2 Introduction...................................................................................................................................................................1439
36.2.1 FlexTimer philosophy.................................................................................................................................. 1440
36.2.2 Features........................................................................................................................................................ 1441
36.2.3 Modes of operation...................................................................................................................................... 1442
36.2.4 Block diagram.............................................................................................................................................. 1442
36.3 FTM signal descriptions............................................................................................................................................... 1445
36.4 Memory map and register definition.............................................................................................................................1445
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36.4.1 Memory map................................................................................................................................................ 1445
36.4.2 Register descriptions.................................................................................................................................... 1446
36.4.3 Status And Control (FTM_SC).................................................................................................................... 1448
36.4.4 Counter (FTM_CNT)...................................................................................................................................1449
36.4.5 Modulo (FTM_MOD)..................................................................................................................................1450
36.4.6 Channel (n) Status And Control (FTM_CnSC)........................................................................................... 1451
36.4.7 Channel (n) Value (FTM_CnV)...................................................................................................................1454
36.4.8 Counter Initial Value (FTM_CNTIN)..........................................................................................................1454
36.4.9 Capture And Compare Status (FTM_STATUS)..........................................................................................1455
36.4.10 Features Mode Selection (FTM_MODE).................................................................................................... 1457
36.4.11 Synchronization (FTM_SYNC)...................................................................................................................1458
36.4.12 Initial State For Channels Output (FTM_OUTINIT).................................................................................. 1461
36.4.13 Output Mask (FTM_OUTMASK)............................................................................................................... 1462
36.4.14 Function For Linked Channels (FTM_COMBINE).................................................................................... 1464
36.4.15 Deadtime Insertion Control (FTM_DEADTIME).......................................................................................1468
36.4.16 FTM External Trigger (FTM_EXTTRIG)...................................................................................................1469
36.4.17 Channels Polarity (FTM_POL)....................................................................................................................1471
36.4.18 Fault Mode Status (FTM_FMS).................................................................................................................. 1473
36.4.19 Input Capture Filter Control (FTM_FILTER)............................................................................................. 1474
36.4.20 Quadrature Decoder Control And Status (FTM_QDCTRL)....................................................................... 1475
36.4.21 Configuration (FTM_CONF).......................................................................................................................1477
36.4.22 Synchronization Configuration (FTM_SYNCONF)................................................................................... 1478
36.4.23 FTM Inverting Control (FTM_INVCTRL)................................................................................................. 1480
36.4.24 FTM Software Output Control (FTM_SWOCTRL)....................................................................................1481
36.4.25 FTM PWM Load (FTM_PWMLOAD)....................................................................................................... 1484
36.5 Functional description...................................................................................................................................................1485
36.5.1 Clock source.................................................................................................................................................1486
36.5.2 Prescaler....................................................................................................................................................... 1486
36.5.3 Counter.........................................................................................................................................................1487
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36.5.4 Input Capture mode......................................................................................................................................1493
36.5.5 Output Compare mode................................................................................................................................. 1497
36.5.6 Edge-Aligned PWM (EPWM) mode........................................................................................................... 1498
36.5.7 Center-Aligned PWM (CPWM) mode........................................................................................................ 1500
36.5.8 Combine mode............................................................................................................................................. 1502
36.5.9 Complementary mode.................................................................................................................................. 1509
36.5.10 Registers updated from write buffers...........................................................................................................1510
36.5.11 PWM synchronization..................................................................................................................................1512
36.5.12 Inverting....................................................................................................................................................... 1528
36.5.13 Software output control................................................................................................................................1529
36.5.14 Deadtime insertion....................................................................................................................................... 1531
36.5.15 Output mask................................................................................................................................................. 1534
36.5.16 Polarity control.............................................................................................................................................1534
36.5.17 Initialization................................................................................................................................................. 1535
36.5.18 Features priority........................................................................................................................................... 1535
36.5.19 Channel trigger output................................................................................................................................. 1536
36.5.20 Initialization trigger......................................................................................................................................1538
36.5.21 Capture Test mode....................................................................................................................................... 1540
36.5.22 DMA............................................................................................................................................................ 1541
36.5.23 Dual Edge Capture mode............................................................................................................................. 1542
36.5.24 Quadrature Decoder mode........................................................................................................................... 1549
36.5.25 BDM mode...................................................................................................................................................1554
36.5.26 Intermediate load..........................................................................................................................................1555
36.5.27 Global time base (GTB)...............................................................................................................................1557
36.6 Reset overview..............................................................................................................................................................1558
36.7 FTM Interrupts..............................................................................................................................................................1560
36.7.1 Timer Overflow Interrupt.............................................................................................................................1560
36.7.2 Channel (n) Interrupt....................................................................................................................................1560
36.8 Initialization Procedure.................................................................................................................................................1560
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Chapter 37
Periodic Interrupt Timer (PIT)
37.1 Chip-specific PIT information...................................................................................................................................... 1563
37.1.1 Overview......................................................................................................................................................1563
37.1.2 Configuration............................................................................................................................................... 1563
37.1.3 PIT Channel Assignment............................................................................................................................. 1563
37.1.4 PIT instances register differences................................................................................................................ 1564
37.2 Introduction...................................................................................................................................................................1564
37.2.1 Block diagram.............................................................................................................................................. 1564
37.2.2 Features........................................................................................................................................................ 1565
37.3 Signal description..........................................................................................................................................................1565
37.4 Memory map/register description.................................................................................................................................1566
37.4.1 PIT Module Control Register (PIT_MCR).................................................................................................. 1567
37.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)............................................................................... 1568
37.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)............................................................................... 1568
37.4.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................1569
37.4.5 Current Timer Value Register (PIT_CVALn)............................................................................................. 1569
37.4.6 Timer Control Register (PIT_TCTRLn)...................................................................................................... 1570
37.4.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................1571
37.5 Functional description...................................................................................................................................................1572
37.5.1 General operation.........................................................................................................................................1572
37.5.2 Interrupts...................................................................................................................................................... 1574
37.5.3 Chained timers............................................................................................................................................. 1574
37.6 Initialization and application information.....................................................................................................................1574
37.7 Example configuration for chained timers....................................................................................................................1575
37.8 Example configuration for the lifetime timer............................................................................................................... 1576
Chapter 38
Software Watchdog Timer (SWT)
38.1 Chip-specific SWT information....................................................................................................................................1577
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38.1.1 SWT chip specific information.................................................................................................................... 1577
38.2 Introduction...................................................................................................................................................................1578
38.2.1 Overview......................................................................................................................................................1578
38.2.2 Features........................................................................................................................................................ 1578
38.2.3 Modes of operation...................................................................................................................................... 1578
38.3 External signal description............................................................................................................................................1579
38.4 Memory Map and Registers..........................................................................................................................................1579
38.4.1 SWT Control Register (SWT_CR).............................................................................................................. 1580
38.4.2 SWT Interrupt Register (SWT_IR)..............................................................................................................1583
38.4.3 SWT Time-out Register (SWT_TO)............................................................................................................1584
38.4.4 SWT Window Register (SWT_WN)........................................................................................................... 1584
38.4.5 SWT Service Register (SWT_SR)...............................................................................................................1585
38.4.6 SWT Counter Output Register (SWT_CO)................................................................................................. 1585
38.4.7 SWT Service Key Register (SWT_SK)....................................................................................................... 1586
38.5 Functional description...................................................................................................................................................1586
38.5.1 Introduction..................................................................................................................................................1586
38.5.2 Configuration locking.................................................................................................................................. 1588
38.5.3 Unlock sequence.......................................................................................................................................... 1588
38.5.4 Servicing operations.....................................................................................................................................1588
38.5.5 Time-out.......................................................................................................................................................1590
38.5.6 Initialization................................................................................................................................................. 1590
Chapter 39
System Timer Module (STM)
39.1 Chip-specific STM information....................................................................................................................................1591
39.1.1 STM Instances..............................................................................................................................................1591
39.2 Introduction...................................................................................................................................................................1591
39.2.1 Overview......................................................................................................................................................1591
39.2.2 Features........................................................................................................................................................ 1591
39.2.3 Modes of operation...................................................................................................................................... 1592
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39.3 External signal description............................................................................................................................................1592
39.4 Memory map and registers............................................................................................................................................1592
39.4.1 STM Control Register (STM_CR)...............................................................................................................1593
39.4.2 STM Count Register (STM_CNT).............................................................................................................. 1594
39.4.3 STM Channel Control Register (STM_CCRn)............................................................................................1594
39.4.4 STM Channel Interrupt Register (STM_CIRn)........................................................................................... 1595
39.4.5 STM Channel Compare Register (STM_CMPn).........................................................................................1596
39.5 Functional description...................................................................................................................................................1596
Chapter 40
Controller Area Network (FlexCAN)
40.1 Chip-specific FlexCAN information.............................................................................................................................1597
40.1.1 FlexCAN Configurations............................................................................................................................. 1597
40.1.2 Requirements for entering FlexCAN modes: Freeze, Module Disable, Stop..............................................1598
40.2 Introduction...................................................................................................................................................................1599
40.2.1 Overview......................................................................................................................................................1600
40.2.2 FlexCAN module features........................................................................................................................... 1601
40.2.3 Modes of operation...................................................................................................................................... 1603
40.3 FlexCAN signal descriptions........................................................................................................................................ 1605
40.3.1 CAN Rx .......................................................................................................................................................1605
40.3.2 CAN Tx .......................................................................................................................................................1605
40.4 Memory map/register definition................................................................................................................................... 1605
40.4.1 FlexCAN memory mapping.........................................................................................................................1605
40.4.2 Module Configuration Register (CAN_MCR)............................................................................................ 1612
40.4.3 Control 1 register (CAN_CTRL1)............................................................................................................... 1616
40.4.4 Free Running Timer (CAN_TIMER).......................................................................................................... 1620
40.4.5 Rx Mailboxes Global Mask Register (CAN_RXMGMASK)..................................................................... 1621
40.4.6 Rx 14 Mask register (CAN_RX14MASK)..................................................................................................1623
40.4.7 Rx 15 Mask register (CAN_RX15MASK)..................................................................................................1623
40.4.8 Error Counter (CAN_ECR)......................................................................................................................... 1624
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40.4.9 Error and Status 1 register (CAN_ESR1).................................................................................................... 1626
40.4.10 Interrupt Masks 2 register (CAN_IMASK2)............................................................................................... 1632
40.4.11 Interrupt Masks 1 register (CAN_IMASK1)............................................................................................... 1633
40.4.12 Interrupt Flags 2 register (CAN_IFLAG2).................................................................................................. 1633
40.4.13 Interrupt Flags 1 register (CAN_IFLAG1).................................................................................................. 1634
40.4.14 Control 2 register (CAN_CTRL2)............................................................................................................... 1637
40.4.15 Error and Status 2 register (CAN_ESR2).................................................................................................... 1641
40.4.16 CRC Register (CAN_CRCR).......................................................................................................................1642
40.4.17 Rx FIFO Global Mask register (CAN_RXFGMASK)................................................................................ 1643
40.4.18 Rx FIFO Information Register (CAN_RXFIR)........................................................................................... 1644
40.4.19 CAN Bit Timing Register (CAN_CBT)...................................................................................................... 1645
40.4.20 Rx Individual Mask Registers (CAN_RXIMRn).........................................................................................1647
40.4.21 Memory Error Control Register (CAN_MECR)......................................................................................... 1648
40.4.22 Error Injection Address Register (CAN_ERRIAR).....................................................................................1650
40.4.23 Error Injection Data Pattern Register (CAN_ERRIDPR)............................................................................1652
40.4.24 Error Injection Parity Pattern Register (CAN_ERRIPPR).......................................................................... 1652
40.4.25 Error Report Address Register (CAN_RERRAR).......................................................................................1653
40.4.26 Error Report Data Register (CAN_RERRDR)............................................................................................ 1654
40.4.27 Error Report Syndrome Register (CAN_RERRSYNR).............................................................................. 1655
40.4.28 Error Status Register (CAN_ERRSR)......................................................................................................... 1657
40.4.29 CAN FD Control Register (CAN_FDCTRL).............................................................................................. 1658
40.4.30 CAN FD Bit Timing Register (CAN_FDCBT)........................................................................................... 1662
40.4.31 CAN FD CRC Register (CAN_FDCRC).....................................................................................................1664
40.4.32 Message buffer structure..............................................................................................................................1666
40.4.33 FlexCAN Memory Partition for CAN FD................................................................................................... 1672
40.4.34 FlexCAN message buffer memory map.......................................................................................................1673
40.4.35 Rx FIFO structure........................................................................................................................................ 1678
40.5 Functional description...................................................................................................................................................1680
40.5.1 Transmit process.......................................................................................................................................... 1681
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40.5.2 Arbitration process.......................................................................................................................................1682
40.5.3 Receive process............................................................................................................................................1686
40.5.4 Matching process......................................................................................................................................... 1688
40.5.5 Move process............................................................................................................................................... 1693
40.5.6 Data coherence.............................................................................................................................................1695
40.5.7 Rx FIFO....................................................................................................................................................... 1698
40.5.8 CAN protocol related features..................................................................................................................... 1701
40.5.9 Clock domains and restrictions.................................................................................................................... 1722
40.5.10 Modes of operation details...........................................................................................................................1727
40.5.11 Interrupts...................................................................................................................................................... 1729
40.5.12 Bus interface................................................................................................................................................ 1731
40.5.13 Detection and Correction of Memory Errors............................................................................................... 1731
40.6 Initialization/application information........................................................................................................................... 1736
40.6.1 FlexCAN initialization sequence................................................................................................................. 1736
Chapter 41
Inter-Integrated Circuit (I2C)
41.1 Chip specific I2C information...................................................................................................................................... 1739
41.1.1 I2C Instances................................................................................................................................................1739
41.1.2 I2C Clocking................................................................................................................................................ 1739
41.2 Overview.......................................................................................................................................................................1739
41.3 Introduction to I2C........................................................................................................................................................1740
41.3.1 Definition: I2C module................................................................................................................................ 1740
41.3.2 Advantages of the I2C bus........................................................................................................................... 1740
41.3.3 Module block diagram................................................................................................................................. 1740
41.3.4 Features........................................................................................................................................................ 1741
41.3.5 Modes of operation...................................................................................................................................... 1742
41.3.6 Definition: I2C conditions........................................................................................................................... 1743
41.4 External signal descriptions.......................................................................................................................................... 1744
41.4.1 Signal overview............................................................................................................................................1744
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41.4.2 Detailed external signal descriptions........................................................................................................... 1744
41.5 Memory map and register definition.............................................................................................................................1744
41.5.1 Register accessibility....................................................................................................................................1745
41.5.2 Register figure conventions......................................................................................................................... 1745
41.5.3 I2C Bus Address Register (I2C_IBAD).......................................................................................................1746
41.5.4 I2C Bus Frequency Divider Register (I2C_IBFD)...................................................................................... 1747
41.5.5 I2C Bus Control Register (I2C_IBCR)........................................................................................................1747
41.5.6 I2C Bus Status Register (I2C_IBSR)...........................................................................................................1749
41.5.7 I2C Bus Data I/O Register (I2C_IBDR)...................................................................................................... 1750
41.5.8 I2C Bus Interrupt Config Register (I2C_IBIC)........................................................................................... 1751
41.5.9 I2C Bus Debug Register (I2C_IBDBG)...................................................................................................... 1752
41.6 Functional description...................................................................................................................................................1753
41.6.1 Notes about module operation..................................................................................................................... 1753
41.6.2 Transactions................................................................................................................................................. 1754
41.6.3 Arbitration procedure...................................................................................................................................1758
41.6.4 Clock behavior............................................................................................................................................. 1758
41.6.5 Interrupts...................................................................................................................................................... 1772
41.6.6 STOP mode.................................................................................................................................................. 1773
41.6.7 DEBUG mode.............................................................................................................................................. 1773
41.6.8 DMA interface............................................................................................................................................. 1775
41.7 Initialization/application information........................................................................................................................... 1776
41.7.1 Recommended interrupt service flow.......................................................................................................... 1776
41.7.2 General programming guidelines (for both master and slave mode)...........................................................1777
41.7.3 Programming guidelines specific to master mode....................................................................................... 1779
41.7.4 Programming guidelines specific to slave mode..........................................................................................1783
41.7.5 DMA application information......................................................................................................................1783
Chapter 42
Serial Peripheral Interface (SPI)
42.1 Chip-specific SPI information...................................................................................................................................... 1791
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42.2 SPI Clocking................................................................................................................................................................. 1791
42.3 Introduction...................................................................................................................................................................1791
42.3.1 Block Diagram............................................................................................................................................. 1791
42.3.2 Features........................................................................................................................................................ 1792
42.3.3 Interface configurations............................................................................................................................... 1794
42.3.4 Modes of Operation..................................................................................................................................... 1795
42.4 Module signal descriptions........................................................................................................................................... 1797
42.4.1 PCS0/SS—Peripheral Chip Select/Slave Select.......................................................................................... 1797
42.4.2 PCS1–PCS3—Peripheral Chip Selects 1–3.................................................................................................1797
42.4.3 PCS4—Peripheral Chip Select 4..................................................................................................................1797
42.4.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................1798
42.4.5 PCS6–PCS7—Peripheral Chip Selects 6–7.................................................................................................1798
42.4.6 SCK—Serial Clock...................................................................................................................................... 1798
42.4.7 SIN—Serial Input........................................................................................................................................ 1798
42.4.8 SOUT—Serial Output..................................................................................................................................1799
42.5 Memory Map/Register Definition.................................................................................................................................1799
42.5.1 Module Configuration Register (SPI_MCR)............................................................................................... 1801
42.5.2 Transfer Count Register (SPI_TCR)............................................................................................................1805
42.5.3 Clock and Transfer Attributes Register (In Master Mode) (SPI_CTARn)..................................................1805
42.5.4 Clock and Transfer Attributes Register (In Slave Mode) (SPI_CTARn_SLAVE)..................................... 1810
42.5.5 Status Register (SPI_SR)............................................................................................................................. 1812
42.5.6 DMA/Interrupt Request Select and Enable Register (SPI_RSER)..............................................................1815
42.5.7 PUSH TX FIFO Register In Master Mode (SPI_PUSHR).......................................................................... 1818
42.5.8 PUSH TX FIFO Register In Slave Mode (SPI_PUSHR_SLAVE)............................................................. 1820
42.5.9 POP RX FIFO Register (SPI_POPR).......................................................................................................... 1821
42.5.10 Transmit FIFO Registers (SPI_TXFRn)...................................................................................................... 1821
42.5.11 Receive FIFO Registers (SPI_RXFRn)....................................................................................................... 1822
42.5.12 Clock and Transfer Attributes Register Extended (SPI_CTAREn).............................................................1822
42.5.13 Status Register Extended (SPI_SREX)........................................................................................................1824
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42.6 Functional description...................................................................................................................................................1825
42.6.1 Start and Stop of module transfers...............................................................................................................1826
42.6.2 Serial Peripheral Interface SPI configuration.............................................................................................. 1827
42.6.3 Module baud rate and clock delay generation............................................................................................. 1832
42.6.4 Transfer formats...........................................................................................................................................1835
42.6.5 Continuous Serial Communications Clock.................................................................................................. 1846
42.6.6 Slave Mode Operation Constraints.............................................................................................................. 1848
42.6.7 Parity Generation and Check....................................................................................................................... 1848
42.6.8 Interrupts/DMA requests..............................................................................................................................1849
42.6.9 Power saving features.................................................................................................................................. 1853
42.7 Initialization/application information........................................................................................................................... 1854
42.7.1 How to manage queues................................................................................................................................ 1854
42.7.2 Switching Master and Slave mode...............................................................................................................1855
42.7.3 Initializing Module in Master/Slave Modes.................................................................................................1855
42.7.4 Baud rate settings......................................................................................................................................... 1855
42.7.5 Delay settings...............................................................................................................................................1856
42.7.6 Calculation of FIFO pointer addresses.........................................................................................................1857
Chapter 43
10/100/1000-Mbps Ethernet MAC (ENET)
43.1 Chip-specific ENET information..................................................................................................................................1861
43.2 Programming ENET_MSCR[HOLDTIME].................................................................................................................1862
43.3 Selecting RMII or RGMII mode...................................................................................................................................1862
43.4 Recieve Parser Match Array Table Depth.................................................................................................................... 1862
43.5 Timer Slave mode.........................................................................................................................................................1862
43.6 Introduction...................................................................................................................................................................1863
43.7 Overview.......................................................................................................................................................................1863
43.7.1 Features........................................................................................................................................................ 1863
43.7.2 Block diagram.............................................................................................................................................. 1866
43.8 External signal description............................................................................................................................................1867
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43.9 Memory map/register definition................................................................................................................................... 1870
43.9.1 Interrupt Event Register (ENET_EIR).........................................................................................................1877
43.9.2 Interrupt Mask Register (ENET_EIMR)......................................................................................................1881
43.9.3 Receive Descriptor Active Register - Ring 0 (ENET_RDAR)....................................................................1885
43.9.4 Transmit Descriptor Active Register - Ring 0 (ENET_TDAR).................................................................. 1885
43.9.5 Ethernet Control Register (ENET_ECR).....................................................................................................1887
43.9.6 MII Management Frame Register (ENET_MMFR).................................................................................... 1889
43.9.7 MII Speed Control Register (ENET_MSCR).............................................................................................. 1890
43.9.8 MIB Control Register (ENET_MIBC)........................................................................................................ 1892
43.9.9 Receive Control Register (ENET_RCR)..................................................................................................... 1893
43.9.10 Transmit Control Register (ENET_TCR).................................................................................................... 1896
43.9.11 Physical Address Lower Register (ENET_PALR)...................................................................................... 1898
43.9.12 Physical Address Upper Register (ENET_PAUR)...................................................................................... 1898
43.9.13 Opcode/Pause Duration Register (ENET_OPD)......................................................................................... 1899
43.9.14 Transmit Interrupt Coalescing Register (ENET_TXICn)............................................................................1899
43.9.15 Receive Interrupt Coalescing Register (ENET_RXICn)............................................................................. 1900
43.9.16 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................. 1901
43.9.17 Descriptor Individual Lower Address Register (ENET_IALR).................................................................. 1902
43.9.18 Descriptor Group Upper Address Register (ENET_GAUR).......................................................................1902
43.9.19 Descriptor Group Lower Address Register (ENET_GALR).......................................................................1903
43.9.20 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................. 1903
43.9.21 Receive Descriptor Ring 1 Start Register (ENET_RDSR1)........................................................................1904
43.9.22 Transmit Buffer Descriptor Ring 1 Start Register (ENET_TDSR1)........................................................... 1905
43.9.23 Maximum Receive Buffer Size Register - Ring 1 (ENET_MRBR1)..........................................................1906
43.9.24 Receive Descriptor Ring 2 Start Register (ENET_RDSR2)........................................................................1907
43.9.25 Transmit Buffer Descriptor Ring 2 Start Register (ENET_TDSR2)........................................................... 1907
43.9.26 Maximum Receive Buffer Size Register - Ring 2 (ENET_MRBR2)..........................................................1908
43.9.27 Receive Descriptor Ring 0 Start Register (ENET_RDSR)..........................................................................1909
43.9.28 Transmit Buffer Descriptor Ring 0 Start Register (ENET_TDSR)............................................................. 1910
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43.9.29 Maximum Receive Buffer Size Register - Ring 0 (ENET_MRBR)............................................................1910
43.9.30 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................ 1911
43.9.31 Receive FIFO Section Empty Threshold (ENET_RSEM).......................................................................... 1912
43.9.32 Receive FIFO Almost Empty Threshold (ENET_RAEM).......................................................................... 1912
43.9.33 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1913
43.9.34 Transmit FIFO Section Empty Threshold (ENET_TSEM)......................................................................... 1913
43.9.35 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1914
43.9.36 Transmit FIFO Almost Full Threshold (ENET_TAFL).............................................................................. 1914
43.9.37 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................. 1915
43.9.38 Frame Truncation Length (ENET_FTRL)...................................................................................................1915
43.9.39 Transmit Accelerator Function Configuration (ENET_TACC).................................................................. 1916
43.9.40 Receive Accelerator Function Configuration (ENET_RACC)....................................................................1917
43.9.41 Receive Classification Match Register for Class n (ENET_RCMRn)........................................................ 1918
43.9.42 DMA Class Based Configuration (ENET_DMAnCFG)............................................................................. 1919
43.9.43 Receive Descriptor Active Register - Ring 1 (ENET_RDAR1)..................................................................1921
43.9.44 Transmit Descriptor Active Register - Ring 1 (ENET_TDAR1)................................................................ 1922
43.9.45 Receive Descriptor Active Register - Ring 2 (ENET_RDAR2)..................................................................1923
43.9.46 Transmit Descriptor Active Register - Ring 2 (ENET_TDAR2)................................................................ 1924
43.9.47 QOS Scheme (ENET_QOS)........................................................................................................................ 1924
43.9.48 Reserved Statistic Register (ENET_RMON_T_DROP)..............................................................................1926
43.9.49 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS).......................................................... 1926
43.9.50 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)......................................................1927
43.9.51 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)......................................................1927
43.9.52 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN).......................... 1928
43.9.53 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)..........1928
43.9.54 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)........1928
43.9.55 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG)...................1929
43.9.56 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)...... 1929
43.9.57 Tx Collision Count Statistic Register (ENET_RMON_T_COL)................................................................ 1930
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43.9.58 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................. 1930
43.9.59 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127).......................................... 1930
43.9.60 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)...................................... 1931
43.9.61 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)...................................... 1931
43.9.62 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................. 1932
43.9.63 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047).............................. 1932
43.9.64 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048)........................ 1933
43.9.65 Tx Octets Statistic Register (ENET_RMON_T_OCTETS)........................................................................ 1933
43.9.66 Reserved Statistic Register (ENET_IEEE_T_DROP).................................................................................1933
43.9.67 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK).............................................. 1934
43.9.68 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................. 1934
43.9.69 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).......................1935
43.9.70 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)..................................1935
43.9.71 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL)................................ 1935
43.9.72 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL)...................1936
43.9.73 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)..................1936
43.9.74 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)..................... 1937
43.9.75 Reserved Statistic Register (ENET_IEEE_T_SQE).................................................................................... 1937
43.9.76 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC).............................1937
43.9.77 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK).........1938
43.9.78 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS).......................................................... 1938
43.9.79 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)..................................................... 1939
43.9.80 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)..................................................... 1939
43.9.81 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)..........................1939
43.9.82 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)..............................................................................................................1940
43.9.83 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE).1940
43.9.84 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................. 1941
43.9.85 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)..... 1941
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43.9.86 Reserved Statistic Register (ENET_RMON_R_RESVD_0).......................................................................1941
43.9.87 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64).................................................................1942
43.9.88 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)......................................... 1942
43.9.89 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)..................................... 1943
43.9.90 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)..................................... 1943
43.9.91 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................. 1943
43.9.92 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................. 1944
43.9.93 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)......................... 1944
43.9.94 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)........................................................................1945
43.9.95 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)............................................... 1945
43.9.96 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................. 1945
43.9.97 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC)............................................ 1946
43.9.98 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN).............................. 1946
43.9.99 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)........................................1947
43.9.100 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC).................................1947
43.9.101 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).......1947
43.9.102 Adjustable Timer Control Register (ENET_ATCR)................................................................................... 1948
43.9.103 Timer Value Register (ENET_ATVR)........................................................................................................ 1950
43.9.104 Timer Offset Register (ENET_ATOFF)...................................................................................................... 1950
43.9.105 Timer Period Register (ENET_ATPER)......................................................................................................1951
43.9.106 Timer Correction Register (ENET_ATCOR).............................................................................................. 1951
43.9.107 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................ 1952
43.9.108 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................ 1952
43.9.109 Pattern Match Data Register (ENET_MDATA)..........................................................................................1953
43.9.110 Match Entry Mask Register (ENET_MMASK).......................................................................................... 1953
43.9.111 Match Entry Rules Configuration Register (ENET_MCONFIG)............................................................... 1954
43.9.112 Match Entry Read/Write Command Register (ENET_MENTRYRW).......................................................1955
43.9.113 Receive Parser Control Register (ENET_RXPCTL)................................................................................... 1956
43.9.114 Maximum Frame Offset (ENET_MAXFRMOFF)......................................................................................1957
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43.9.115 Receive Parser Status (ENET_RXPARST)................................................................................................. 1958
43.9.116 Parser Discard Count (ENET_PARSDSCD)...............................................................................................1959
43.9.117 Parser Accept Count 0 (ENET_PRSACPT0).............................................................................................. 1960
43.9.118 Parser Reject Count 0 (ENET_PRSRJCT0)................................................................................................ 1960
43.9.119 Parser Accept Count 1 (ENET_PRSACPT1).............................................................................................. 1961
43.9.120 Parser Reject Count 1 (ENET_PRSRJCT1)................................................................................................ 1961
43.9.121 Parser Accept Count 2 (ENET_PRSACPT2).............................................................................................. 1962
43.9.122 Parser Reject Count 2 (ENET_PRSRJCT2)................................................................................................ 1962
43.9.123 Timer Global Status Register (ENET_TGSR).............................................................................................1963
43.9.124 Timer Control Status Register (ENET_TCSRn)..........................................................................................1964
43.9.125 Timer Compare Capture Register (ENET_TCCRn)....................................................................................1965
43.10 Functional description...................................................................................................................................................1966
43.10.1 Ethernet MAC frame formats...................................................................................................................... 1966
43.10.2 IP and higher layers frame format................................................................................................................1969
43.10.3 IEEE 1588 message formats........................................................................................................................ 1973
43.10.4 MAC receive................................................................................................................................................ 1977
43.10.5 MAC transmit.............................................................................................................................................. 1986
43.10.6 Full-duplex flow control operation.............................................................................................................. 1992
43.10.7 Magic packet detection................................................................................................................................ 1994
43.10.8 IP accelerator functions................................................................................................................................1995
43.10.9 Resets and stop controls...............................................................................................................................1999
43.10.10 IEEE 1588 functions.................................................................................................................................... 2002
43.10.11 FIFO thresholds............................................................................................................................................2006
43.10.12 Loopback options.........................................................................................................................................2009
43.10.13 Legacy buffer descriptors.............................................................................................................................2010
43.10.14 Enhanced buffer descriptors.........................................................................................................................2011
43.10.15 Client FIFO application interface................................................................................................................ 2018
43.10.16 FIFO protection............................................................................................................................................2021
43.10.17 Reference clock............................................................................................................................................2023
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43.10.18 PHY management interface......................................................................................................................... 2023
43.10.19 Ethernet interfaces........................................................................................................................................2026
43.10.20 AVB configuration.......................................................................................................................................2031
43.10.21 Interrupt coalescence....................................................................................................................................2032
Chapter 44
ZIPWIRE
44.1 Chip-specific Zipwire Information............................................................................................................................... 2035
44.2 Overview.......................................................................................................................................................................2036
44.3 Introduction...................................................................................................................................................................2036
44.4 Zipwire Block Diagram................................................................................................................................................ 2036
44.5 Architecture...................................................................................................................................................................2037
44.6 Zipwire interconnections.............................................................................................................................................. 2038
44.7 Zipwire performance.....................................................................................................................................................2039
44.7.1 Read performance........................................................................................................................................ 2040
44.7.2 Write performance....................................................................................................................................... 2043
Chapter 45
LFAST
45.1 LFAST Chip-specific information................................................................................................................................2047
45.2 Introduction...................................................................................................................................................................2047
45.3 Block diagram ..............................................................................................................................................................2047
45.4 External signals.............................................................................................................................................................2048
45.4.1 LFAST operating data rates......................................................................................................................... 2048
45.5 LFAST frame structure.................................................................................................................................................2049
45.6 Features.........................................................................................................................................................................2052
45.7 Memory map and register definition.............................................................................................................................2053
45.7.1 LFAST Mode Configuration Register (LFAST_MCR)...............................................................................2055
45.7.2 LFAST Speed Control Register (LFAST_SCR)..........................................................................................2057
45.7.3 LFAST Correlator Control Register (LFAST_COCR)................................................................................2058
45.7.4 LFAST Test Mode Control Register (LFAST_TMCR).............................................................................. 2060
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45.7.5 LFAST Auto Loopback Control Register (LFAST_ALCR)....................................................................... 2061
45.7.6 LFAST Rate Change Delay Control Register (LFAST_RCDCR).............................................................. 2062
45.7.7 LFAST Wakeup Delay Control Register (LFAST_SLCR)......................................................................... 2062
45.7.8 LFAST ICLC Control Register (LFAST_ICR)........................................................................................... 2064
45.7.9 LFAST Ping Control Register (LFAST_PICR)...........................................................................................2065
45.7.10 LFAST Rx FIFO CTS Control Register (LFAST_RFCR).......................................................................... 2066
45.7.11 LFAST Tx Interrupt Enable Register (LFAST_TIER)................................................................................2066
45.7.12 LFAST Rx Interrupt Enable Register (LFAST_RIER)............................................................................... 2067
45.7.13 LFAST Rx ICLC Interrupt Enable Register (LFAST_RIIER)....................................................................2069
45.7.14 LFAST PLL Control Register (LFAST_PLLCR)....................................................................................... 2071
45.7.15 LFAST LVDS Control Register (LFAST_LCR).........................................................................................2073
45.7.16 LFAST Unsolicited Tx Control Register (LFAST_UNSTCR)................................................................... 2075
45.7.17 LFAST Unsolicited Tx Data Registers (LFAST_UNSTDRn).................................................................... 2076
45.7.18 LFAST Global Status Register (LFAST_GSR)...........................................................................................2077
45.7.19 LFAST Ping Status Register (LFAST_PISR)..............................................................................................2078
45.7.20 LFAST Data Frame Status Register (LFAST_DFSR).................................................................................2079
45.7.21 LFAST Tx Interrupt Status Register (LFAST_TISR)................................................................................. 2080
45.7.22 LFAST Rx Interrupt Status Register (LFAST_RISR).................................................................................2081
45.7.23 LFAST Rx ICLC Interrupt Status Register (LFAST_RIISR)..................................................................... 2083
45.7.24 LFAST PLL and LVDS Status Register (LFAST_PLLLSR)......................................................................2085
45.7.25 LFAST Unsolicited Rx Status Register (LFAST_UNSRSR)......................................................................2086
45.7.26 LFAST Unsolicited Rx Data Register (LFAST_UNSRDRn)..................................................................... 2087
45.8 Functional description...................................................................................................................................................2087
45.8.1 Startup procedure......................................................................................................................................... 2087
45.8.2 Line Receiver............................................................................................................................................... 2090
45.8.3 Transmit Controller......................................................................................................................................2099
45.8.4 CTS mode support....................................................................................................................................... 2104
45.8.5 Frames supported......................................................................................................................................... 2105
45.8.6 Frame flow................................................................................................................................................... 2106
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45.8.7 Test and Debug Support...............................................................................................................................2113
45.8.8 Interrupts...................................................................................................................................................... 2122
45.9 Packet memory..............................................................................................................................................................2125
45.10 Resets............................................................................................................................................................................ 2126
45.11 Clocks........................................................................................................................................................................... 2127
45.11.1 Clocking strategy......................................................................................................................................... 2127
45.11.2 Slow speed clock..........................................................................................................................................2128
45.11.3 Rx Controller Clocks................................................................................................................................... 2131
45.11.4 Clocking Module Requirements for High Speed Phases............................................................................. 2131
45.11.5 Clock module requirements for low speed phases.......................................................................................2132
45.11.6 Tx Controller Clocks....................................................................................................................................2133
45.12 PLL configuration example.......................................................................................................................................... 2134
Chapter 46
Serial Interprocessor Interface (SIPI)
46.1 Serial Interprocessor Interface (SIPI) Device ID..........................................................................................................2135
46.2 Introduction...................................................................................................................................................................2135
46.2.1 Scalability.....................................................................................................................................................2135
46.3 Overview.......................................................................................................................................................................2136
46.4 SIPI block diagram....................................................................................................................................................... 2138
46.5 Feature description........................................................................................................................................................2138
46.5.1 Main features................................................................................................................................................2138
46.5.2 Standard features..........................................................................................................................................2139
46.6 SIPI operation from reset..............................................................................................................................................2139
46.7 Functional description...................................................................................................................................................2139
46.7.1 External signals............................................................................................................................................ 2139
46.7.2 Frame format................................................................................................................................................2140
46.8 Transfer types................................................................................................................................................................2146
46.8.1 Read transfer................................................................................................................................................ 2146
46.8.2 Register read answer transfer.......................................................................................................................2147
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46.8.3 Register Write transfer................................................................................................................................. 2148
46.8.4 Write Acknowledge transfer........................................................................................................................ 2151
46.8.5 ID request response......................................................................................................................................2151
46.9 Transfer API and flow charts........................................................................................................................................2153
46.10 DMA programming sequence.......................................................................................................................................2160
46.11 Modes of operation....................................................................................................................................................... 2161
46.11.1 Initialization mode....................................................................................................................................... 2161
46.11.2 Normal mode................................................................................................................................................2161
46.11.3 Module Disable (MD)..................................................................................................................................2161
46.12 Errors.............................................................................................................................................................................2162
46.12.1 Timeout error............................................................................................................................................... 2162
46.12.2 CRC error.....................................................................................................................................................2162
46.12.3 Maximum count reached error.....................................................................................................................2163
46.12.4 Transaction ID error.....................................................................................................................................2163
46.12.5 Acknowledge error.......................................................................................................................................2163
46.13 CRC calculation............................................................................................................................................................2163
46.14 Interrupt logic................................................................................................................................................................2164
46.15 SIPI control and status overview.................................................................................................................................. 2165
46.16 Memory map and register definition.............................................................................................................................2166
46.16.1 SIPI Channel Control Register 0 (SIPI_CCR0)...........................................................................................2169
46.16.2 SIPI Channel Status Register 0 (SIPI_CSR0)..............................................................................................2172
46.16.3 SIPI Channel Interrupt Register 0 (SIPI_CIR0).......................................................................................... 2173
46.16.4 SIPI Channel Timeout Register 0 (SIPI_CTOR0).......................................................................................2174
46.16.5 SIPI Channel CRC Register 0 (SIPI_CCRC0)............................................................................................ 2175
46.16.6 SIPI Channel Address Register 0 (SIPI_CAR0)..........................................................................................2175
46.16.7 SIPI Channel Data Register 0 (SIPI_CDR0)............................................................................................... 2176
46.16.8 SIPI Channel Control Register 1 (SIPI_CCR1)...........................................................................................2176
46.16.9 SIPI Channel Status Register 1 (SIPI_CSR1)..............................................................................................2179
46.16.10 SIPI Channel Interrupt Register 1 (SIPI_CIR1).......................................................................................... 2181
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46.16.11 SIPI Channel Timeout Register 1 (SIPI_CTOR1).......................................................................................2182
46.16.12 SIPI Channel CRC Register 1 (SIPI_CCRC1)............................................................................................ 2183
46.16.13 SIPI Channel Address Register 1 (SIPI_CAR1)..........................................................................................2183
46.16.14 SIPI Channel Data Register 1 (SIPI_CDR1)............................................................................................... 2184
46.16.15 SIPI Channel Control Register 2 (SIPI_CCR2)...........................................................................................2184
46.16.16 SIPI Channel Status Register 2 (SIPI_CSR2)..............................................................................................2187
46.16.17 SIPI Channel Interrupt Register 2 (SIPI_CIR2).......................................................................................... 2189
46.16.18 SIPI Channel Timeout Register 2 (SIPI_CTOR2).......................................................................................2190
46.16.19 SIPI Channel CRC Register 2 (SIPI_CCRC2)............................................................................................ 2191
46.16.20 SIPI Channel Address Register 2 (SIPI_CAR2)..........................................................................................2191
46.16.21 SIPI Channel Data Register 2 (SIPI_CDR2_n)........................................................................................... 2192
46.16.22 SIPI Channel Control Register 3 (SIPI_CCR3)...........................................................................................2192
46.16.23 SIPI Channel Status Register 3 (SIPI_CSR3)..............................................................................................2195
46.16.24 SIPI Channel Interrupt Register 3 (SIPI_CIR3).......................................................................................... 2197
46.16.25 SIPI Channel Timeout Register 3 (SIPI_CTOR3).......................................................................................2198
46.16.26 SIPI Channel CRC Register 3 (SIPI_CCRC3)............................................................................................ 2199
46.16.27 SIPI Channel Address Register 3 (SIPI_CAR3)..........................................................................................2199
46.16.28 SIPI Channel Data Register 3 (SIPI_CDR3)............................................................................................... 2200
46.16.29 SIPI Module Configuration Register (SIPI_MCR)......................................................................................2200
46.16.30 SIPI Status Register (SIPI_SR)....................................................................................................................2203
46.16.31 SIPI Max Count Register (SIPI_MAXCR)..................................................................................................2205
46.16.32 SIPI Address Reload Register (SIPI_ARR).................................................................................................2205
46.16.33 SIPI Address Count Register (SIPI_ACR).................................................................................................. 2206
46.16.34 SIPI Error Register (SIPI_ERR).................................................................................................................. 2207
Chapter 47
LINFlexD
47.1 Chip specific LinFlexD information.............................................................................................................................2211
47.1.1 LinFlexD Configurations............................................................................................................................. 2211
47.1.2 LIN_CLK and BUS clock relationship........................................................................................................2211
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47.2 Introduction...................................................................................................................................................................2212
47.2.1 Glossary and acronyms................................................................................................................................ 2212
47.2.2 References....................................................................................................................................................2212
47.3 Main features................................................................................................................................................................ 2214
47.3.1 LIN mode features....................................................................................................................................... 2214
47.3.2 UART mode features................................................................................................................................... 2215
47.4 Functional description...................................................................................................................................................2215
47.4.1 LIN protocol.................................................................................................................................................2215
47.4.2 LINFlexD features....................................................................................................................................... 2218
47.4.3 Timer............................................................................................................................................................2234
47.4.4 UART mode.................................................................................................................................................2235
47.4.5 DMA interface............................................................................................................................................. 2239
47.5 Memory map and register description.......................................................................................................................... 2258
47.5.1 LIN Control Register 1 (LINFlexD_LINCR1)............................................................................................ 2260
47.5.2 LIN Interrupt enable register (LINFlexD_LINIER).................................................................................... 2263
47.5.3 LIN Status Register (LINFlexD_LINSR).................................................................................................... 2265
47.5.4 LIN Error Status Register (LINFlexD_LINESR)........................................................................................ 2268
47.5.5 UART Mode Control Register (LINFlexD_UARTCR).............................................................................. 2270
47.5.6 UART Mode Status Register (LINFlexD_UARTSR)................................................................................. 2275
47.5.7 LIN Time-Out Control Status Register (LINFlexD_LINTCSR).................................................................2277
47.5.8 LIN Output Compare Register (LINFlexD_LINOCR)................................................................................2279
47.5.9 LIN Time-Out Control Register (LINFlexD_LINTOCR)........................................................................... 2280
47.5.10 LIN Fractional Baud Rate Register (LINFlexD_LINFBRR)...................................................................... 2280
47.5.11 LIN Integer Baud Rate Register (LINFlexD_LINIBRR)............................................................................ 2281
47.5.12 LIN Checksum Field Register (LINFlexD_LINCFR)................................................................................. 2282
47.5.13 LIN Control Register 2 (LINFlexD_LINCR2)............................................................................................ 2283
47.5.14 Buffer Identifier Register (LINFlexD_BIDR)............................................................................................. 2285
47.5.15 Buffer Data Register Least Significant (LINFlexD_BDRL)....................................................................... 2286
47.5.16 Buffer Data Register Most Significant (LINFlexD_BDRM)...................................................................... 2287
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47.5.17 Identifier Filter Enable Register (LINFlexD_IFER)....................................................................................2287
47.5.18 Identifier Filter Match Index (LINFlexD_IFMI)......................................................................................... 2288
47.5.19 Identifier Filter Mode Register (LINFlexD_IFMR).................................................................................... 2288
47.5.20 Identifier Filter Control Register (LINFlexD_IFCRn)................................................................................ 2289
47.5.21 Global Control Register (LINFlexD_GCR).................................................................................................2290
47.5.22 UART Preset Timeout Register (LINFlexD_UARTPTO).......................................................................... 2292
47.5.23 UART Current Timeout Register (LINFlexD_UARTCTO)....................................................................... 2293
47.5.24 DMA Tx Enable Register (LINFlexD_DMATXE)..................................................................................... 2294
47.5.25 DMA Rx Enable Register (LINFlexD_DMARXE).....................................................................................2294
47.6 Programming considerations........................................................................................................................................ 2295
47.6.1 Master node..................................................................................................................................................2295
47.6.2 Slave node.................................................................................................................................................... 2297
47.6.3 Timeout........................................................................................................................................................ 2302
47.6.4 UART mode.................................................................................................................................................2303
47.6.5 Interrupts...................................................................................................................................................... 2304
47.6.6 LINFlexD Clock Tolerance......................................................................................................................... 2305
Chapter 48
FlexRay Communication Controller (FlexRay)
48.1 Introduction...................................................................................................................................................................2307
48.1.1 Reference..................................................................................................................................................... 2307
48.1.2 Glossary....................................................................................................................................................... 2307
48.1.3 Overview......................................................................................................................................................2309
48.1.4 Features........................................................................................................................................................ 2310
48.1.5 Modes of operation...................................................................................................................................... 2312
48.2 External Signal Description.......................................................................................................................................... 2313
48.2.1 Detailed Signal Descriptions........................................................................................................................2314
48.3 Controller Host Interface Clocking...............................................................................................................................2315
48.4 Protocol Engine Clocking.............................................................................................................................................2315
48.4.1 Oscillator Clocking...................................................................................................................................... 2316
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48.4.2 PLL Clocking...............................................................................................................................................2316
48.5 Register Descriptions....................................................................................................................................................2316
48.5.1 Register Reset.............................................................................................................................................. 2317
48.5.2 Register Write Access..................................................................................................................................2317
48.6 Memory map and register definition.............................................................................................................................2319
48.6.1 Module Version Register (FR_MVR)..........................................................................................................2355
48.6.2 Module Configuration Register (FR_MCR)................................................................................................ 2355
48.6.3 System Memory Base Address High Register (FR_SYMBADHR)............................................................2358
48.6.4 System Memory Base Address Low Register (FR_SYMBADLR).............................................................2359
48.6.5 Strobe Signal Control Register (FR_STBSCR)........................................................................................... 2359
48.6.6 Message Buffer Data Size Register (FR_MBDSR).....................................................................................2361
48.6.7 Message Buffer Segment Size and Utilization Register (FR_MBSSUTR).................................................2362
48.6.8 PE DRAM Access Register (FR_PEDRAR)............................................................................................... 2363
48.6.9 PE DRAM Data Register (FR_PEDRDR)...................................................................................................2364
48.6.10 Protocol Operation Control Register (FR_POCR).......................................................................................2364
48.6.11 Global Interrupt Flag and Enable Register (FR_GIFER)............................................................................ 2366
48.6.12 Protocol Interrupt Flag Register 0 (FR_PIFR0)...........................................................................................2369
48.6.13 Protocol Interrupt Flag Register 1 (FR_PIFR1)...........................................................................................2371
48.6.14 Protocol Interrupt Enable Register 0 (FR_PIER0)...................................................................................... 2373
48.6.15 Protocol Interrupt Enable Register 1 (FR_PIER1)...................................................................................... 2375
48.6.16 CHI Error Flag Register (FR_CHIERFR)................................................................................................... 2376
48.6.17 Message Buffer Interrupt Vector Register (FR_MBIVEC).........................................................................2379
48.6.18 Channel A Status Error Counter Register (FR_CASERCR)....................................................................... 2380
48.6.19 Channel B Status Error Counter Register (FR_CBSERCR)........................................................................2380
48.6.20 Protocol Status Register 0 (FR_PSR0)........................................................................................................ 2381
48.6.21 Protocol Status Register 1 (FR_PSR1)........................................................................................................ 2383
48.6.22 Protocol Status Register 2 (FR_PSR2)........................................................................................................ 2384
48.6.23 Protocol Status Register 3 (FR_PSR3)........................................................................................................ 2386
48.6.24 Macrotick Counter Register (FR_MTCTR).................................................................................................2388
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48.6.25 Cycle Counter Register (FR_CYCTR)........................................................................................................ 2389
48.6.26 Slot Counter Channel A Register (FR_SLTCTAR).................................................................................... 2389
48.6.27 Slot Counter Channel B Register (FR_SLTCTBR).....................................................................................2390
48.6.28 Rate Correction Value Register (FR_RTCORVR)......................................................................................2390
48.6.29 Offset Correction Value Register (FR_OFCORVR)................................................................................... 2391
48.6.30 Combined Interrupt Flag Register (FR_CIFR)............................................................................................ 2392
48.6.31 System Memory Access Time-Out Register (FR_SYMATOR)..................................................................2393
48.6.32 Sync Frame Counter Register (FR_SFCNTR).............................................................................................2394
48.6.33 Sync Frame Table Offset Register (FR_SFTOR)........................................................................................ 2394
48.6.34 Sync Frame Table Configuration, Control, Status Register (FR_SFTCCSR).............................................2395
48.6.35 Sync Frame ID Rejection Filter Register (FR_SFIDRFR).......................................................................... 2397
48.6.36 Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)......................................................... 2397
48.6.37 Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)......................................................... 2398
48.6.38 Network Management Vector Register (FR_NMVRn)............................................................................... 2398
48.6.39 Network Management Vector Length Register (FR_NMVLR).................................................................. 2399
48.6.40 Timer Configuration and Control Register (FR_TICCR)............................................................................2399
48.6.41 Timer 1 Cycle Set Register (FR_TI1CYSR)............................................................................................... 2401
48.6.42 Timer 1 Macrotick Offset Register (FR_TI1MTOR).................................................................................. 2402
48.6.43 Timer 2 Configuration Register 0 (Absolute Timer Configuration) (FR_TI2CR0_ABS).......................... 2402
48.6.44 Timer 2 Configuration Register 0 (Relative Timer Configuration) (FR_TI2CR0_REL)............................2403
48.6.45 Timer 2 Configuration Register 1 (Absolute Timer Configuration) (FR_TI2CR1_ABS).......................... 2403
48.6.46 Timer 2 Configuration Register 1 (Relative Timer Configuration) (FR_TI2CR1_REL)............................2404
48.6.47 Slot Status Selection Register (FR_SSSR).................................................................................................. 2405
48.6.48 Slot Status Counter Condition Register (FR_SSCCR)................................................................................ 2406
48.6.49 Slot Status Register (FR_SSRn).................................................................................................................. 2408
48.6.50 Slot Status Counter Register (FR_SSCRn)..................................................................................................2410
48.6.51 MTS A Configuration Register (FR_MTSACFR).......................................................................................2410
48.6.52 MTS B Configuration Register (FR_MTSBCFR)....................................................................................... 2411
48.6.53 Receive Shadow Buffer Index Register (FR_RSBIR).................................................................................2412
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48.6.54 Receive FIFO Watermark and Selection Register (FR_RFWMSR)........................................................... 2413
48.6.55 Receive FIFO Start Index Register (FR_RFSIR)........................................................................................ 2414
48.6.56 Receive FIFO Depth and Size Register (FR_RFDSR)................................................................................ 2414
48.6.57 Receive FIFO A Read Index Register (FR_RFARIR).................................................................................2415
48.6.58 Receive FIFO B Read Index Register (FR_RFBRIR)................................................................................. 2415
48.6.59 Receive FIFO Message ID Acceptance Filter Value Register (FR_RFMIDAFVR)...................................2416
48.6.60 Receive FIFO Message ID Acceptance Filter Mask Register (FR_RFMIDAFMR)...................................2416
48.6.61 Receive FIFO Frame ID Rejection Filter Value Register (FR_RFFIDRFVR)........................................... 2417
48.6.62 Receive FIFO Frame ID Rejection Filter Mask Register (FR_RFFIDRFMR)........................................... 2417
48.6.63 Receive FIFO Range Filter Configuration Register (FR_RFRFCFR).........................................................2418
48.6.64 Receive FIFO Range Filter Control Register (FR_RFRFCTR)...................................................................2419
48.6.65 Last Dynamic Transmit Slot Channel A Register (FR_LDTXSLAR)........................................................ 2420
48.6.66 Last Dynamic Transmit Slot Channel B Register (FR_LDTXSLBR).........................................................2421
48.6.67 Protocol Configuration Register 0 (FR_PCR0)........................................................................................... 2421
48.6.68 Protocol Configuration Register 1 (FR_PCR1)........................................................................................... 2424
48.6.69 Protocol Configuration Register 2 (FR_PCR2)........................................................................................... 2424
48.6.70 Protocol Configuration Register 3 (FR_PCR3)........................................................................................... 2425
48.6.71 Protocol Configuration Register 4 (FR_PCR4)........................................................................................... 2425
48.6.72 Protocol Configuration Register 5 (FR_PCR5)........................................................................................... 2426
48.6.73 Protocol Configuration Register 6 (FR_PCR6)........................................................................................... 2426
48.6.74 Protocol Configuration Register 7 (FR_PCR7)........................................................................................... 2427
48.6.75 Protocol Configuration Register 8 (FR_PCR8)........................................................................................... 2427
48.6.76 Protocol Configuration Register 9 (FR_PCR9)........................................................................................... 2428
48.6.77 Protocol Configuration Register 10 (FR_PCR10)....................................................................................... 2429
48.6.78 Protocol Configuration Register 11 (FR_PCR11)....................................................................................... 2429
48.6.79 Protocol Configuration Register 12 (FR_PCR12)....................................................................................... 2430
48.6.80 Protocol Configuration Register 13 (FR_PCR13)....................................................................................... 2430
48.6.81 Protocol Configuration Register 14 (FR_PCR14)....................................................................................... 2431
48.6.82 Protocol Configuration Register 15 (FR_PCR15)....................................................................................... 2431
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48.6.83 Protocol Configuration Register 16 (FR_PCR16)....................................................................................... 2432
48.6.84 Protocol Configuration Register 17 (FR_PCR17)....................................................................................... 2432
48.6.85 Protocol Configuration Register 18 (FR_PCR18)....................................................................................... 2433
48.6.86 Protocol Configuration Register 19 (FR_PCR19)....................................................................................... 2433
48.6.87 Protocol Configuration Register 20 (FR_PCR20)....................................................................................... 2434
48.6.88 Protocol Configuration Register 21 (FR_PCR21)....................................................................................... 2434
48.6.89 Protocol Configuration Register 22 (FR_PCR22)....................................................................................... 2435
48.6.90 Protocol Configuration Register 23 (FR_PCR23)....................................................................................... 2435
48.6.91 Protocol Configuration Register 24 (FR_PCR24)....................................................................................... 2436
48.6.92 Protocol Configuration Register 25 (FR_PCR25)....................................................................................... 2436
48.6.93 Protocol Configuration Register 26 (FR_PCR26)....................................................................................... 2437
48.6.94 Protocol Configuration Register 27 (FR_PCR27)....................................................................................... 2437
48.6.95 Protocol Configuration Register 28 (FR_PCR28)....................................................................................... 2438
48.6.96 Protocol Configuration Register 29 (FR_PCR29)....................................................................................... 2438
48.6.97 Protocol Configuration Register 30 (FR_PCR30)....................................................................................... 2439
48.6.98 StopWatch Count High Register (FR_STPWHR)....................................................................................... 2440
48.6.99 Stop Watch Count Low Register (FR_STPWLR)....................................................................................... 2440
48.6.100 Protocol Event Output Enable and StopWatch Control Register (FR_PEOER)......................................... 2440
48.6.101 Receive FIFO Start Data Offset Register (FR_RFSDOR)...........................................................................2441
48.6.102 Receive FIFO System Memory Base Address High Register (FR_RFSYMBADHR)............................... 2442
48.6.103 Receive FIFO System Memory Base Address Low Register (FR_RFSYMBADLR)................................ 2442
48.6.104 Receive FIFO Periodic Timer Register (FR_RFPTR).................................................................................2443
48.6.105 Receive FIFO Fill Level and POP Count Register (FR_RFFLPCR)...........................................................2444
48.6.106 ECC Error Interrupt Flag and Enable Register (FR_EEIFER).................................................................... 2445
48.6.107 ECC Error Report and Injection Control Register (FR_EERICR).............................................................. 2447
48.6.108 ECC Error Report Address Register (FR_EERAR).................................................................................... 2448
48.6.109 ECC Error Report Data Register (FR_EERDR).......................................................................................... 2449
48.6.110 ECC Error Report Code Register (FR_EERCR)......................................................................................... 2450
48.6.111 ECC Error Injection Address Register (FR_EEIAR).................................................................................. 2451
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48.6.112 ECC Error Injection Data Register (FR_EEIDR)........................................................................................ 2451
48.6.113 ECC Error Injection Code Register (FR_EEICR)....................................................................................... 2452
48.6.114 Message Buffer Configuration, Control, Status Register (FR_MBCCSRn)............................................... 2452
48.6.115 Message Buffer Cycle Counter Filter Register (FR_MBCCFRn)............................................................... 2454
48.6.116 Message Buffer Frame ID Register (FR_MBFIDRn)..................................................................................2456
48.6.117 Message Buffer Index Register (FR_MBIDXRn)....................................................................................... 2456
48.6.118 Message Buffer Data Field Offset Register (FR_MBDORn)......................................................................2457
48.6.119 LRAM ECC Error Test Register (FR_LEETRn).........................................................................................2458
48.7 Functional Description..................................................................................................................................................2458
48.7.1 Message Buffer Concept..............................................................................................................................2458
48.7.2 Physical Message Buffer..............................................................................................................................2458
48.7.3 Message Buffer Types................................................................................................................................. 2460
48.7.4 FlexRay Memory Area Layout.................................................................................................................... 2469
48.7.5 Physical Message Buffer Description.......................................................................................................... 2473
48.7.6 Individual Message Buffer Functional Description..................................................................................... 2484
48.7.7 Individual Message Buffer Search...............................................................................................................2504
48.7.8 Individual Message Buffer Reconfiguration................................................................................................2508
48.7.9 Receive FIFOs..............................................................................................................................................2508
48.7.10 Channel Device Modes................................................................................................................................ 2517
48.7.11 External Clock Synchronization.................................................................................................................. 2519
48.7.12 Sync Frame ID and Sync Frame Deviation Tables......................................................................................2520
48.7.13 MTS Generation...........................................................................................................................................2524
48.7.14 Key Slot Transmission................................................................................................................................. 2524
48.7.15 Sync Frame Filtering....................................................................................................................................2525
48.7.16 Strobe Signal Support.................................................................................................................................. 2527
48.7.17 Timer Support.............................................................................................................................................. 2528
48.7.18 Slot Status Monitoring................................................................................................................................. 2530
48.7.19 System Bus Access...................................................................................................................................... 2534
48.7.20 Interrupt Support.......................................................................................................................................... 2536
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48.7.21 Lower Bit Rate Support............................................................................................................................... 2541
48.7.22 PE Data Memory (PE DRAM).................................................................................................................... 2542
48.7.23 CHI Lookup-Table Memory (CHI LRAM)................................................................................................. 2544
48.7.24 Memory Content Fault Detection................................................................................................................ 2545
48.7.25 Memory Fault Injection............................................................................................................................... 2550
48.7.26 StopWatch function......................................................................................................................................2553
48.8 Application Information................................................................................................................................................2555
48.8.1 Module Configuration..................................................................................................................................2555
48.8.2 Initialization Sequence.................................................................................................................................2556
48.8.3 Memory Fault Injection out of POC:default config.....................................................................................2558
48.8.4 Shut Down Sequence................................................................................................................................... 2559
48.8.5 Number of Usable Message Buffers............................................................................................................ 2559
48.8.6 Protocol Control Command Execution........................................................................................................ 2560
48.8.7 Message Buffer Search On Simple Message Buffer Configuration............................................................ 2561
Chapter 49
Secure Digital Host Controller (uSDHC)
49.1 uSDHC Chip-specific information............................................................................................................................... 2565
49.2 Introduction...................................................................................................................................................................2566
49.2.1 Overview......................................................................................................................................................2566
49.3 Memory Map/Register Definition.................................................................................................................................2570
49.3.1 DMA System Address (uSDHC_S_ADDR)................................................................................................2572
49.3.2 Block Attributes (uSDHC_BLK_ATT)....................................................................................................... 2572
49.3.3 Command Argument (uSDHC_CMD_ARG)..............................................................................................2573
49.3.4 Command Transfer Type (uSDHC_CMD_XFR_TYP).............................................................................. 2574
49.3.5 Command Response0 (uSDHC_CMD_RSP0)............................................................................................ 2577
49.3.6 Command Response1 (uSDHC_CMD_RSP1)............................................................................................ 2578
49.3.7 Command Response2 (uSDHC_CMD_RSP2)............................................................................................ 2578
49.3.8 Command Response3 (uSDHC_CMD_RSP3)............................................................................................ 2579
49.3.9 Data Buffer Access Port (uSDHC_DATA_BUFF_ACC_PORT)...............................................................2580
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49.3.10 Present State (uSDHC_PRES_STATE).......................................................................................................2580
49.3.11 Protocol Control (uSDHC_PROT_CTRL).................................................................................................. 2586
49.3.12 System Control (uSDHC_SYS_CTRL).......................................................................................................2590
49.3.13 Interrupt Status (uSDHC_INT_STATUS)...................................................................................................2593
49.3.14 Interrupt Status Enable (uSDHC_INT_STATUS_EN)............................................................................... 2598
49.3.15 Interrupt Signal Enable (uSDHC_INT_SIGNAL_EN)............................................................................... 2602
49.3.16 Auto CMD12 Error Status (uSDHC_AUTOCMD12_ERR_STATUS)......................................................2604
49.3.17 Host Controller Capabilities (uSDHC_HOST_CTRL_CAP)......................................................................2608
49.3.18 Watermark Level (uSDHC_WTMK_LVL).................................................................................................2610
49.3.19 Mixer Control (uSDHC_MIX_CTRL)........................................................................................................ 2611
49.3.20 Force Event (uSDHC_FORCE_EVENT)....................................................................................................2613
49.3.21 ADMA Error Status Register (uSDHC_ADMA_ERR_STATUS)............................................................. 2616
49.3.22 ADMA System Address (uSDHC_ADMA_SYS_ADDR)......................................................................... 2618
49.3.23 Vendor Specific Register (uSDHC_VEND_SPEC).................................................................................... 2619
49.3.24 MMC Boot Register (uSDHC_MMC_BOOT)............................................................................................2622
49.3.25 Vendor Specific 2 Register (uSDHC_VEND_SPEC2)............................................................................... 2624
49.3.26 Host Controller Version (uSDHC_HOST_CTRL_VER)............................................................................ 2625
49.4 Functional Description..................................................................................................................................................2626
49.4.1 Data Buffer...................................................................................................................................................2626
49.4.2 DMA AHB Interface....................................................................................................................................2632
49.4.3 Register Bank ..............................................................................................................................................2638
49.4.4 Clock and Reset Manager............................................................................................................................ 2640
49.4.5 Clock Generator........................................................................................................................................... 2641
49.4.6 SDIO Card Interrupt.....................................................................................................................................2641
49.4.7 Card Insertion and Removal Detection........................................................................................................2643
49.4.8 Power Management and Wake Up Events...................................................................................................2644
49.5 Initialization/Application of uSDHC............................................................................................................................ 2645
49.5.1 Command Send and Response Receive Basic Operation............................................................................ 2645
49.5.2 Card Identification Mode............................................................................................................................. 2646
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49.5.3 Card Access..................................................................................................................................................2652
49.5.4 Switch Function........................................................................................................................................... 2661
49.5.5 ADMA Operation........................................................................................................................................ 2663
49.6 Commands for MMC/SD/SDIO................................................................................................................................... 2665
49.7 Software Restrictions....................................................................................................................................................2670
49.7.1 Initialization Active......................................................................................................................................2670
49.7.2 Software Polling Procedure......................................................................................................................... 2670
49.7.3 Suspend Operation....................................................................................................................................... 2670
49.7.4 Data Length Setting..................................................................................................................................... 2670
49.7.5 (A)DMA Address Setting............................................................................................................................ 2671
49.7.6 Data Port Access.......................................................................................................................................... 2671
49.7.7 Change Clock Frequency............................................................................................................................. 2671
49.7.8 Multi-block Read......................................................................................................................................... 2671
Chapter 50
PCI Express (PCIe)
50.1 PCIe Chip Specific Information....................................................................................................................................2673
50.1.1 GIC134 interrupt.......................................................................................................................................... 2673
50.2 Register Configuration for PCIe Base Spec..................................................................................................................2674
50.3 Introduction...................................................................................................................................................................2674
50.3.1 Terms and Abbreviations............................................................................................................................. 2674
50.3.2 Overview......................................................................................................................................................2676
50.3.3 Modes of Operation..................................................................................................................................... 2680
50.4 External (Link Interface) Signal Descriptions.............................................................................................................. 2681
50.5 PCIe CTRL EP Mode Memory Map/Register Definition............................................................................................ 2682
50.5.1 Device ID and Vendor ID Register (PCIE_EP_DeviceID)......................................................................... 2684
50.5.2 Command and Status Register (PCIE_EP_Command)............................................................................... 2686
50.5.3 PCI Express Revision ID Register (PCIE_EP_Revision_ID)......................................................................2689
50.5.4 BIST Register (PCIE_EP_BIST)................................................................................................................. 2691
50.5.5 Base Address 0 (PCIE_EP_BAR0)..............................................................................................................2692
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50.5.6 Base Address 1 (PCIE_EP_BAR1)..............................................................................................................2694
50.5.7 Base Address 2 (PCIE_EP_BAR2)..............................................................................................................2695
50.5.8 Base Address 3 (PCIE_EP_BAR3)..............................................................................................................2696
50.5.9 CardBus CIS Pointer Register (PCIE_EP_CISP)........................................................................................ 2696
50.5.10 Subsystem ID and Subsystem Vendor ID Register (PCIE_EP_SSID)........................................................2697
50.5.11 Expansion ROM Base Address Register (PCIE_EP_EROMBAR).............................................................2697
50.5.12 Capability Pointer Register (PCIE_EP_CAPPR)........................................................................................ 2698
50.5.13 Interrupt Line and Pin Register (PCIE_EP_ILR)........................................................................................ 2698
50.5.14 Power Management Capability ID Register (PCIE_EP_PMCIDR)............................................................ 2699
50.5.15 Power Management Capabilities Register (PCIE_EP_PMCR)................................................................... 2699
50.5.16 Power Management Status and Control Register (PCIE_EP_PMSCR)...................................................... 2700
50.5.17 PCI Express MSI Message Capability ID Register (PCIE_EP_MSI_MCIDR).......................................... 2701
50.5.18 PCI Express MSI Message Control Register (PCIE_EP_MSI_MCR)........................................................ 2702
50.5.19 PCI Express MSI Message Address Register (PCIE_EP_MSI_MADDR)................................................. 2703
50.5.20 PCI Express MSI Message Upper Address Register (PCIE_EP_MSI_MUADDR)................................... 2703
50.5.21 PCI Express MSI Message Data Register (PCIE_EP_MSI_MDATR)....................................................... 2704
50.5.22 Capability ID Register (PCIE_EP_CIDR)...................................................................................................2704
50.5.23 PCI Express Capabilities Register (PCIE_EP_CR)..................................................................................... 2704
50.5.24 PCI Express Device Capabilities Register (PCIE_EP_DCR)......................................................................2705
50.5.25 PCI Express Device Control Register (PCIE_EP_DCTRLR)..................................................................... 2706
50.5.26 PCI Express Device Status Register (PCIE_EP_DSR)................................................................................2707
50.5.27 PCI Express Link Capabilities Register (PCIE_EP_LCR).......................................................................... 2709
50.5.28 PCI Express Link Control Register (PCIE_EP_CTRLR)............................................................................2711
50.5.29 PCI Express Link Status Register (PCIE_EP_SR)...................................................................................... 2712
50.5.30 PCI Express Slot Capabilities Register (PCIE_EP_SCR)........................................................................... 2713
50.5.31 PCI Express Slot Control Register (PCIE_EP_SCTRLR)...........................................................................2714
50.5.32 PCI Express Slot Status Register (PCIE_EP_SSR)..................................................................................... 2716
50.5.33 Root Control Register (PCIE_EP_RCR)..................................................................................................... 2717
50.5.34 PCI Express Root Status Register (PCIE_EP_RSR)................................................................................... 2718
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50.5.35 PCI Express Device Capabilities 2 Register (PCIE_EP_DC_2)................................................................. 2719
50.5.36 PCI Express Device Control 2 Register (PCIE_EP_DCTR_2)................................................................... 2719
50.5.37 PCI Express Link Capabilities 2 Register (PCIE_EP_LC_2)......................................................................2721
50.5.38 PCI Express Link Control 2 Register (PCIE_EP_LCTR_2)....................................................................... 2722
50.5.39 PCI Express Link Status 2 Register (PCIE_EP_LS_2)............................................................................... 2723
50.5.40 AER Capability Header (PCIE_EP_AER).................................................................................................. 2723
50.5.41 Uncorrectable Error Status Register (PCIE_EP_UESR)............................................................................. 2725
50.5.42 Uncorrectable Error Mask Register (PCIE_EP_UEMR).............................................................................2728
50.5.43 Uncorrectable Error Severity Register (PCIE_EP_UESevR)......................................................................2730
50.5.44 Correctable Error Status Register (PCIE_EP_CESR)................................................................................. 2732
50.5.45 Correctable Error Mask Register (PCIE_EP_CEMR)................................................................................. 2734
50.5.46 Advanced Capabilities and Control Register (PCIE_EP_ACCR)............................................................... 2736
50.5.47 PCI Express Header Log Register 1 (PCIE_EP_Header_Log_Register_DWORD1)................................. 2738
50.5.48 PCI Express Header Log Register 2 (PCIE_EP_Header_Log_Register_DWORD2)................................. 2739
50.5.49 PCI Express Header Log Register 3 (PCIE_EP_Header_Log_Register_DWORD3)................................. 2739
50.5.50 PCI Express Header Log Register 4 (PCIE_EP_Header_Log_Register_DWORD4)................................. 2740
50.5.51 BAR 0 Mask Register (PCIE_EP_MASK0)................................................................................................2740
50.5.52 BAR 1 Mask Register (PCIE_EP_MASK1)................................................................................................2742
50.5.53 BAR 2 Mask Register (PCIE_EP_MASK2)................................................................................................2743
50.5.54 BAR 3 Mask Register (PCIE_EP_MASK3)................................................................................................2744
50.5.55 Expansion ROM BAR Mask Register (PCIE_EP_EROMMASK)............................................................. 2745
50.6 PCIe CTRL RC Mode Memory Map/Register Definition............................................................................................2746
50.6.1 Device ID and Vendor ID Register (PCIE_RC_DeviceID).........................................................................2748
50.6.2 Command and Status Register (PCIE_RC_Command)...............................................................................2749
50.6.3 BIST Register (PCIE_RC_BIST)................................................................................................................ 2752
50.6.4 Base Address 0 (PCIE_RC_BAR0).............................................................................................................2753
50.6.5 Base Address 1 (PCIE_RC_BAR1).............................................................................................................2755
50.6.6 Bus Number Registers (PCIE_RC_BNR)....................................................................................................2755
50.6.7 I/O Base Limit Secondary Status Register (PCIE_RC_IOBLSSR).............................................................2757
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50.6.8 Memory Base and Memory Limit Register (PCIE_RC_MEM_BLR)........................................................ 2759
50.6.9 Prefetchable Memory Base and Limit Register (PCIE_RC_PREF_MEM_BLR).......................................2759
50.6.10 Prefetchable Base Upper 32 Bits Register (PCIE_RC_PREF_BASE_U32)...............................................2760
50.6.11 Prefetchable Limit Upper 32 Bits Register (PCIE_RC_PREF_LIM_U32).................................................2760
50.6.12 I/O Base and Limit Upper 16 Bits Register (PCIE_RC_IO_BASE_LIM_U16).........................................2761
50.6.13 Capability Pointer Register (PCIE_RC_CAPPR)........................................................................................2761
50.6.14 Expansion ROM Base Address Register (PCIE_RC_EROMBAR)............................................................ 2762
50.6.15 PCI Express Interrupt Line Register (PCIE_RC_Interrupt_Line_Register)................................................2762
50.6.16 Power Management Capability Register (PCIE_RC_PMCR).....................................................................2763
50.6.17 Power Management Control and Status Register (PCIE_RC_PMCSR)..................................................... 2766
50.6.18 PCI Express Capability ID Register (PCIE_RC_CIDR)............................................................................. 2769
50.6.19 Device Capabilities Register (PCIE_RC_DCR).......................................................................................... 2770
50.6.20 Device Control Register (PCIE_RC_DConR).............................................................................................2772
50.6.21 Link Capabilities Register (PCIE_RC_LCR).............................................................................................. 2776
50.6.22 Link Control and Status Register (PCIE_RC_LCSR)................................................................................. 2779
50.6.23 Slot Capabilities Register (PCIE_RC_SCR)................................................................................................2783
50.6.24 Slot Control and Status Register (PCIE_RC_SCSR)...................................................................................2786
50.6.25 Root Control and Capabilities Register (PCIE_RC_RCCR)....................................................................... 2788
50.6.26 Root Status Register (PCIE_RC_RSR)........................................................................................................2789
50.6.27 Device Capabilities 2 Register (PCIE_RC_DCR2)..................................................................................... 2791
50.6.28 Device Control and Status 2 Register (PCIE_RC_DCSR2)........................................................................ 2792
50.6.29 Link Capabilities 2 Register (PCIE_RC_LCR2)......................................................................................... 2794
50.6.30 Link Control and Status 2 Register (PCIE_RC_LCSR2)............................................................................ 2796
50.6.31 AER Capability Header (PCIE_RC_AER)..................................................................................................2799
50.6.32 Uncorrectable Error Status Register (PCIE_RC_UESR).............................................................................2801
50.6.33 Uncorrectable Error Mask Register (PCIE_RC_UEMR)............................................................................ 2804
50.6.34 Uncorrectable Error Severity Register (PCIE_RC_UESevR)..................................................................... 2806
50.6.35 Correctable Error Status Register (PCIE_RC_CESR).................................................................................2808
50.6.36 Correctable Error Mask Register (PCIE_RC_CEMR)................................................................................ 2810
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50.6.37 Advanced Error Capabilities and Control Register (PCIE_RC_AECCR)...................................................2812
50.6.38 PCI Express Header Log Register 1 (PCIE_RC_Header_Log_Register_DWORD1)................................ 2814
50.6.39 PCI Express Header Log Register 2 (PCIE_RC_Header_Log_Register_DWORD2)................................ 2815
50.6.40 PCI Express Header Log Register 3 (PCIE_RC_Header_Log_Register_DWORD3)................................ 2815
50.6.41 PCI Express Header Log Register 4 (PCIE_RC_Header_Log_Register_DWORD4)................................ 2816
50.6.42 Root Error Command Register (PCIE_RC_RECR).................................................................................... 2817
50.6.43 Root Error Status Register (PCIE_RC_RESR)............................................................................................2818
50.6.44 Error Source Identification Register (PCIE_RC_ESIR)..............................................................................2820
50.6.45 BAR 0 Mask Register (PCIE_RC_MASK0)............................................................................................... 2820
50.6.46 BAR 1 Mask Register (PCIE_RC_MASK1)............................................................................................... 2823
50.6.47 Expansion ROM BAR Mask Register (PCIE_RC_EROMMASK)............................................................ 2823
50.7 PCIe CTRL Port Logic Memory Map/Register Definition.......................................................................................... 2824
50.7.1 Ack Latency Timer and Replay Timer Register (PCIE_PL_ALTRTR)......................................................2826
50.7.2 Vendor Specific DLLP Register (PCIE_PL_VSDR)...................................................................................2827
50.7.3 Port Force Link Register (PCIE_PL_PFLR)............................................................................................... 2827
50.7.4 Ack Frequency and L0-L1 ASPM Control Register (PCIE_PL_AFLACR)...............................................2828
50.7.5 Port Link Control Register (PCIE_PL_PLCR)............................................................................................2831
50.7.6 Lane Skew Register (PCIE_PL_LSR)......................................................................................................... 2833
50.7.7 Timer Control and Max Function Number Register (PCIE_PL_TIMER_CTRL_MAX_NUM)................2834
50.7.8 Symbol Timer Register and Filter Mask Register 1 (PCIE_PL_STRFM1)................................................ 2835
50.7.9 Filter Mask Register 2 (PCIE_PL_STRFM2)..............................................................................................2836
50.7.10 AMBA Multiple Outbound Decomposed NP Sub-Requests Control Register (PCIE_PL_AMODNPSR) 2837
50.7.11 Debug Register 0 (PCIE_PL_DEBUG0).....................................................................................................2838
50.7.12 Debug Register 1 (PCIE_PL_DEBUG1).....................................................................................................2838
50.7.13 Transmit Posted FC Credit Status Register (PCIE_PL_TPFCSR).............................................................. 2838
50.7.14 Transmit Non-Posted FC Credit Status Register (PCIE_PL_TNFCSR)..................................................... 2839
50.7.15 Transmit Completion FC Credit Status Register (PCIE_PL_TCFCSR)..................................................... 2840
50.7.16 Queue Status Register (PCIE_PL_QSR)..................................................................................................... 2841
50.7.17 Gen2 Control Register (PCIE_PL_G2CR).................................................................................................. 2844
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50.7.18 PHY Status (PCIE_PL_PHY_STATUS).....................................................................................................2845
50.7.19 PHY Control (PCIE_PL_PHY_CTRL)....................................................................................................... 2846
50.7.20 Master Response Composer Control Register 0 (PCIE_PL_MRCCR0)..................................................... 2846
50.7.21 Master Response Composer Control Register 1 (PCIE_PL_MRCCR1)..................................................... 2847
50.7.22 MSI Controller Address (PCIE_PL_MSICA)............................................................................................. 2848
50.7.23 MSI Controller Upper Address (PCIE_PL_MSICUA)............................................................................... 2848
50.7.24 MSI Controller Interrupt n Enable (PCIE_PL_MSICIn_ENB)...................................................................2849
50.7.25 MSI Controller Interrupt n Mask (PCIE_PL_MSICIn_MASK)..................................................................2849
50.7.26 MSI Controller Interrupt nStatus (PCIE_PL_MSICInn_STATUS)............................................................ 2850
50.7.27 MSI Controller General Purpose IO Register (PCIE_PL_MSICGPIO)......................................................2850
50.7.28 iATM Viewport Register (PCIE_PL_iATMVR).........................................................................................2850
50.7.29 iATM Region Control 1 Register (PCIE_PL_iATMRC1).......................................................................... 2852
50.7.30 iATM Region Control 2 Register (PCIE_PL_iATMRC2).......................................................................... 2854
50.7.31 iATM Region Lower Base Address Register (PCIE_PL_iATMRLBA).....................................................2857
50.7.32 iATM Region Upper Base Address Register (PCIE_PL_iATMRUBA).....................................................2858
50.7.33 iATM Region Limit Address Register (PCIE_PL_iATMRLA)..................................................................2858
50.7.34 iATM Region Lower Target Address Register (PCIE_PL_iATMRLTA).................................................. 2858
50.7.35 iATM Region Upper Target Address Register (PCIE_PL_iATMRUTA).................................................. 2859
50.8 Functional Description..................................................................................................................................................2859
50.8.1 Transaction Layer........................................................................................................................................ 2860
50.8.2 Data Link Layer........................................................................................................................................... 2861
50.8.3 MAC Layer.................................................................................................................................................. 2861
50.8.4 Architecture..................................................................................................................................................2862
50.9 Initialization/Application Information..........................................................................................................................2864
50.9.1 Initial start-up programming guide ............................................................................................................. 2864
50.9.2 L2 entry and exit procedures........................................................................................................................2865
50.10 Embedded DMA Controller..........................................................................................................................................2865
50.10.1 Overview......................................................................................................................................................2865
50.10.2 Feature List.................................................................................................................................................. 2866
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50.10.3 Limitations................................................................................................................................................... 2867
50.10.4 DMA Architecture....................................................................................................................................... 2868
50.10.5 Interrupts and Error Handling...................................................................................................................... 2870
50.10.6 Using the DMA............................................................................................................................................2880
50.10.7 Programming Examples...............................................................................................................................2885
50.10.8 Advanced DMA Information and Operation............................................................................................... 2895
50.10.9 PCIe Registers (DMA).................................................................................................................................2901
50.11 PCIe2 PHY Overview...................................................................................................................................................2939
50.12 PCIe2 PHY Features.....................................................................................................................................................2940
50.12.1 Standards Compliance..................................................................................................................................2940
50.12.2 PHY Features............................................................................................................................................... 2940
50.13 PCIe2 PHY Functional Description..............................................................................................................................2940
50.13.1 Clocks and Resets........................................................................................................................................ 2940
Chapter 51
Analog-to-Digital Converter (SAR-ADC)
51.1 Chip specific SAR-ADC information...........................................................................................................................2943
51.1.1 SAR-ADC channels..................................................................................................................................... 2943
51.1.2 Channel specific configurations...................................................................................................................2944
51.1.3 Self-test........................................................................................................................................................ 2945
51.2 Introduction...................................................................................................................................................................2945
51.3 Overview.......................................................................................................................................................................2945
51.3.1 Interfaces......................................................................................................................................................2946
51.3.2 Submodules..................................................................................................................................................2946
51.3.3 Clock and Reset........................................................................................................................................... 2946
51.3.4 Special channels...........................................................................................................................................2947
51.4 Feature list.....................................................................................................................................................................2948
51.5 Functional description...................................................................................................................................................2948
51.5.1 Conversion................................................................................................................................................... 2948
51.5.2 Normal Conversion mode............................................................................................................................ 2949
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51.5.3 Injected Conversion mode........................................................................................................................... 2952
51.5.4 Abort of conversion..................................................................................................................................... 2953
51.5.5 ADC clock prescaler and sample time settings............................................................................................2954
51.5.6 Presampling..................................................................................................................................................2955
51.5.7 Programmable analog watchdog..................................................................................................................2956
51.5.8 DMA functionality.......................................................................................................................................2958
51.5.9 Interrupts...................................................................................................................................................... 2959
51.5.10 Power Down mode.......................................................................................................................................2962
51.5.11 Auto-clock-off mode....................................................................................................................................2963
51.5.12 Calibration ...................................................................................................................................................2963
51.5.13 Self-test ....................................................................................................................................................... 2965
51.5.14 Conversion time........................................................................................................................................... 2976
51.5.15 Conversion data processing......................................................................................................................... 2980
51.5.16 User defined offset and gain values............................................................................................................. 2980
51.6 Programming sequences............................................................................................................................................... 2982
51.6.1 Running calibration......................................................................................................................................2982
51.6.2 Running Normal conversion........................................................................................................................ 2983
51.6.3 Running Injected conversion....................................................................................................................... 2984
51.6.4 Running self-test.......................................................................................................................................... 2984
51.7 Register Description......................................................................................................................................................2985
51.7.1 Main Configuration Register (SAR_ADC_MCR).......................................................................................2988
51.7.2 Main Status Register (SAR_ADC_MSR)....................................................................................................2992
51.7.3 Interrupt Status Register (SAR_ADC_ISR)................................................................................................ 2995
51.7.4 Channel Pending Register (SAR_ADC_CEOCFR0).................................................................................. 2995
51.7.5 Channel Pending Register 1 (SAR_ADC_CEOCFR1)............................................................................... 2997
51.7.6 Interrupt Mask Register (SAR_ADC_IMR)................................................................................................ 2999
51.7.7 Channel Interrupt Mask Register 0 (SAR_ADC_CIMR0).......................................................................... 3000
51.7.8 Channel Interrupt Mask Register 1 (SAR_ADC_CIMR1).......................................................................... 3001
51.7.9 Watchdog Threshold Interrupt Status Register (SAR_ADC_WTISR)........................................................3003
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51.7.10 Watchdog Threshold Interrupt Mask Register (SAR_ADC_WTIMR)....................................................... 3005
51.7.11 DMAE Register (SAR_ADC_DMAE)........................................................................................................3008
51.7.12 DMA Register 0 (SAR_ADC_DMAR0)..................................................................................................... 3008
51.7.13 DMA Register 1 (SAR_ADC_DMAR1)..................................................................................................... 3010
51.7.14 Analog Watchdog Threshold Register 0 (SAR_ADC_THRHLR0)............................................................ 3012
51.7.15 Analog Watchdog Threshold Register 1 (SAR_ADC_THRHLR1)............................................................ 3012
51.7.16 Analog Watchdog Threshold Register 2 (SAR_ADC_THRHLR2)............................................................ 3013
51.7.17 Analog Watchdog Threshold Register 2 (SAR_ADC_THRHLR3)............................................................ 3013
51.7.18 Presampling Control Register (SAR_ADC_PSCR).................................................................................... 3014
51.7.19 Presampling Register 0 (SAR_ADC_PSR0)............................................................................................... 3014
51.7.20 Presampling Register 1 (SAR_ADC_PSR1)............................................................................................... 3016
51.7.21 Conversion Timing Register 0 (SAR_ADC_CTR0)................................................................................... 3018
51.7.22 Conversion Timing Register 2 (SAR_ADC_CTR1)................................................................................... 3018
51.7.23 Normal Conversion Mask Register (SAR_ADC_NCMR0)........................................................................ 3018
51.7.24 Normal Conversion Mask Register (SAR_ADC_NCMR1)........................................................................ 3020
51.7.25 Injected Conversion Mask Register (SAR_ADC_JCMR0).........................................................................3021
51.7.26 Injected Conversion Mask Register (SAR_ADC_JCMR1).........................................................................3023
51.7.27 User OFFSET and Gain Register (SAR_ADC_USROFSGN).................................................................... 3024
51.7.28 Power Down Exit Delay Register (SAR_ADC_PDEDR)........................................................................... 3025
51.7.29 Channel n Data Register (SAR_ADC_CDRn)............................................................................................ 3025
51.7.30 Channel n Data Register (SAR_ADC_CDRn)............................................................................................ 3027
51.7.31 Analog Watchdog Threshold Register 4 (SAR_ADC_THRHLR4)............................................................ 3028
51.7.32 Analog Watchdog Threshold Register 5 (SAR_ADC_THRHLR5)............................................................ 3028
51.7.33 Analog Watchdog Threshold Register 6 (SAR_ADC_THRHLR6)............................................................ 3029
51.7.34 Analog Watchdog Threshold Register 7 (SAR_ADC_THRHLR7)............................................................ 3029
51.7.35 Channel Watchdog Select Register (SAR_ADC_CWSELR0)....................................................................3030
51.7.36 Channel Watchdog Select Register (SAR_ADC_CWSELR4)....................................................................3032
51.7.37 Channel Watchdog Enable Register (SAR_ADC_CWENR0).................................................................... 3034
51.7.38 Channel Watchdog Enable Register (SAR_ADC_CWENR1).................................................................... 3036
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51.7.39 Analog Watchdog Out of Range Register (SAR_ADC_AWORR0)...........................................................3037
51.7.40 Analog Watchdog Out of Range Register (SAR_ADC_AWORR1)...........................................................3039
51.7.41 Self-Test Configuration Register 1 (SAR_ADC_STCR1).......................................................................... 3041
51.7.42 Self-Test Configuration Register 2 (SAR_ADC_STCR2).......................................................................... 3042
51.7.43 Self-Test Configuration Register 3 (SAR_ADC_STCR3).......................................................................... 3045
51.7.44 Self-Test Baud Rate Register (SAR_ADC_STBRR).................................................................................. 3046
51.7.45 Self-Test Status Register 1 (SAR_ADC_STSR1)....................................................................................... 3047
51.7.46 Self-Test Status Register 2 (SAR_ADC_STSR2)....................................................................................... 3050
51.7.47 Self-Test Status Register 3 (SAR_ADC_STSR3)....................................................................................... 3051
51.7.48 Self-Test Status Register 4 (SAR_ADC_STSR4)....................................................................................... 3051
51.7.49 Self-Test Data Register 1 (SAR_ADC_STDR1)......................................................................................... 3052
51.7.50 Self-Test Data Register 2 (SAR_ADC_STDR2)......................................................................................... 3053
51.7.51 Self-Test Analog Watchdog Register (SAR_ADC_STAW0R)...................................................................3054
51.7.52 Self-Test Analog Watchdog Register (SAR_ADC_STAW1AR)................................................................3055
51.7.53 Self-Test Analog Watchdog Register 1B (SAR_ADC_STAW1BR).......................................................... 3056
51.7.54 Self-Test Analog Watchdog Register 2 (SAR_ADC_STAW2R)................................................................3057
51.7.55 Self-Test Analog Watchdog Register 3 (SAR_ADC_STAW3R)................................................................3057
51.7.55 Self-Test Analog Watchdog Register 4 (SAR_ADC_STAW4R)................................................................3058
51.7.56 Self-Test Analog Watchdog Register 5 (SAR_ADC_STAW5R)................................................................3059
51.7.57 Calibration Status register (SAR_ADC_CALSTAT).................................................................................. 3060
51.8 Input impedance versus ADC speed.............................................................................................................................3063
Chapter 52
Temperature Sensor
52.1 Chip-specific TSENS Information................................................................................................................................3065
52.2 Introduction...................................................................................................................................................................3065
52.2.1 Overview......................................................................................................................................................3065
52.2.2 Features........................................................................................................................................................ 3066
52.2.3 Modes of Operation..................................................................................................................................... 3067
52.3 TMU memory map and registers.................................................................................................................................. 3067
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52.3.1 Mode Register (TMU_MR)......................................................................................................................... 3069
52.3.2 Status Register (TMU_SR).......................................................................................................................... 3070
52.3.3 Monitor Temperature Measurement Interval Register (TMU_MTMIR).....................................................3071
52.3.4 Interrupt Enable Register (TMU_IER)........................................................................................................ 3072
52.3.5 Interrupt Detect Register (TMU_IDR)........................................................................................................ 3073
52.3.6 Monitor High Temperature Capture Register (TMU_MHTCR)................................................................. 3074
52.3.7 Monitor Low Temperature Capture Register (TMU_MLTCR).................................................................. 3075
52.3.8 Monitor High Temperature Immediate Threshold Register (TMU_MHTITR)...........................................3075
52.3.9 Monitor High Temperature Average Threshold Register (TMU_MHTATR).............................................3076
52.3.10 Monitor High Temperature Average Critical Threshold Register (TMU_MHTACTR).............................3077
52.3.11 Temperature Configuration Register (TMU_TCFGR)................................................................................ 3077
52.3.12 Sensor Configuration Register (TMU_SCFGR)..........................................................................................3078
52.3.13 Report Immediate Temperature Site Register (TMU_RITSR)....................................................................3079
52.3.14 Report Average Temperature Site Register (TMU_RATSR)......................................................................3079
52.3.15 Engineering Use Mode Register (TMU_EUMR)........................................................................................ 3080
52.4 Functional Description..................................................................................................................................................3080
52.4.1 Monitoring................................................................................................................................................... 3081
52.4.2 Reporting......................................................................................................................................................3081
52.5 Initialization information.............................................................................................................................................. 3082
Chapter 53
2D-ACE
53.1 2D-ACE QoS................................................................................................................................................................ 3085
53.2 Introduction...................................................................................................................................................................3085
53.2.1 Overview......................................................................................................................................................3086
53.2.2 Features........................................................................................................................................................ 3088
53.2.3 Modes of operation...................................................................................................................................... 3089
53.3 External Signal Description.......................................................................................................................................... 3089
53.3.1 Overview......................................................................................................................................................3089
53.3.2 Detailed Signal Descriptions........................................................................................................................3089
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53.4 Memory Map................................................................................................................................................................ 3090
53.5 Memory Map and Registers..........................................................................................................................................3090
53.5.1 Control Descriptor Cursor 1 Register (DCU_CTRLDESCCURSOR1)......................................................3096
53.5.2 Control Descriptor Cursor 2 Register (DCU_CTRLDESCCURSOR2)......................................................3097
53.5.3 Control Descriptor Cursor 3 Register (DCU_CTRLDESCCURSOR3)......................................................3098
53.5.4 Mode Register (DCU_MODE).................................................................................................................... 3099
53.5.5 Background Register (DCU_BGND).......................................................................................................... 3101
53.5.6 Display Size Register (DCU_DISP_SIZE)..................................................................................................3102
53.5.7 Horizontal Sync Parameter Register (DCU_HSYN_PARA)...................................................................... 3102
53.5.8 Vertical Sync Parameter Register (DCU_VSYN_PARA)...........................................................................3103
53.5.9 Synchronize Polarity Register (DCU_SYNPOL)........................................................................................ 3104
53.5.10 Threshold Register (DCU_THRESHOLD)................................................................................................. 3105
53.5.11 Interrupt Status Register (DCU_INT_STATUS).........................................................................................3106
53.5.12 Interrupt Mask Register (DCU_INT_MASK)............................................................................................. 3109
53.5.13 COLBAR_1 Register (DCU_COLBAR_1).................................................................................................3111
53.5.14 COLBAR_2 Register (DCU_COLBAR_2).................................................................................................3112
53.5.15 COLBAR_3 Register (DCU_COLBAR_3).................................................................................................3112
53.5.16 COLBAR_4 Register (DCU_COLBAR_4).................................................................................................3113
53.5.17 COLBAR_5 Register (DCU_COLBAR_5).................................................................................................3114
53.5.18 COLBAR_6 Register (DCU_COLBAR_6).................................................................................................3114
53.5.19 COLBAR_7 Register (DCU_COLBAR_7).................................................................................................3115
53.5.20 COLBAR_8 Register (DCU_COLBAR_8).................................................................................................3115
53.5.21 Divide Ratio Register (DCU_DIV_RATIO)............................................................................................... 3116
53.5.22 Sign Calculation 1 Register (DCU_SIGN_CALC_1)................................................................................. 3117
53.5.23 Sign Calculation 2 Register (DCU_SIGN_CALC_2)................................................................................. 3118
53.5.24 CRC Value Register (DCU_CRC_VAL).................................................................................................... 3118
53.5.25 Parameter Error Status 1 Register (DCU_PARR_ERR_STATUS1).......................................................... 3119
53.5.26 Parameter Error Status 3 Register (DCU_PARR_ERR_STATUS3).......................................................... 3119
53.5.27 Mask Parameter Error Status 1 Register (DCU_MASK_PARR_ERR_STATUS1)................................... 3120
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53.5.28 Mask Parameter Error Status 3 Register (DCU_MASK_PARR_ERR_STATUS3)................................... 3121
53.5.29 Threshold Input 1 Register (DCU_THRESHOLD_INP_BUF_1)...............................................................3122
53.5.30 LUMA Component Register (DCU_LUMA_COMP).................................................................................3123
53.5.31 Red Chroma Components Register (DCU_CHROMA_RED).................................................................... 3124
53.5.32 Green Chroma Components Register (DCU_CHROMA_GREEN)........................................................... 3124
53.5.33 Blue Chroma Components Register (DCU_CHROMA_BLUE).................................................................3125
53.5.34 CRC Position Register (DCU_CRC_POS)..................................................................................................3125
53.5.35 Layer Interpolation Enable Register (DCU_LYR_INTPOL_EN)...............................................................3126
53.5.36 Layer Luminance Component Register (DCU_LYR_LUMA_COMP)...................................................... 3127
53.5.37 Layer Chroma Red Register (DCU_LYR_CHRM_RED)...........................................................................3128
53.5.38 Layer Chroma Green Register (DCU_LYR_CHRM_GRN)....................................................................... 3128
53.5.39 Layer Chroma Blue Register (DCU_LYR_CHRM_BLUE)....................................................................... 3129
53.5.40 Update Mode Register (DCU_UPDATE_MODE)......................................................................................3130
53.5.41 Underrun Register (DCU_UNDERRUN)....................................................................................................3131
53.5.42 Frame CRC Control (DCU_FRM_CRC_CTRL)........................................................................................ 3131
53.5.43 Frame CRC Value (DCU_FRM_CRC_VAL)............................................................................................. 3132
53.5.44 QoS Level (DCU_TX_ESCAL_LVL).........................................................................................................3132
53.5.45 Global Protection Register (DCU_GPR)..................................................................................................... 3133
53.5.46 Soft Lock Bit Layer 0 Register (DCU_SLR_L0)........................................................................................ 3134
53.5.47 Soft Lock Bit Layer 1 Register (DCU_SLR_L1)........................................................................................ 3136
53.5.48 Soft Lock Display Size Register (DCU_SLR_DISP_SIZE)........................................................................3139
53.5.49 Soft Lock Hsync/Vsync Parameter Register (DCU_SLR_HVSYNC_PARA)........................................... 3140
53.5.50 Soft Lock POL Register (DCU_SLR_POL)................................................................................................3141
53.5.51 Soft Lock L0 Transparency Register (DCU_SLR_L0_TRANSP).............................................................. 3142
53.5.52 Soft Lock L1 Transparency Register (DCU_SLR_L1_TRANSP).............................................................. 3144
53.5.53 Control Descriptor Layer 1 Register (DCU_CTRLDESCLn_1).................................................................3145
53.5.54 Control Descriptor Layer 2 Register (DCU_CTRLDESCLn_2).................................................................3146
53.5.55 Control Descriptor Layer 3 Register (DCU_CTRLDESCLn_3).................................................................3146
53.5.56 Control Descriptor Layer 4 Register (DCU_CTRLDESCLn_4).................................................................3147
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53.5.57 Control Descriptor Layer 5 Register (DCU_CTRLDESCLn_5).................................................................3149
53.5.58 Control Descriptor Layer 6 Register (DCU_CTRLDESCLn_6).................................................................3150
53.5.59 Control Descriptor Layer 8 Register (DCU_CTRLDESCLn_8).................................................................3151
53.5.60 Control Descriptor Layer 9 Register (DCU_CTRLDESCLn_9).................................................................3151
53.5.61 Control Descriptor Layer 10 Register (DCU_CTRLDESCLn_10).............................................................3152
53.6 Functional Description..................................................................................................................................................3153
53.6.1 TFT LCD panel configuration..................................................................................................................... 3153
53.6.2 Mode selection and background color......................................................................................................... 3156
53.6.3 Layer configuration and blending................................................................................................................ 3156
53.6.4 Hardware cursor...........................................................................................................................................3178
53.6.5 CLUT RAM................................................................................................................................................. 3179
53.6.6 Gamma correction........................................................................................................................................3180
53.6.7 Temporal Dithering......................................................................................................................................3181
53.7 Timing, Error and Interrupt Management.....................................................................................................................3182
53.7.1 Synchronizing to panel frame rate............................................................................................................... 3182
53.7.2 Managing the FIFOs and DMA activity...................................................................................................... 3183
53.7.3 Arbitration and DMA scheduling................................................................................................................ 3185
53.7.4 Error detection..............................................................................................................................................3186
53.7.5 Interrupt generation......................................................................................................................................3187
53.8 Register protection........................................................................................................................................................3188
53.8.1 Operation of scheme.................................................................................................................................... 3188
53.8.2 List of protected registers.............................................................................................................................3189
53.9 Safety Mode..................................................................................................................................................................3189
53.9.1 CRC Area Description................................................................................................................................. 3191
53.10 2D-ACE Initialization...................................................................................................................................................3193
53.11 Glossary........................................................................................................................................................................ 3194
Chapter 54
GC3000 Graphics Processing Unit (GC3000)
54.1 Introduction...................................................................................................................................................................3195
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54.2 GC3000 architecture..................................................................................................................................................... 3196
54.2.1 GPU 3D hardware features.......................................................................................................................... 3196
54.2.2 GPU core design description........................................................................................................................3196
54.2.3 GPU core API support and architecture features......................................................................................... 3198
54.2.4 OpenCL support...........................................................................................................................................3199
54.3 GC3000 driver architecture overview...........................................................................................................................3199
54.3.1 Graphics driver software stack.....................................................................................................................3199
54.3.2 3D rendering................................................................................................................................................ 3200
54.3.3 Commands and Data.................................................................................................................................... 3201
54.3.4 Threads and Contexts...................................................................................................................................3201
54.3.5 Driver GAL (Graphics Abstraction Layer)..................................................................................................3202
Chapter 55
DEC200 Compression/Decompression Engine
55.1 Introduction...................................................................................................................................................................3203
55.2 Hardware features......................................................................................................................................................... 3204
55.2.1 Encode and decode hardware features......................................................................................................... 3204
55.3 Memory Map and Register Description........................................................................................................................3204
55.3.1 DEC200_gcregDECReadConfign............................................................................................................... 3207
55.3.2 DEC200_gcregDECWriteConfign...............................................................................................................3208
55.3.3 DEC200_gcregDECReadBufferBasen........................................................................................................ 3209
55.3.4 DEC200_gcregDECReadCacheBasen.........................................................................................................3210
55.3.5 DEC200_gcregDECWriteBufferBasen....................................................................................................... 3210
55.3.6 DEC200_gcregDECWriteCacheBasen........................................................................................................3210
55.3.7 DEC200_gcregDECControl.........................................................................................................................3211
55.3.8 DEC200_gcregDECIntrAcknowledge.........................................................................................................3213
55.3.9 DEC200_gcregDECIntrEnbl....................................................................................................................... 3214
55.3.10 DEC200_gcDECTotalReadsIn.................................................................................................................... 3215
55.3.11 DEC200_gcDECTotalWritesIn................................................................................................................... 3215
55.3.12 DEC200_gcDECTotalReadBurstsIn............................................................................................................3216
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55.3.13 DEC200_gcDECTotalWriteBurstsIn...........................................................................................................3216
55.3.14 DEC200_gcDECTotalReadsReqIn..............................................................................................................3216
55.3.15 DEC200_gcDECTotalWritesReqIn............................................................................................................. 3217
55.3.16 DEC200_gcDECTotalReadLastsIn............................................................................................................. 3217
55.3.17 DEC200_gcDECTotalWriteLastsIn.............................................................................................................3218
55.3.18 DEC200_gcDECTotalReadsOUT............................................................................................................... 3218
55.3.19 DEC200_gcDECTotalWritesOUT...............................................................................................................3218
55.3.20 DEC200_gcDECTotalReadBurstsOUT.......................................................................................................3219
55.3.21 DEC200_gcDECTotalWriteBurstsOUT......................................................................................................3219
55.3.22 DEC200_gcDECTotalReadsReqOUT......................................................................................................... 3220
55.3.23 DEC200_gcDECTotalWritesReqOUT........................................................................................................ 3220
55.3.24 DEC200_gcDECTotalReadLastsOUT.........................................................................................................3220
55.3.25 DEC200_gcDECTotalWriteLastsOUT........................................................................................................3221
Chapter 56
ADAS Camera Vision Flow
56.1 Introduction...................................................................................................................................................................3223
56.2 Components and Data Flow..........................................................................................................................................3224
56.3 Use Case........................................................................................................................................................................3225
Chapter 57
APEX-CL Image Cognition Processor
57.1 Chip-specific APEX-CL Information...........................................................................................................................3229
57.2 Introduction...................................................................................................................................................................3229
57.3 Overview.......................................................................................................................................................................3229
57.4 Feature Summary..........................................................................................................................................................3229
57.5 Acronyms and Abbreviations....................................................................................................................................... 3231
57.6 Global Software Interface.............................................................................................................................................3231
57.7 APU Architecture..........................................................................................................................................................3232
57.7.1 The Computational Units (CU)....................................................................................................................3233
57.7.2 CU Registers................................................................................................................................................ 3233
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57.7.3 Shifter/Rotator..............................................................................................................................................3233
57.7.4 CU-to-CU Shifter.........................................................................................................................................3234
57.7.5 Multiplier..................................................................................................................................................... 3234
57.7.6 Load/Store Unit............................................................................................................................................3235
57.8 CMEM Interface........................................................................................................................................................... 3235
57.9 DMEM FIFO................................................................................................................................................................ 3236
57.10 DMA Subsystem...........................................................................................................................................................3236
57.11 Sequencer......................................................................................................................................................................3237
57.12 Horizontal Resizer/Scaler (HRSZ)............................................................................................................................... 3238
57.13 Features.........................................................................................................................................................................3238
Chapter 58
High Performance Shared Memory Interconnect (HPSMI)
58.1 Chip-specific HPSMI information................................................................................................................................3239
58.1.1 AXI Master Connections............................................................................................................................. 3239
58.1.2 Stream DMA Master Connections...............................................................................................................3240
58.1.3 SRAM contents retention on a functional reset........................................................................................... 3241
58.2 Introduction...................................................................................................................................................................3241
58.3 Feature List................................................................................................................................................................... 3242
58.4 Block diagram...............................................................................................................................................................3243
58.5 Memory Map and Register Definition..........................................................................................................................3244
58.5.1 HPSMI Global Control Register (HPSMI_GBL_CTRL)............................................................................3249
58.5.2 HPSMI MPU Address Select 0 Register (HPSMI_MPU_SEL0)................................................................3250
58.5.3 HPSMI MPU Address Select 1 Register (HPSMI_MPU_SEL1)................................................................3250
58.5.4 HPSMI MPU Address Select 2 Register (HPSMI_MPU_SEL2)................................................................3251
58.5.5 HPSMI MPU Address Select 3 Register (HPSMI_MPU_SEL3)................................................................3251
58.5.6 HPSMI Stream DMA Master Priority Change Register (HPSMI_PRIO_CHANGE)................................ 3252
58.5.7 HPSMI LSB2AXI Master 0 Cycle counter Register (HPSMI_PROFILE_LSB2AXICYCCNTR_0)........3253
58.5.8 HPSMI LSB2AXI Master 1 Cycle Counter Value Register
(HPSMI_PROFILE_LSB2AXICYCCNTR_1)........................................................................................... 3253
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58.5.9 HPSMI Profile Cycle Counter Overflow Register (HPSMI_PROFILE_CYCCNTR_OVF)......................3254
58.5.10 HPSMI AXI Profile Stop Register (HPSMI_PROFILE_STOP).................................................................3256
58.5.11 HPSMI Interrupt Enable 0 Register (HPSMI_INTR_EN0)........................................................................ 3257
58.5.12 HPSMI Interrupt Enable 1 Register (HPSMI_INTR_EN1)........................................................................ 3258
58.5.13 HPSMI AXI Profile Start Register (HPSMI_PROFILE_START)..............................................................3260
58.5.14 HPSMI AXI Profile Reset Register (HPSMI_PROFILE_RESET).............................................................3261
58.5.15 HPSMI AXI Profile Freeze Register (HPSMI_PROFILE_FREEZE).........................................................3263
58.5.16 HPSMI AXI Profile Decrement Value Register (HPSMI_PROFILE_DECVAL)......................................3264
58.5.17 HPSMI AXI Profile Decrement Counter Information Register
(HPSMI_PROFILE_DECVAL_CNTRNUM)............................................................................................ 3265
58.5.18 HPSMI AXI Master 0 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_0)............................................................................................... 3266
58.5.19 HPSMI AXI Master 0 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_0).............................................................................................. 3266
58.5.20 HPSMI AXI Master 1 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_1)............................................................................................... 3267
58.5.21 HPSMI AXI Master 1 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_1).............................................................................................. 3267
58.5.22 HPSMI AXI Master 2 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_2)............................................................................................... 3268
58.5.23 HPSMI AXI Master 2 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_2).............................................................................................. 3268
58.5.24 HPSMI AXI Master 3 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_3)............................................................................................... 3269
58.5.25 HPSMI AXI Master 3 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_3).............................................................................................. 3269
58.5.26 HPSMI AXI Master 4 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_4)............................................................................................... 3270
58.5.27 HPSMI AXI Master 4 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_4).............................................................................................. 3270
58.5.28 HPSMI AXI Master 5 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_5)............................................................................................... 3271
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58.5.29 HPSMI AXI Master 5 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_5).............................................................................................. 3271
58.5.30 HPSMI AXI Master 6 Read Port Profile Counter Value Register
(HPSMI_PROFILE_AXIRDCNTRVAL_6)............................................................................................... 3272
58.5.31 HPSMI AXI Master 6 Write Port Profile Counter Value Register
(HPSMI_PROFILE_AXIWRCNTRVAL_6).............................................................................................. 3272
58.5.32 HPSMI LSB2AXI Master 0 Read Port Profile Counter Value Register
(HPSMI_PROFILE_LSB2AXIRDCNTRVAL_0)......................................................................................3273
58.5.33 HPSMI LSB2AXI Master 0 Write Port Profile Counter Value Register
(HPSMI_PROFILE_LSB2AXIWRCNTRVAL_0).....................................................................................3273
58.5.34 HPSMI LSB2AXI Master 1 Read Port Profile Counter Value Register
(HPSMI_PROFILE_LSB2AXIRDCNTRVAL_1)......................................................................................3274
58.5.35 HPSMI LSB2AXI Master 1 Write Port Profile Counter Value Register
(HPSMI_PROFILE_LSB2AXIWRCNTRVAL_1).....................................................................................3274
58.5.36 HPSMI AXI Master 0 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_0).......3275
58.5.37 HPSMI AXI Master 1 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_1).......3275
58.5.38 HPSMI AXI Master 2 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_2).......3276
58.5.39 HPSMI AXI Master 3 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_3).......3276
58.5.40 HPSMI AXI Master 4 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_4).......3277
58.5.41 HPSMI AXI Master 5 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_5).......3277
58.5.42 HPSMI AXI Master 6 Cycle Counter Value Register (HPSMI_PROFILE_AXICYCCNTRVAL_6).......3278
58.5.43 HPSMI Stream DMA Read Pipeline Level 31_0 Register (HPSMI_RD_PL_LVL_31_0)........................ 3278
58.5.44 HPSMI Stream DMA Read Pipeline Level 63_32 Register (HPSMI_RD_PL_LVL_63_32).................... 3279
58.5.45 HPSMI Stream DMA Write Pipeline Level 31_0 Register (HPSMI_WR_PL_LVL_31_0)...................... 3279
58.5.46 HPSMI Stream DMA Write Pipeline Level 63_32 Register (HPSMI_WR_PL_LVL_63_32).................. 3280
58.5.47 HPSMI Stream DMA Read Address Error 0 Register (HPSMI_DSRD_ADDRESS_ERROR0)...............3280
58.5.48 HPSMI Stream DMA Read Address Error 1 Register (HPSMI_DSRD_ADDRESS_ERROR1)...............3281
58.5.49 HPSMI Stream DMA Write Address Error 0 Register (HPSMI_DSWR_ADDRESS_ERROR0).............3281
58.5.50 HPSMI Stream DMA Write Address Error 1 Register (HPSMI_DSWR_ADDRESS_ERROR1).............3282
58.5.51 HPSMI Addressing Error Address Register (HPSMI_ADDR_ERROR_ADDRVAL).............................. 3282
58.5.52 HPSMI Addressing Error Information Register (HPSMI_ADDR_ERROR_INFO).................................. 3283
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58.5.53 HPSMI Stream DMA Write MPU Error 0 Register (HPSMI_WRMPU_ERROR0)..................................3284
58.5.54 HPSMI Stream DMA Write MPU Error 1 Register (HPSMI_WRMPU_ERROR1)..................................3285
58.5.55 HPSMI MPU Error Address Register (HPSMI_WRMPU_ERROR_ADDR)............................................ 3285
58.5.56 HPSMI MPU Error Information Register (HPSMI_WRMPU_ERROR_INFO)........................................ 3286
58.5.57 HPSMI_PM_ERROR_1_2.......................................................................................................................... 3287
58.5.58 HPSMI_PM_ERROR_ADDR_1_2............................................................................................................. 3287
58.5.59 HPSMI_PM_ERROR_INFO_1_2............................................................................................................... 3288
58.5.60 HPSMI Error Inject Register (HPSMI_ECC_ERR_INJECT).....................................................................3289
58.5.61 HPSMI ECC Error Counter Reset Mask (HPSMI_ECC_ERRCNTR_MASK)..........................................3290
58.5.62 Single Error counter for SEG1_2 Register (HPSMI_ECC_SINGLE_ERRCNTR_1_2)............................ 3292
58.5.63 Uncorrectable Error Counter for Seg1_2 Register (HPSMI_ECC_UNCORR_ERRCNTR_1_2)..............3294
58.5.64 HPSMI ECC Error Address Segment 1 Register (HPSMI_ECC_ERRADDR_SEG1).............................. 3295
58.5.65 HPSMI ECC Error Data 31:0 for Segment 1 Register (HPSMI_ECC_ERRDATA0_SEG1).................... 3296
58.5.66 HPSMI ECC Error Data 63:32 for Segment 1 Register (HPSMI_ECC_ERRDATA1_SEG1).................. 3296
58.5.67 HPSMI ECC Error Information Segment 1 Register (HPSMI_ECC_ERRINFO_SEG1).......................... 3297
58.5.68 HPSMI ECC Error Address Segment 2 Register (HPSMI_ECC_ERRADDR_SEG2).............................. 3298
58.5.69 HPSMI ECC Error Data 31:0 for Segment 2 Register (HPSMI_ECC_ERRDATA0_SEG2).................... 3298
58.5.70 HPSMI ECC Error Data 63:32 for Segment 2 Register (HPSMI_ECC_ERRDATA1_SEG2).................. 3299
58.5.71 HPSMI ECC Error Information Segment 2 Register (HPSMI_ECC_ERRINFO_SEG2).......................... 3300
58.5.72 HPSMI_ECC_ERROCCURRED_SEG1_2.................................................................................................3301
58.5.73 HPSMI ECC Error Address for Even Banks of Segment0 Register
(HPSMI_ECC_ERRADDR_SEG0_EVEN)................................................................................................3302
58.5.74 HPSMI ECC Error Address for Odd Banks of Segment0 Register
(HPSMI_ECC_ERRADDR_SEG0_ODD)..................................................................................................3302
58.5.75 HPSMI ECC Error Data 31:0 for even banks of Segment0 Register
(HPSMI_ECC_ERRDATA0_SEG0_EVEN)..............................................................................................3303
58.5.76 HPSMI ECC Error Data 63:32 for even banks of Segment0 Register
(HPSMI_ECC_ERRDATA1_SEG0_EVEN)..............................................................................................3303
58.5.77 HPSMI ECC Error Data 31:0 for odd banks of Segment0 Register
(HPSMI_ECC_ERRDATA0_SEG0_ODD)................................................................................................3304
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58.5.78 HPSMI ECC Error Data 63:32 for odd banks of Segment0 Register
(HPSMI_ECC_ERRDATA1_SEG0_ODD)................................................................................................3304
58.5.79 HPSMI ECC Error Information Segment 0 Register (HPSMI_ECC_ERRINFO_SEG0).......................... 3305
58.5.80 HPSMI_ECC_ERROCCURED_SEG0....................................................................................................... 3307
58.5.81 ECC Single Error Counter for Odd and Even Bank Register
(HPSMI_ECC_SINGLE_ERRCNTR_ODD_EVEN_0)............................................................................. 3308
58.5.82 ECC Uncorectable Error Conter for Odd and Even Bank Register
(HPSMI_ECC_UNCORR_ERRCNTR_ODD_EVEN_0)...........................................................................3311
58.5.83 HPSMI_PM_ERROR_0.............................................................................................................................. 3313
58.5.84 HPSMI_PM_ERROR_ADDR_0................................................................................................................. 3313
58.5.85 HPSMI_PM_ERROR_INFO_0................................................................................................................... 3314
58.5.86 HPSMI_POWMOD_CTRL_0..................................................................................................................... 3315
58.5.87 HPSMI_POWMOD_CTRL_0_8_11........................................................................................................... 3316
58.5.88 HPSMI_POWMOD_CTRL_1_2................................................................................................................. 3316
58.5.89 HPSMI_QOS_PRIORITY........................................................................................................................... 3317
58.5.90 Interconnect Parity Checking Global Enable Register (HPSMI_IPCGE)................................................... 3318
58.5.91 Interconnect Parity Read Checking Enable Register (HPSMI_IPRCE)......................................................3319
58.5.92 HPSMI_IPWCE........................................................................................................................................... 3321
58.5.93 Interconnect Parity Write Address Checking Enable Register (HPSMI_IPWACE)...................................3323
58.5.94 Interconnect Parity Read Address Checking Enable Register (HPSMI_IPRACE).....................................3325
58.5.95 Interconnect Parity Checking Global Injection Enable Register (HPSMI_IPCGIE).................................. 3327
58.6 Functional Description..................................................................................................................................................3327
58.7 Feature Description:......................................................................................................................................................3331
58.7.1 Stream DMA Master Priority.......................................................................................................................3331
58.7.2 NIC301 functional details for HPSMI MSB................................................................................................3332
58.7.3 NIC Integrity Check(parity).........................................................................................................................3338
58.7.4 Error Correcting Code(ECC)....................................................................................................................... 3341
58.7.5 Power Modes................................................................................................................................................3347
58.7.6 Memory Protection Unit.............................................................................................................................. 3347
58.7.7 Error injection.............................................................................................................................................. 3348
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58.8 Debug Features............................................................................................................................................................. 3350
58.8.1 Profiling:...................................................................................................................................................... 3350
58.8.2 Debug Watchpoints......................................................................................................................................3351
58.9 Interrupts, Error Reporting and Error Response...........................................................................................................3368
58.10 Implementation Procedure............................................................................................................................................3372
58.11 HTM Implementation Procedure.................................................................................................................................. 3373
Chapter 59
MIPICSI2
59.1 Chip-specific MIPICSI2 Information........................................................................................................................... 3375
59.2 About this module.........................................................................................................................................................3375
59.2.1 Definition..................................................................................................................................................... 3375
59.2.2 MIPICSI2 Copyright....................................................................................................................................3376
59.2.3 Features........................................................................................................................................................ 3376
59.2.4 MIPICSI2 compliance..................................................................................................................................3377
59.2.5 Modes of operation...................................................................................................................................... 3377
59.2.6 Clocking....................................................................................................................................................... 3377
59.3 MIPICSI2......................................................................................................................................................................3377
59.3.1 MIPICSI2 block diagram............................................................................................................................. 3377
59.3.2 MIPICSI2 components.................................................................................................................................3378
59.3.3 MIPICSI2 signals.........................................................................................................................................3378
59.4 DPHY RX..................................................................................................................................................................... 3379
59.4.1 DPHY RX block diagram............................................................................................................................ 3379
59.4.2 DPHY RX components................................................................................................................................3380
59.4.3 DPHY RX signals........................................................................................................................................ 3380
59.4.4 Calibrator..................................................................................................................................................... 3381
59.4.5 Receiver....................................................................................................................................................... 3381
59.5 RX controller core.........................................................................................................................................................3382
59.5.1 RX controller core block diagram................................................................................................................3382
59.5.2 RX controller core components................................................................................................................... 3383
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59.5.3 RX controller core signals............................................................................................................................3384
59.6 HPSMI gasket............................................................................................................................................................... 3384
59.6.1 MIPICSI2 subsystem output data format.....................................................................................................3384
59.7 Using MIPICSI2........................................................................................................................................................... 3385
59.7.1 Initializing the MIPICSI2 subsystem...........................................................................................................3385
59.7.2 Calculate the required settle time for DPHY RX.........................................................................................3385
59.7.3 Override auto calibration values.................................................................................................................. 3386
59.7.4 Place receiver in high-speed mode...............................................................................................................3386
59.7.5 Place receiver in ultra low-power mode...................................................................................................... 3387
59.7.6 Video Data Capture......................................................................................................................................3387
59.7.7 Embedded Data Capture.............................................................................................................................. 3389
59.7.8 Understanding MIPICSI2 compliant error levels........................................................................................ 3392
59.7.9 Decipher error sources and interrupt signals................................................................................................3393
59.7.10 Interrupts...................................................................................................................................................... 3394
59.8 Memory map and register definition.............................................................................................................................3395
59.8.1 RX Controller Configuration Register (MIPICSI2_CONC)....................................................................... 3399
59.8.2 PHY Configuration Register (MIPICSI2_PHYC).......................................................................................3400
59.8.3 Clock Configuration Status Register (MIPICSI2_CLKCS)........................................................................ 3401
59.8.4 D-PHY Lane 0 Configuration Status Register (MIPICSI2_LAN0CS)....................................................... 3403
59.8.5 D-PHY Data LANE 1 Configuration Status Register (MIPICSI2_LAN1CS)............................................ 3405
59.8.6 LANE 2 Configuration/Status Register (MIPICSI2_LAN2CS)..................................................................3407
59.8.7 LANE3 Configuration Status Register (MIPICSI2_LAN3CS)................................................................... 3409
59.8.8 External Resistor Configuration Status Register (MIPICSI2_RESCS).......................................................3411
59.8.9 Status Register (MIPICSI2_SR).................................................................................................................. 3412
59.8.10 DATAID VC Report Register (MIPICSI2_DATAVCR)............................................................................3413
59.8.11 Protocol and Packet Error Register (MIPICSI2_ERRPPREG)................................................................... 3414
59.8.12 Error Position (MIPICSI2_ERRPOS)..........................................................................................................3415
59.8.13 Protocol Packet Error Interrupt Enable (MIPICSI2_ERPPINTEN)............................................................ 3416
59.8.14 PHY Error Report Register (MIPICSI2_ERRPHY)....................................................................................3417
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59.8.15 Phy Error Interrupt Enable Register (MIPICSI2_ERPHYIE)..................................................................... 3420
59.8.16 RX Enable Register (MIPICSI2_RXEN).................................................................................................... 3422
59.8.17 Alpha Value Register (MIPICSI2_ALPHAVAL)....................................................................................... 3423
59.8.18 Start Pointer for Virtual Channel data in SRAM (MIPICSI2_SRTPTRn).................................................. 3423
59.8.19 Buffer Line Length for Virtual Channel Data (MIPICSI2_BUFLLENn)................................................... 3424
59.8.20 LINE LENGTH for Virtual Channel data (MIPICSI2_LINLENn).............................................................3425
59.8.21 NUMBER OF LINES ON A VC (MIPICSI2_NUMLINEn)...................................................................... 3426
59.8.22 Next Line In SRAM for a particular VC (MIPICSI2_NXTLINn).............................................................. 3427
59.8.23 Total Lines received for Virtual Channel (MIPICSI2_TOTLINn)..............................................................3427
59.8.24 Expected Number of Lines on a VC (MIPICSI2_EXPCTDLn)..................................................................3428
59.8.25 Lines Per Done Indication for a VC (MIPICSI2_LPDIn)........................................................................... 3428
59.8.26 Stream Data Type for VC (MIPICSI2_STRMDTn)....................................................................................3429
59.8.27 ERROR LENGTH (MIPICSI2_ERRLENn)............................................................................................... 3430
59.8.28 Error Line (MIPICSI2_ERRLINEn)............................................................................................................3430
59.8.29 Enable Channel (MIPICSI2_ENABLECH).................................................................................................3431
59.8.30 Interrupt Enable on Virtual Channel (MIPICSI2_INTRENVC)................................................................. 3432
59.8.31 Interrupt Status For Virtual Channel (MIPICSI2_INTRSVC).................................................................... 3434
59.8.32 Embedded Data Start Pointer (MIPICSI2_EMBEDSP).............................................................................. 3436
59.8.33 Embedded Data Length (MIPICSI2_EMBEDLEN)....................................................................................3436
59.8.34 Embedded Data Next Pointer (MIPICSI2_EMBEDNP)............................................................................. 3437
59.8.35 Embedded Data Enable (MIPICSI2_EMBEDENB)....................................................................................3438
59.8.36 Embedded data Received Count (MIPICSI2_EMBEDRCVD)...................................................................3439
59.8.37 Embedded Data Master Channel (MIPICSI2_EMBMSTR)........................................................................3440
59.8.38 Embedded Data Interrupt Enable (MIPICSI2_EMBEDIE).........................................................................3441
59.8.39 Embedded Data Interrupt Status Register (MIPICSI2_EMBEDINTS).......................................................3442
59.8.40 Embedded Lines for genertaion of first interrupt (MIPICSI2_EMBEDIRQ1)........................................... 3443
59.8.41 Embedded Lines after which second interrpt is generated (MIPICSI2_EMBEDIRQ2)............................. 3443
59.9 NOTICE OF DISCLAIMER........................................................................................................................................ 3444
Chapter 60
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H264 Encoder (H264_ENC)
60.1 Chip-specific H264_ENC information......................................................................................................................... 3447
60.2 Introduction...................................................................................................................................................................3447
60.2.1 Features........................................................................................................................................................ 3447
60.2.2 Abbreviations and Acronyms.......................................................................................................................3448
60.2.3 Block Diagram............................................................................................................................................. 3448
60.2.4 Modes of Operation..................................................................................................................................... 3449
60.2.5 Interrupts...................................................................................................................................................... 3451
60.3 Memory map /Register Definition................................................................................................................................3454
60.3.1 Module Configuration Register (H264_ENC_MCR).................................................................................. 3456
60.3.2 Video Configuration Register (H264_ENC_VCR)..................................................................................... 3458
60.3.3 Video Input Alarm Register (H264_ENC_VI_ALARM)............................................................................3459
60.3.4 Fetch Macroblock Row Register (H264_ENC_FETCH_MBRW)..............................................................3460
60.3.5 Video Input Circular Buffer Luma Start Address Register (H264_ENC_VI_CBUF_Y_ADDR).............. 3461
60.3.6 Video Input Circular Buffer Cb Start Address Register (H264_ENC_VI_CBUF_CB_ADDR)................ 3461
60.3.7 Video Input Circular Buffer Cr Start Address Register (H264_ENC_VI_CBUF_CR_ADDR)................. 3462
60.3.8 Video Input Number of Lines Register (H264_ENC_VI_NRLINES)........................................................ 3463
60.3.9 Rate Flow Control Register (H264_ENC_RATE_FLOW_CTRL)............................................................. 3464
60.3.10 Output Circular Buffer Start Address Register (H264_ENC_OUT_CBUF_START_ADDR)...................3464
60.3.11 Output Circular Buffer End Address Register (H264_ENC_OUT_CBUF_END_ADDR)........................ 3465
60.3.12 Ouput Circular Buffer Alarm Address Register (H264_ENC_OUT_CBUF_ALARM_ADDR)............... 3466
60.3.13 Output Circular Buffer Current Address Register (H264_ENC_OUT_CBUF_CURR_ADDR)................3467
60.3.14 Output Circular Buffer Vend Address Register (H264_ENC_OUT_CBUF_VEND_ADDR)................... 3468
60.3.15 Line Counter Status Register (H264_ENC_LINE_CNTR_STAT)............................................................. 3469
60.3.16 Interrupt Status Register (H264_ENC_ISR)................................................................................................3470
60.3.17 Interrupt Enable Register (H264_ENC_IER).............................................................................................. 3472
60.3.18 Testline Configuration Register (H264_ENC_TESTLINE_CFG).............................................................. 3474
60.3.19 Testline Start Location Register (H264_ENC_TESTLINE_STRT_LOC)..................................................3475
60.3.20 Testline Luma Value Register (H264_ENC_TESTLINE_LUMA_VAL).................................................. 3476
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60.3.21 Testline Chroma Cb Value Register (H264_ENC_TESTLINE_CB_VAL)................................................3477
60.3.22 Testline Chroma Cr Value Register (H264_ENC_TESTLINE_CR_VAL)................................................ 3478
60.3.23 ULLVC Frame Rate Register (H264_ENC_ULLVC_FRAME_RATE).................................................... 3478
60.3.24 ULLVC Quantization Parameter Initial Register (H264_ENC_ULLVC_QP_INIT)..................................3479
60.3.25 ULLVC Quantization Parameter Range Register (H264_ENC_ULLVC_QP_RANGE)........................... 3479
60.3.26 ULLVC Bits Per Macroblock Row Register (H264_ENC_ULLVC_BITS_PER_MB_ROW)..................3480
60.3.27 ULLVC Fallback QP Limit Register (H264_ENC_ULLVC_QP_FALLBACK_LIMIT).......................... 3481
60.3.28 ULLVC Increment QP Register (H264_ENC_ULLVC_QP_INC).............................................................3481
60.3.29 ULLVC Increment Threshold Register (H264_ENC_ULLVC_QP_INC_THLDn)................................... 3483
60.3.30 ULLVC Decrement QP Register (H264_ENC_ULLVC_QP_DEC).......................................................... 3483
60.3.31 ULLVC Decrement Threshold Register (H264_ENC_ULLVC_QP_DEC_THLDn).................................3485
60.3.32 ULLVC Wait Frames Register (H264_ENC_ULLVC_WAIT_FRAMES)................................................ 3486
60.3.33 ULLVC Disable DBF Register (H264_ENC_ULLVC_DISABLE_DBF)................................................. 3486
60.3.34 ULLVC Bitrate Stream Register (H264_ENC_ULLVC_BITRATE_STREAM).......................................3487
60.4 Functional Description..................................................................................................................................................3487
60.4.1 Input Stream DMA.......................................................................................................................................3487
60.4.2 Encoder Core Functional Description..........................................................................................................3491
60.4.3 Output Stream DMA....................................................................................................................................3497
60.4.4 Data Mode Chroma......................................................................................................................................3500
60.4.5 Testline Feature............................................................................................................................................3501
60.4.6 Rate Flow Control........................................................................................................................................3502
60.4.7 Endianess..................................................................................................................................................... 3504
60.5 Encoder SW flow and handshaking with Cortex-A53 and Sequencer......................................................................... 3505
60.5.1 Encoder Input...............................................................................................................................................3505
60.5.2 Encoder Output............................................................................................................................................ 3506
60.5.3 Encoder Input and Output............................................................................................................................ 3507
60.6 Use Case........................................................................................................................................................................3507
Chapter 61
H264 Decoder (H264_DEC)
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61.1 Chip-specific H264_DEC information......................................................................................................................... 3509
61.2 Performance Considerations......................................................................................................................................... 3509
61.3 Introduction...................................................................................................................................................................3510
61.3.1 Features........................................................................................................................................................ 3510
61.3.2 Abbreviations and Acronyms.......................................................................................................................3511
61.3.3 Block Diagram............................................................................................................................................. 3511
61.4 Modes of Operation...................................................................................................................................................... 3513
61.5 Interrupts.......................................................................................................................................................................3516
61.6 Memory map /Register Definition................................................................................................................................3517
61.6.1 MODULE CONFIGURATION REGISTER (H264_DEC_MCR)............................................................. 3524
61.6.2 TIMEOUT CONFIGURATION REGISTER (H264_DEC_TIMEOUT_CFG)......................................... 3528
61.6.3 STREAM VIDEO CONFIGURATION REGISTER (H264_DEC_STRn_VCR)......................................3529
61.6.4 STREAM PACKET ADDRESS REGISTER (H264_DEC_STR_PKT_ADDR).......................................3530
61.6.5 STREAM TRIGGER AND PACKET CONFIGURATION REGISTER
(H264_DEC_STR_TRIG_PKT_CFG)........................................................................................................ 3531
61.6.6 STREAM PACKET FIFO WATERMARK REGISTER (H264_DEC_STR_PKT_FIFO_WMRK).........3532
61.6.7 STREAM 0 and 1 PACKET FIFO STATUS REGISTER (H264_DEC_STR_01_PKT_FIFO_STAT).... 3532
61.6.8 STREAM 2 and 3 PACKET FIFO STATUS REGISTER (H264_DEC_STR_23_PKT_FIFO_STAT).... 3535
61.6.9 STREAM 0 PACKET STATUS REGISTER (H264_DEC_STR_0_PKTn_STATUS)............................. 3538
61.6.10 STREAM 1 PACKET STATUS REGISTER (H264_DEC_STR_1_PKTn_STATUS)............................. 3540
61.6.11 STREAM 2 PACKET STATUS REGISTER (H264_DEC_STR_2_PKTn_STATUS)............................. 3542
61.6.12 STREAM 3 PACKET STATUS REGISTER (H264_DEC_STR_3_PKTn_STATUS)............................. 3544
61.6.13 VIDEO OUTPUT STREAM LUMA ADDRESS REGISTER (H264_DEC_VO_STRn_Y_ADDR)....... 3545
61.6.14 VIDEO OUTPUT STREAM Cb ADDRESS REGISTER (H264_DEC_VO_STRn_CB_ADDR)............3546
61.6.15 VIDEO OUTPUT STREAM Cr ADDRESS REGISTER (H264_DEC_VO_STRn_CR_ADDR).............3546
61.6.16 VIDEO OUTPUT STREAM NUMBER OF LINES REGISTER (H264_DEC_VO_STRn_NRLINES).. 3547
61.6.17 RATE FLOW CONTROL REGISTER (H264_DEC_RATE_FLOW_CNTRL)....................................... 3548
61.6.18 LINE COUNT STATUS REGISTER (H264_DEC_LINE_CNT_STAT)..................................................3549
61.6.19 STATUS REGISTER (H264_DEC_STAT)................................................................................................3550
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61.6.20 INTERRUPT STATUS REGISTER (H264_DEC_ISR).............................................................................3552
61.6.21 INTERRUPT ENABLE REGISTER (H264_DEC_IER)............................................................................3556
61.6.22 TESTLINE CONFIGURATION REGISTER (H264_DEC_TESTLINE_CFG)........................................ 3558
61.6.23 TESTLINE PIXEL LOCATION REGISTER (H264_DEC_TESTLINE_PXL_LOC).............................. 3559
61.6.24 TESTLINE STREAM LUMA PIXEL VALUE (H264_DEC_TESTLINE_STRn_LUMA_VAL)............3560
61.6.25 TESTLINE STREAM Cb PIXEL VALUE REGISTER (H264_DEC_TESTLINE_STRn_CB_VAL)..... 3561
61.6.26 TESTLINE STREAM Cr PIXEL VALUE REGISTER (H264_DEC_TESTLINE_STRn_CR_VAL)......3561
61.6.27 ELLVC CONFIGURATION REGISTER (H264_DEC_ELLVC_CFG)....................................................3562
61.6.28 ELLVC REFERENCE ADDRESS CHANNEL REGISTER (H264_DEC_ELLVC_REF_ADDR_CHn)3563
61.6.29 ELLVC DEBUG FRAME CYCLE COUNTER THRESHOLD REGISTER
(H264_DEC_ELLVC_DBG_FRAME_CYC_CNT_THRn).......................................................................3564
61.6.30 ELLVC STATE REGISTER (H264_DEC_ELLVC_STATE)................................................................... 3565
61.6.31 ELLVC PIC BIT REGISTER (H264_DEC_ELLVC_PIC_BIT)................................................................3566
61.6.32 ELLVC PIC WIDTH IN MBS REGISTER (H264_DEC_ELLVC_PIC_WIDTH_IN_MBS)...................3568
61.6.33 ELLVC PIC HEIGHT IN MBS REGISTER (H264_DEC_ELLVC_PIC_HEIGHT_IN_MBS)................3568
61.6.34 ELLVC PIC CROP LEFT CHANNEL 0, 1 REGISTER
(H264_DEC_ELLVC_PIC_CROP_LEFT_CH_01)................................................................................... 3569
61.6.35 ELLVC PIC CROP LEFT CHANNEL 2, 3 REGISTER
(H264_DEC_ELLVC_PIC_CROP_LEFT_CH_23)................................................................................... 3570
61.6.36 ELLVC PIC CROP RIGHT CHANNEL 0, 1 REGISTER
(H264_DEC_ELLVC_PIC_CROP_RGHT_CH_01).................................................................................. 3570
61.6.37 ELLVC PIC CROP RIGHT CHANNEL 2, 3 REGISTER
(H264_DEC_ELLVC_PIC_CROP_RGHT_CH_23).................................................................................. 3571
61.6.38 ELLVC PIC CROP TOP CHANNEL 0, 1 REGISTER
(H264_DEC_ELLVC_PIC_CROP_TOP_CH_01)..................................................................................... 3572
61.6.39 ELLVC PIC CROP TOP CHANNEL 2, 3 REGISTER
(H264_DEC_ELLVC_PIC_CROP_TOP_CH_23)..................................................................................... 3572
61.6.40 ELLVC PIC CROP BOTTOM CHANNEL 0, 1 REGISTER
(H264_DEC_ELLVC_PIC_CROP_BTTM_CH_01)..................................................................................3573
61.6.41 ELLVC PIC CROP BOTTOM CHANNEL 2, 3 REGISTER
(H264_DEC_ELLVC_PIC_CROP_BTTM_CH_23)..................................................................................3574
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61.6.42 ELLVC PIC PARAM VALID REGISTER (H264_DEC_ELLVC_PIC_PARAM_VLD).........................3575
61.6.43 ELLVC PICTURE ORDER COUNT VALUE REGISTER (H264_DEC_ELLVC_POC_VALUE)........ 3576
61.6.44 ELLVC STATUS REGISTER (H264_DEC_ELLVC_STAT)................................................................... 3577
61.7 Functional Description..................................................................................................................................................3578
61.7.1 Input Stream DMA.......................................................................................................................................3578
61.7.2 Decoder Core............................................................................................................................................... 3579
61.7.3 Output Stream DMA....................................................................................................................................3581
61.8 Data Mode Chroma.......................................................................................................................................................3585
61.9 Testline..........................................................................................................................................................................3585
61.10 Rate Flow Control.........................................................................................................................................................3586
61.11 Endianess...................................................................................................................................................................... 3588
61.11.1 Read from SRAM........................................................................................................................................ 3588
61.11.2 Write to SRAM............................................................................................................................................ 3589
61.12 Decoder Modes............................................................................................................................................................. 3589
61.12.1 Constrained Baseline, Single Channel mode............................................................................................... 3590
61.12.2 Intra Only, Multiple channels...................................................................................................................... 3590
61.12.3 Constrained Baseline, Multiple channels mode...........................................................................................3591
61.13 Decoder SW flow and handshaking with host and Sequencer..................................................................................... 3593
61.14 Decoder Core Software Consideration......................................................................................................................... 3594
61.14.1 Reference Address for Channel's................................................................................................................. 3594
61.14.2 Picture Crop Status for Channel’s................................................................................................................3596
61.14.3 Frame Cycle Count Threshold .................................................................................................................... 3596
Chapter 62
JPEG Decoder (JPEG)
62.1 Soft reset sequence........................................................................................................................................................3599
62.2 Introduction...................................................................................................................................................................3599
62.3 Features.........................................................................................................................................................................3599
62.4 Abbreviations and Acronyms....................................................................................................................................... 3600
62.5 Block Diagram..............................................................................................................................................................3601
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62.6 Memory Map and Registers..........................................................................................................................................3602
62.6.1 Stream 1 SRAM Pointer Register (JPEG_ST1_SRAM_PTR).................................................................... 3610
62.6.2 Stream 1 SRAM Length Value Register (JPEG_ST1_SRAM_LEN_VAL)............................................... 3610
62.6.3 Stream 1 Pointer FIFO Register (JPEG_ST1_PTR_FIFOn)....................................................................... 3611
62.6.4 Stream 1 Length Value FIFO register (JPEG_ST1_LEN_VAL_FIFOn)....................................................3611
62.6.5 Stream 2 SRAM Pointer register (JPEG_ST2_SRAM_PTR)..................................................................... 3612
62.6.6 Stream 2 SRAM Length Value Register (JPEG_ST2_SRAM_LEN_VAL)............................................... 3612
62.6.7 Stream 2 Pointer FIFO Register (JPEG_ST2_PTR_FIFOn)....................................................................... 3613
62.6.8 Stream 2 Length Value FIFO Register (JPEG_ST2_LEN_VAL_FIFOn).................................................. 3613
62.6.9 Stream 3 SRAM Pointer Register (JPEG_ST3_SRAM_PTR).................................................................... 3614
62.6.10 Stream 3 SRAM Length Value Register (JPEG_ST3_SRAM_LEN_VAL)............................................... 3614
62.6.11 Stream 3 Pointer FIFO Register (JPEG_ST3_PTR_FIFOn)....................................................................... 3615
62.6.12 Stream 3 Length Value FIFO Register (JPEG_ST3_LEN_VAL_FIFOn).................................................. 3615
62.6.13 Stream 4 SRAM Pointer Register (JPEG_ST4_SRAM_PTR).................................................................... 3616
62.6.14 Stream 4 SRAM Length Value Register (JPEG_ST4_SRAM_LEN_VAL)............................................... 3616
62.6.15 Stream 4 Pointer FIFO Register (JPEG_ST4_PTR_FIFOn)....................................................................... 3617
62.6.16 Stream 4 Length Value FIFO Register (JPEG_ST4_LEN_VAL_FIFOn).................................................. 3617
62.6.17 Buffer Component 1 Address Register (JPEG_BUF_C1_ADDR)..............................................................3618
62.6.18 Buffer Component 2 Address Register (JPEG_BUF_C2_ADDR)..............................................................3618
62.6.19 Buffer Component 3 Address Register (JPEG_BUF_C3_ADDR)..............................................................3619
62.6.20 Buffer Component 4 Address Register (JPEG_BUF_C4_ADDR)..............................................................3619
62.6.21 Block to Lines Number of Lines Register (JPEG_NRLINES_B2L)...........................................................3620
62.6.22 Block to Lines Number of Lines for Component 4 Register (JPEG_NRLINES_B2L_C4)........................3620
62.6.23 Timeout Register (JPEG_TIMEOUT)......................................................................................................... 3621
62.6.24 Wrapper Control Register (JPEG_W_CTRL1)........................................................................................... 3621
62.6.25 Wrapper Control Register 2 (JPEG_W_CTRL2)........................................................................................ 3622
62.6.26 Interrupt Enable (JPEG_INTR_EN)............................................................................................................ 3624
62.6.27 Wrapper Status Register (JPEG_W_STATUS)...........................................................................................3626
62.6.28 Error Status Register (JPEG_E_STATUS)..................................................................................................3628
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62.6.29 Restart Interval (JPEG_RST_INTVL).........................................................................................................3628
62.6.30 Image Size of Stream 1 (JPEG_IMG_SZ_ST1).......................................................................................... 3629
62.6.31 Image Size of Stream 2 (JPEG_IMG_SZ_ST2).......................................................................................... 3629
62.6.32 Image Size of Stream 3 (JPEG_IMG_SZ_ST3).......................................................................................... 3630
62.6.33 Image Size of Stream 4 (JPEG_IMG_SZ_ST4).......................................................................................... 3630
62.6.34 Sampling Factor Stream 1 (JPEG_SMPL_FCTR_ST1)..............................................................................3630
62.6.35 Sampling Factor Stream 2 (JPEG_SMPL_FCTR_ST2)..............................................................................3631
62.6.36 Sampling Factor Stream 3 (JPEG_SMPL_FCTR_ST3)..............................................................................3632
62.6.37 Sampling Factor Stream 4 (JPEG_SMPL_FCTR_ST4)..............................................................................3632
62.6.38 Test Pixel Location (JPEG_TST_PXL_LOC).............................................................................................3633
62.6.39 Test Pixel Location 1 (JPEG_TST_PXL_LOC1)........................................................................................3634
62.6.40 Test Line Luma Pixel Value for Stream 1 (JPEG_TST_LINE_LUMA_ST1)............................................3634
62.6.41 Test Line Cb Pixel Value for Stream 1 (JPEG_TST_LINE_Cb_ST1)........................................................3635
62.6.42 Test Line Cr Pixel Value for Stream 1 (JPEG_TST_LINE_Cr_ST1)......................................................... 3636
62.6.43 Test Line Luma Pixel Value for Stream 2 (JPEG_TST_LINE_LUMA_ST2)............................................3636
62.6.44 Test Line Cb Pixel Value for Stream 2 (JPEG_TST_LINE_Cb_ST2)........................................................3637
62.6.45 Test Line Cr Pixel Value for Stream 2 (JPEG_TST_LINE_Cr_ST2)......................................................... 3637
62.6.46 Test Line Luma Pixel Value for Stream 3 (JPEG_TST_LINE_LUMA_ST3)............................................3638
62.6.47 Test Line Cb Pixel Value for Stream 3 (JPEG_TST_LINE_Cb_ST3)........................................................3639
62.6.48 Test Line Cr Pixel Value for Stream 3 (JPEG_TST_LINE_Cr_ST3)......................................................... 3639
62.6.49 Test Line Luma Pixel Value for Stream 4 (JPEG_TST_LINE_LUMA_ST4)............................................3640
62.6.50 Test Line Luma Cb Pixel Value for Stream 4 (JPEG_TST_LINE_Cb_ST4)............................................. 3640
62.6.51 Test Line Cr Pixel Value for Stream 4 (JPEG_TST_LINE_Cr_ST4)......................................................... 3641
62.6.52 Control Register (JPEG_JPEG_CTRL)....................................................................................................... 3642
62.6.53 Status 1 Register (JPEG_JPEG_STATUS1)................................................................................................3642
62.6.54 Status 2 Register (JPEG_JPEG_STATUS2)................................................................................................3643
62.6.55 Status 3 Register (JPEG_JPEG_STATUS3)................................................................................................3643
62.6.56 Status 4 Register (JPEG_JPEG_STATUS4)................................................................................................3644
62.6.57 Status 5 Register (JPEG_JPEG_STATUS5)................................................................................................3644
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62.6.58 Status 6 Register (JPEG_JPEG_STATUS6)................................................................................................3645
62.6.59 Status 7 Register (JPEG_JPEG_STATUS7)................................................................................................3645
62.6.60 Status 8 Register (JPEG_JPEG_STATUS8)................................................................................................3646
62.6.61 Status 9 Register (JPEG_JPEG_STATUS9)................................................................................................3646
62.6.62 Status 10 Register (JPEG_JPEG_STATUS10)............................................................................................3647
62.6.63 Status 11 Register (JPEG_JPEG_STATUS11)............................................................................................3647
62.6.64 Status 12 Register (JPEG_JPEG_STATUS12)............................................................................................3648
62.6.65 Status 13 Register (JPEG_JPEG_STATUS13)............................................................................................3649
62.7 Functional description...................................................................................................................................................3650
62.7.1 JPEG Decoder.............................................................................................................................................. 3650
62.7.2 Input Stream DMA Interface....................................................................................................................... 3650
62.7.3 Output Stream DMA Interface.....................................................................................................................3651
62.7.4 Stream Wrapper........................................................................................................................................... 3656
62.7.5 Testline Feature............................................................................................................................................3657
62.7.6 JPEG Decoder Core functionality................................................................................................................3657
62.7.7 Programming Constraints............................................................................................................................ 3658
62.8 Copyright Notice...........................................................................................................................................................3659
Chapter 63
FastDMA (FDMA)
63.1 Chip-specific FDMA information.................................................................................................................................3661
63.1.1 Programming Guidelines............................................................................................................................. 3661
63.2 Introduction...................................................................................................................................................................3662
63.3 Overview.......................................................................................................................................................................3662
63.3.1 Block diagram.............................................................................................................................................. 3662
63.3.2 Features........................................................................................................................................................ 3664
63.3.3 Acronyms and abbreviations........................................................................................................................3664
63.3.4 Modes of operation...................................................................................................................................... 3664
63.4 FastDMA Register Map ...............................................................................................................................................3665
63.4.1 Transfer Records List Pointer register (FDMA_XFR_REC_LIST_PTR)...................................................3666
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63.4.2 Total entries in Transfer Record List (FDMA_XFR_REC_CNT).............................................................. 3666
63.4.3 Transfer Record number for current Line transfer (FDMA_XFR_REC_NUM).........................................3667
63.4.4 DDR and SRAM Line numbers for current transfer (FDMA_XFR_LINE_NUM).................................... 3667
63.4.5 Line increment value for SRAM and DDR (FDMA_LINE_INCR)............................................................3668
63.4.6 Interrupt enable register (FDMA_IRQ_EN)................................................................................................3669
63.4.7 Status register (FDMA_XFR_STAT)..........................................................................................................3670
63.4.8 Calculated CRC value (FDMA_CALC_CRC_VAL)..................................................................................3673
63.4.9 Current DDR address (FDMA_CURR_DDR_PTR)................................................................................... 3673
63.4.10 Current SRAM address (FDMA_CURR_SRAM_PTR)............................................................................. 3674
63.4.11 Last completed Transfer Record Number (FDMA_XFR_REC_NUM_DONE).........................................3674
63.4.12 Transfer Record Number of an Erroneous Transfer (FDMA_ERR_XFR_REC_NUM).............................3675
63.4.13 SRAM and DDR next Line number (FDMA_NEXT_LINE)......................................................................3675
63.4.14 Control register (FDMA_CTRL)................................................................................................................. 3676
63.5 Functional Description..................................................................................................................................................3677
63.5.1 Basic Data Flow........................................................................................................................................... 3677
63.5.2 Transfer Record List.................................................................................................................................... 3677
63.5.3 Functional Blocks........................................................................................................................................ 3680
63.6 Clock and Reset............................................................................................................................................................ 3684
Chapter 64
Vision Sequencer (VSEQ)
64.1 Chip-specific VSEQ information..................................................................................................................................3685
64.2 VSEQ KRAM and ISP Debug registers....................................................................................................................... 3686
64.3 Introduction...................................................................................................................................................................3686
64.4 Features.........................................................................................................................................................................3686
64.5 Acronyms and abbreviations.........................................................................................................................................3687
64.6 Block diagram...............................................................................................................................................................3688
64.7 Design Overview.......................................................................................................................................................... 3689
64.7.1 Initialization Sequence and Functional Modes............................................................................................ 3690
64.7.2 System Memory Map...................................................................................................................................3691
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64.7.3 Interrupt Vector Assignment........................................................................................................................3693
64.7.4 AIPS Peripheral Slot Assignment................................................................................................................ 3695
64.8 Sub-module Description............................................................................................................................................... 3698
64.8.1 ARM Cortex-M0  Core...............................................................................................................................3698
64.8.2 Crossbar-Lite (AXBS-Lite)..........................................................................................................................3699
64.8.3 Control Block (CTRL_BLK)....................................................................................................................... 3699
64.8.4 Event Controller Block (EVT_CTRL).........................................................................................................3715
64.8.5 Internal DMA...............................................................................................................................................3743
64.8.6 Address Translation for External AHB Master Port....................................................................................3748
64.9 Interrupts.......................................................................................................................................................................3749
64.10 Power Modes................................................................................................................................................................ 3750
Chapter 65
Video-In-Lite (VIULite)
65.1 Chip-specific VIULite Information.............................................................................................................................. 3751
65.2 Introduction...................................................................................................................................................................3751
65.3 Features.........................................................................................................................................................................3752
65.4 Video Input Signal Mapping.........................................................................................................................................3752
65.5 Video Output Format.................................................................................................................................................... 3753
65.6 Memory map and register definition.............................................................................................................................3753
65.6.1 Status And Control Register (VIULite_SCR)..............................................................................................3755
65.6.2 Interrupt Register (VIULite_INTR).............................................................................................................3757
65.6.3 Detected Input Video Pixel and Line Count (VIULite_DINVSZ).............................................................. 3759
65.6.4 Detected Input Video Frame Length (VIULite_DINVFL)..........................................................................3760
65.6.5 DMA Size Register (VIULite_DMA_SIZE)............................................................................................... 3760
65.6.6 Base Address Of Every Field/Frame Of Picture In Memory (VIULite_DMA_ADDR).............................3761
65.6.7 Horizontal DMA Increment (VIULite_DMA_INC)....................................................................................3761
65.6.8 Input Video Pixel and Line Count (VIULite_INVSZ)................................................................................ 3762
65.6.9 Programable Alpha Value (VIULite_ALPHA)........................................................................................... 3762
65.6.10 Active Image Original Coordinate (VIULite_ACT_ORG)......................................................................... 3763
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65.6.11 Active Image Size (VIULite_ACT_SIZE).................................................................................................. 3763
65.7 Functional Description..................................................................................................................................................3763
65.7.1 Input Formats............................................................................................................................................... 3764
65.7.2 Input Synchronizer.......................................................................................................................................3765
65.7.3 Decoder........................................................................................................................................................ 3766
65.7.4 DMA and De-interlace.................................................................................................................................3766
65.7.5 Input Video Checking.................................................................................................................................. 3767
65.7.6 Error Case.................................................................................................................................................... 3768
65.8 Initialization/Application Information..........................................................................................................................3769
65.8.1 Image Mode Initialization Information........................................................................................................3769
65.8.2 Register Configuration Timing Window..................................................................................................... 3770
Chapter 66
Image Signal Processor (ISP)
66.1 Chip-specific ISP information...................................................................................................................................... 3771
66.2 Introduction...................................................................................................................................................................3772
66.3 Block Diagram..............................................................................................................................................................3772
66.4 Features.........................................................................................................................................................................3774
66.5 Working Principle.........................................................................................................................................................3775
66.6 Scalar Image Processing Unit (IPUS)...........................................................................................................................3776
66.6.1 IPUS Core Description ................................................................................................................................3778
66.6.2 Hazards and Dependencies ......................................................................................................................... 3781
66.6.3 Pipeline Stalls ..............................................................................................................................................3784
66.6.4 Core Register Memory Map ....................................................................................................................... 3794
66.6.5 Host Memory Map and Register Description ............................................................................................. 3837
66.6.6 Pipeline Description and Execution ............................................................................................................3950
66.6.7 Instruction Set ............................................................................................................................................. 3965
66.6.8 Stream DMA Interface ................................................................................................................................4035
66.6.9 Stream-out DMA interface ..........................................................................................................................4040
66.6.10 Stream DMA Interface: Orthogonality ....................................................................................................... 4042
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66.6.11 Reverse/inverse Scan .................................................................................................................................. 4044
66.6.12 Unaligned Scan Line ...................................................................................................................................4046
66.7 Vector Image Processing Unit (IPUV)......................................................................................................................... 4047
66.7.1 IPUV Core description ................................................................................................................................4049
66.7.2 Hazards and Dependencies ......................................................................................................................... 4051
66.7.3 Pipeline Stalls...............................................................................................................................................4053
66.7.4 Core Register Memory Map ....................................................................................................................... 4063
66.7.5 Vector Registers...........................................................................................................................................4080
66.7.6 Host Memory Map and Register Description.............................................................................................. 4088
66.7.7 Pipeline Description and Execution ............................................................................................................4164
66.7.8 Instruction Set ............................................................................................................................................. 4172
66.7.9 Stream DMA Interface ................................................................................................................................4269
66.7.10 Stream-out DMA interface ..........................................................................................................................4275
66.7.11 Stream DMA Interface: Orthogonality ....................................................................................................... 4279
66.7.12 Reverse/Inverse Scan .................................................................................................................................. 4280
66.7.13 Unaligned Scan Line ...................................................................................................................................4282
66.7.14 Debug Mode cross-triggering Unit ............................................................................................................. 4283
66.7.15 Software Resetting and Initialization ..........................................................................................................4286
Chapter 67
Power Management
67.1 Overview.......................................................................................................................................................................4287
67.2 Power Management Controller (PMC).........................................................................................................................4287
67.3 Supply Concept.............................................................................................................................................................4288
67.4 Power Modes................................................................................................................................................................ 4289
67.5 External Supply.............................................................................................................................................................4290
67.6 Voltage Monitoring.......................................................................................................................................................4290
67.7 Core Supply Monitor.................................................................................................................................................... 4290
67.8 Non Core Supplies Monitor..........................................................................................................................................4291
67.9 Power-on Reset............................................................................................................................................................. 4293
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67.10 Power-up Sequence.......................................................................................................................................................4294
67.11 ADC Interface...............................................................................................................................................................4295
67.12 Safety Measures............................................................................................................................................................4296
Chapter 68
Power Management Controller (PMC)
68.1 PMC introduction......................................................................................................................................................... 4297
68.1.1 Features........................................................................................................................................................ 4298
68.2 Memory Map and Registers..........................................................................................................................................4298
68.2.1 PMC Control Register (PMC_CR).............................................................................................................. 4299
68.2.2 PMC Reset Event Enable (PMC_REE)....................................................................................................... 4301
68.2.3 PMC Fault Event Enable (PMC_FEE)........................................................................................................ 4303
68.2.4 PMC Interrupt Event Enable (PMC_IEE)................................................................................................... 4304
68.2.5 PMC Fault Injection Register (PMC_FIR).................................................................................................. 4306
68.2.6 PMC ADC Channel Select Register (PMC_ADC_CS)...............................................................................4307
68.2.7 PMC Self Test Control Register (PMC_STCR).......................................................................................... 4308
68.3 Functional Description..................................................................................................................................................4312
68.3.1 POR MC_RGM phase gates........................................................................................................................ 4312
68.3.2 PMC Fuse Interface..................................................................................................................................... 4312
68.3.3 PMC Fuse Latching Mechanism..................................................................................................................4313
68.3.4 FCCU interface............................................................................................................................................ 4313
68.3.5 LVD and HVD self test mechanism............................................................................................................ 4315
Chapter 69
Mode Entry Module (MC_ME)
69.1 Introduction...................................................................................................................................................................4319
69.1.1 Overview......................................................................................................................................................4319
69.1.2 Features........................................................................................................................................................ 4321
69.1.3 Use cases...................................................................................................................................................... 4321
69.1.4 Modes of operation...................................................................................................................................... 4324
69.2 External signal description............................................................................................................................................4324
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69.3 Memory map and register definition.............................................................................................................................4325
69.3.1 Global Status Register (MC_ME_GS).........................................................................................................4328
69.3.2 Mode Control Register (MC_ME_MCTL)..................................................................................................4331
69.3.3 Mode Enable Register (MC_ME_ME)........................................................................................................ 4332
69.3.4 Interrupt Status Register (MC_ME_IS)....................................................................................................... 4334
69.3.5 Interrupt Mask Register (MC_ME_IM).......................................................................................................4336
69.3.6 Invalid Mode Transition Status Register (MC_ME_IMTS)........................................................................ 4337
69.3.7 Debug Mode Transition Status Register (MC_ME_DMTS)....................................................................... 4338
69.3.8 RESET Mode Configuration Register (MC_ME_RESET_MC)................................................................. 4342
69.3.9 DRUN Mode Configuration Register (MC_ME_DRUN_MC)...................................................................4344
69.3.10 RUN Mode Configuration Register (MC_ME_RUNn_MC).......................................................................4347
69.3.11 Peripheral Status Register 1 (MC_ME_PS1)...............................................................................................4349
69.3.12 Peripheral Status Register 2 (MC_ME_PS2)...............................................................................................4351
69.3.13 Peripheral Status Register 3 (MC_ME_PS3)...............................................................................................4354
69.3.14 Peripheral Status Register 5 (MC_ME_PS5)...............................................................................................4355
69.3.15 Peripheral Status Register 6 (MC_ME_PS6)...............................................................................................4358
69.3.16 Peripheral Status Register 7 (MC_ME_PS7)...............................................................................................4360
69.3.17 Run Peripheral Configuration Register (MC_ME_RUN_PCn)...................................................................4361
69.3.18 DEC200 Encoder Peripheral Control Register (MC_ME_PCTL39)...........................................................4363
69.3.19 2D-ACE Peripheral Control Register (MC_ME_PCTL40).........................................................................4364
69.3.20 ENET Peripheral Control Register (MC_ME_PCTL50).............................................................................4365
69.3.21 DMACHMUX0 Peripheral Control Register (MC_ME_PCTL49).............................................................4366
69.3.22 CSI0 Peripheral Control Register (MC_ME_PCTL48)...............................................................................4367
69.3.23 MMDC0 Peripheral Control Register (MC_ME_PCTL54)........................................................................ 4367
69.3.24 FlexRay Peripheral Control Register (MC_ME_PCTL52)......................................................................... 4368
69.3.25 PIT0 Peripheral Control Register (MC_ME_PCTL58)............................................................................... 4369
69.3.26 FlexTIMER0 Peripheral Control Register (MC_ME_PCTL79)................................................................. 4370
69.3.27 SARADC0 Peripheral Control Register (MC_ME_PCTL77).....................................................................4371
69.3.28 LINFLEX0 Peripheral Control Register (MC_ME_PCTL83).................................................................... 4372
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69.3.29 IIC0 Peripheral Control Register (MC_ME_PCTL81)................................................................................4373
69.3.30 SPI0 Peripheral Control Register (MC_ME_PCTL87)............................................................................... 4374
69.3.31 CANFD0 Peripheral Control Register (MC_ME_PCTL85)....................................................................... 4375
69.3.32 CRC0 Peripheral Control Register (MC_ME_PCTL91)............................................................................. 4376
69.3.33 SPI2 Peripheral Control Register (MC_ME_PCTL89)............................................................................... 4377
69.3.34 SDHC Peripheral Control Register (MC_ME_PCTL93)............................................................................ 4378
69.3.35 VIU0 Peripheral Control Register (MC_ME_PCTL100)............................................................................4378
69.3.36 HPSMI Peripheral Control Register (MC_ME_PCTL104).........................................................................4379
69.3.37 SIPI Peripheral Control Register (MC_ME_PCTL116)..............................................................................4380
69.3.38 LFAST Peripheral Control Register (MC_ME_PCTL120).........................................................................4381
69.3.39 MMDC1 Peripheral Control Register (MC_ME_PCTL162)...................................................................... 4382
69.3.40 DMACHMUX1 Peripheral Control Register (MC_ME_PCTL161)...........................................................4383
69.3.41 CSI1 Peripheral Control Register (MC_ME_PCTL160).............................................................................4384
69.3.42 QUADSPI0 Peripheral Control Register (MC_ME_PCTL166)..................................................................4385
69.3.43 PIT1 Peripheral Control Register (MC_ME_PCTL170)............................................................................. 4386
69.3.44 FlexTIMER1 Peripheral Control Register (MC_ME_PCTL182)............................................................... 4387
69.3.45 IIC2 Peripheral Control Register (MC_ME_PCTL186)..............................................................................4388
69.3.46 IIC1 Peripheral Control Register (MC_ME_PCTL184)..............................................................................4389
69.3.47 CANFD1 Peripheral Control Register (MC_ME_PCTL190)..................................................................... 4389
69.3.48 LINFLEX1 Peripheral Control Register (MC_ME_PCTL188).................................................................. 4390
69.3.49 SPI3 Peripheral Control Register (MC_ME_PCTL194)............................................................................. 4391
69.3.50 SPI1 Peripheral Control Register (MC_ME_PCTL192)............................................................................. 4392
69.3.51 TSENS Peripheral Control Register (MC_ME_PCTL206).........................................................................4393
69.3.52 CRC1 Peripheral Control Register (MC_ME_PCTL204)........................................................................... 4394
69.3.53 VIU1 Peripheral Control Register (MC_ME_PCTL208)............................................................................4395
69.3.54 JPEG Peripheral Control Register (MC_ME_PCTL212)............................................................................4396
69.3.55 H264_DEC Peripheral Control Register (MC_ME_PCTL216).................................................................. 4397
69.3.56 H264_ENC Peripheral Control Register (MC_ME_PCTL220).................................................................. 4398
69.3.57 MBIST Peripheral Control Register (MC_ME_PCTL236).........................................................................4399
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69.3.58 Core Status Register (MC_ME_CS)............................................................................................................ 4400
69.3.59 Cortex-A53_CORE0 Control Register (MC_ME_CCTL1)........................................................................ 4401
69.3.60 Cortex-M4 Core Control Register (MC_ME_CCTL0)............................................................................... 4402
69.3.61 Cortex-A53_CORE2 Control Register (MC_ME_CCTL3)........................................................................ 4403
69.3.62 Cortex-A53_CORE1 Control Register (MC_ME_CCTL2)........................................................................ 4404
69.3.63 Cortex-A53_CORE3 Control Register (MC_ME_CCTL4)........................................................................ 4405
69.3.64 Cortex-M4 Core Address Register (MC_ME_CADDR0)...........................................................................4406
69.3.65 Cortex-A53_CORE0 Core Address Register (MC_ME_CADDR1)...........................................................4407
69.3.66 Cortex-A53_CORE1 Core Address Register (MC_ME_CADDR2)...........................................................4408
69.3.67 Cortex-A53_CORE2 Core Address Register (MC_ME_CADDR3)...........................................................4409
69.3.68 Cortex-A53_CORE3 Core Address Register (MC_ME_CADDR4)...........................................................4410
69.3.69 DRUN Secondary Clock Configuration Register (MC_ME_DRUN_SEC_CC_I).....................................4411
69.3.70 RUN0 Secondary Clock Configuration Register (MC_ME_RUN0_SEC_CC_I).......................................4413
69.3.71 RUN1 Secondary Clock Configuration Register (MC_ME_RUN1_SEC_CC_I).......................................4415
69.3.72 RUN2 Secondary Clock Configuration Register (MC_ME_RUN2_SEC_CC_I).......................................4417
69.3.73 RUN3 Secondary Clock Configuration Register (MC_ME_RUN3_SEC_CC_I).......................................4420
69.3.74 Secondary Clock Status Register (MC_ME_SEC_CS)............................................................................... 4422
69.4 Functional description...................................................................................................................................................4423
69.4.1 Mode transition request................................................................................................................................4423
69.4.2 Mode details.................................................................................................................................................4425
69.4.3 Mode transition process............................................................................................................................... 4427
69.4.4 Software considerations for preventing the blocking of mode transitions...................................................4433
69.4.5 Protection of mode configuration registers..................................................................................................4435
69.4.6 Mode transition interrupts............................................................................................................................4435
69.4.7 Peripheral clock gating.................................................................................................................................4437
69.4.8 Initialization/application information.......................................................................................................... 4438
Chapter 70
Functional Safety Overview
70.1 Introduction...................................................................................................................................................................4443
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Chapter 71
Error Injection In Memories
71.1 Introduction...................................................................................................................................................................4445
71.2 Memory map and register definition.............................................................................................................................4445
71.3 Persistence of error injection........................................................................................................................................ 4452
71.4 Procedure for using error injection in memories.......................................................................................................... 4452
Chapter 72
Memory Error Management Unit (MEMU)
72.1 Chip-specific MEMU information................................................................................................................................4453
72.1.1 MEMU error sources................................................................................................................................... 4453
72.1.2 Reporting table implementation...................................................................................................................4453
72.1.3 Concurrent overflow register (OFLW) implementation.............................................................................. 4454
72.1.4 MEMU Error source details.........................................................................................................................4455
72.1.5 IPD wrapper and overflow scenarios........................................................................................................... 4457
72.2 Introduction...................................................................................................................................................................4458
72.3 Features.........................................................................................................................................................................4459
72.4 Block diagram...............................................................................................................................................................4460
72.5 Design overview........................................................................................................................................................... 4460
72.6 External signal description............................................................................................................................................4464
72.7 Memory map and register definition.............................................................................................................................4465
72.7.1 Overview......................................................................................................................................................4465
72.7.2 Control register (MEMU_CTRL)................................................................................................................ 4466
72.7.3 Error flag register (MEMU_ERR_FLAG)...................................................................................................4466
72.7.4 Debug register (MEMU_DEBUG).............................................................................................................. 4468
72.7.5 Peripheral RAM correctable error reporting table status register
(MEMU_PERIPH_RAM_CERR_STSn).................................................................................................... 4470
72.7.6 Peripheral RAM correctable error reporting table address register
(MEMU_PERIPH_RAM_CERR_ADDRn)................................................................................................4470
72.7.7 Peripheral RAM uncorrectable error reporting table status register
(MEMU_PERIPH_RAM_UNCERR_STS).................................................................................................4471
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72.7.8 Peripheral RAM uncorrectable error reporting table address register
(MEMU_PERIPH_RAM_UNCERR_ADDR)............................................................................................ 4471
72.7.9 Peripheral RAM concurrent overflow register (MEMU_PERIPH_RAM_OFLWn).................................. 4472
72.8 Functional description...................................................................................................................................................4472
72.8.1 Initializing MEMU.......................................................................................................................................4472
72.8.2 Reading the reporting table.......................................................................................................................... 4473
72.8.3 Handling overflows (Multiple error reporting)............................................................................................4474
Chapter 73
Fault Collection and Control Unit (FCCU)
73.1 Chip-specific FCCU information..................................................................................................................................4477
73.1.1 Chip-boundary FCCU signals......................................................................................................................4477
73.1.2 Fault signal flow diagram............................................................................................................................ 4478
73.1.3 FCCU FOSU Count Value...........................................................................................................................4479
73.1.4 FCCU chip-specific register reset values.....................................................................................................4479
73.1.5 FCCU_CFG register event bit values by source (N and C).........................................................................4479
73.1.6 FCCU False Faults Occurring During MBIST Execution .......................................................................... 4480
73.1.7 Enabling NCF.............................................................................................................................................. 4481
73.2 Introduction...................................................................................................................................................................4481
73.2.1 Acronyms and abbreviations........................................................................................................................4482
73.3 Main features................................................................................................................................................................ 4483
73.4 Block diagram...............................................................................................................................................................4483
73.5 Signal description..........................................................................................................................................................4485
73.5.1 Signals..........................................................................................................................................................4485
73.6 Put FCCU in Configuration or Normal state................................................................................................................ 4487
73.6.1 Introduction..................................................................................................................................................4487
73.6.2 About changing states.................................................................................................................................. 4487
73.6.3 About locking the configuration.................................................................................................................. 4487
73.6.4 Put FCCU in Configuration state................................................................................................................. 4488
73.6.5 Put FCCU in Normal state........................................................................................................................... 4488
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73.7 Run operations.............................................................................................................................................................. 4489
73.7.1 Introduction..................................................................................................................................................4489
73.7.2 About running operations.............................................................................................................................4489
73.7.3 Run an operation.......................................................................................................................................... 4489
73.8 Functional description...................................................................................................................................................4490
73.8.1 Definitions....................................................................................................................................................4490
73.8.2 FSM description...........................................................................................................................................4491
73.8.3 Fault priority scheme and nesting................................................................................................................ 4493
73.8.4 Fault recovery.............................................................................................................................................. 4494
73.8.5 NMI/WKPU interface.................................................................................................................................. 4496
73.8.6 STCU interface............................................................................................................................................ 4497
73.8.7 Nonvolatile memory interface..................................................................................................................... 4498
73.8.8 EOUT interface............................................................................................................................................ 4499
73.8.9 Fault signal flow...........................................................................................................................................4506
73.9 Register descriptions.....................................................................................................................................................4506
73.9.1 Control (FCCU_CTRL)............................................................................................................................... 4509
73.9.2 Control Key (FCCU_CTRLK).....................................................................................................................4511
73.9.3 Configuration (FCCU_CFG)....................................................................................................................... 4512
73.9.4 Noncritical Fault Configuration (FCCU_NCF_CFGn)............................................................................... 4515
73.9.5 Noncritical Fault State Configuration (FCCU_NCFS_CFGn).................................................................... 4516
73.9.6 Noncritical Fault Status (FCCU_NCF_Sn)..................................................................................................4517
73.9.7 Noncritical Fault Key (FCCU_NCFK)........................................................................................................ 4519
73.9.8 Noncritical Fault Enable (FCCU_NCF_En)................................................................................................ 4520
73.9.9 Noncritical Fault Timeout Enable (FCCU_NCF_TOEn)............................................................................ 4521
73.9.10 Noncritical Fault Timeout (FCCU_NCF_TO).............................................................................................4522
73.9.11 Configuration-State Timer Interval (FCCU_CFG_TO).............................................................................. 4522
73.9.12 IO Control (FCCU_EINOUT)..................................................................................................................... 4523
73.9.13 Status (FCCU_STAT)..................................................................................................................................4525
73.9.14 NA Freeze Status (FCCU_N2AF_STATUS).............................................................................................. 4527
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73.9.15 AF Freeze Status (FCCU_A2FF_STATUS)................................................................................................4528
73.9.16 NF Freeze Status (FCCU_N2FF_STATUS)................................................................................................4529
73.9.17 FA Freeze Status (FCCU_F2A_STATUS)..................................................................................................4530
73.9.18 Noncritical Fault Fake (FCCU_NCFF)........................................................................................................4531
73.9.19 IRQ Status (FCCU_IRQ_STAT)................................................................................................................. 4532
73.9.20 IRQ Enable (FCCU_IRQ_EN).................................................................................................................... 4533
73.9.21 X Timer (FCCU_XTMR)............................................................................................................................ 4534
73.9.22 Mode Controller Status (FCCU_MCS)........................................................................................................4535
73.9.23 Transient Configuration Lock (FCCU_TRANS_LOCK)............................................................................4537
73.9.24 Permanent Configuration Lock (FCCU_PERMNT_LOCK).......................................................................4538
73.9.25 Delta T (FCCU_DELTA_T)........................................................................................................................4538
73.9.26 IRQ Alarm Enable (FCCU_IRQ_ALARM_ENn).......................................................................................4539
73.9.27 NMI Enable (FCCU_NMI_ENn).................................................................................................................4540
73.9.28 Noncritical Fault-State EOUT Signaling Enable (FCCU_EOUT_SIG_ENn)............................................ 4541
73.9.29 Configuration registers.................................................................................................................................4542
73.9.30 FCCU_CFG register bit value sources (N and C) by event.........................................................................4543
73.10 FCCU Output Supervision Unit....................................................................................................................................4544
73.11 Use cases and limitations..............................................................................................................................................4546
73.11.1 Configuration guidelines..............................................................................................................................4546
73.11.2 Recommendations to configure FCCU........................................................................................................ 4547
Chapter 74
Self-Test Control Unit (STCU2)
74.1 Chip-specific Self Test Control Unit (STCU2) information.........................................................................................4549
74.1.1 Supported BIST sequences.......................................................................................................................... 4549
74.1.2 Self Test Overview.......................................................................................................................................4549
74.1.3 STCU2 L/MBIST mapping..........................................................................................................................4550
74.1.4 Wait Time for Writing to the Online Registers............................................................................................4579
74.1.5 On-Line Reset Generation (only MBIST)................................................................................................... 4579
74.1.6 On-Line Reset Generation (LBIST Enabled)...............................................................................................4579
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74.1.7 AUTOLOCK_VALUE for Register Write Access via STCU2_SKC.........................................................4580
74.1.8 STCU Registers Reset Values......................................................................................................................4580
74.1.9 BIST interrupt support................................................................................................................................. 4580
74.1.10 PLL Loss of Lock During Self-test..............................................................................................................4581
74.2 Introduction...................................................................................................................................................................4581
74.3 Main features................................................................................................................................................................ 4581
74.4 Block diagram...............................................................................................................................................................4582
74.5 IPS bus interface........................................................................................................................................................... 4584
74.6 BISTs and BIST partitions............................................................................................................................................4585
74.6.1 Definition: BIST.......................................................................................................................................... 4585
74.6.2 Definition: BIST partition............................................................................................................................4585
74.6.3 Example: BIST partitions on a chip.............................................................................................................4585
74.6.4 Types of BIST partitions..............................................................................................................................4586
74.7 BIST sequences.............................................................................................................................................................4586
74.7.1 Definition: BIST sequence...........................................................................................................................4586
74.7.2 STCU2 executes MBISTs before LBISTs................................................................................................... 4586
74.7.3 Example: Single-phase BIST sequence....................................................................................................... 4586
74.7.4 Example: Multiphase BIST sequence.......................................................................................................... 4587
74.7.5 Types of BIST sequences.............................................................................................................................4587
74.7.6 Supported BIST sequences.......................................................................................................................... 4587
74.8 Functional description...................................................................................................................................................4587
74.8.1 FSM description...........................................................................................................................................4587
74.8.2 Reset management....................................................................................................................................... 4588
74.8.3 Built-in self-test scheduling......................................................................................................................... 4588
74.8.4 ABORT management...................................................................................................................................4589
74.8.5 FCCU interface............................................................................................................................................ 4589
74.8.6 Watchdogs....................................................................................................................................................4589
74.9 Register description...................................................................................................................................................... 4590
74.9.1 STCU2 Run Software Register (STCU2_RUNSW)....................................................................................4602
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74.9.2 STCU2 SK Code Register (STCU2_SKC)..................................................................................................4604
74.9.3 STCU2 Configuration Register (STCU2_CFG).......................................................................................... 4605
74.9.4 STCU2 Watchdog Register Granularity (STCU2_WDG)...........................................................................4607
74.9.5 STCU2 Error Register (STCU2_ERR_STAT)............................................................................................ 4608
74.9.6 STCU2 Error FM Register (STCU2_ERR_FM)......................................................................................... 4610
74.9.7 STCU2 On-Line LBIST Status Register 0 (STCU2_LBSSW0)................................................................. 4611
74.9.8 STCU2 On-Line LBIST End Flag Register 0 (STCU2_LBESW0)............................................................ 4615
74.9.9 STCU2 LBIST Unrecoverable FM Register 0 (STCU2_LBUFM0)........................................................... 4618
74.9.10 STCU2 On-Line MBIST Status Register 0 (STCU2_MBSSW0)............................................................... 4621
74.9.11 STCU2 On-Line MBIST Status Register 1 (STCU2_MBSSW1)............................................................... 4625
74.9.12 STCU2 On-Line MBIST Status High Register 2 (STCU2_MBSSW2)...................................................... 4628
74.9.13 STCU2 On-Line MBIST End Flag Register 0 (STCU2_MBESW0).......................................................... 4630
74.9.14 STCU2 On-Line MBIST End Flag Register 1 (STCU2_MBESW1).......................................................... 4634
74.9.15 STCU2 On-Line MBIST End Flag Register 2 (STCU2_MBESW2).......................................................... 4638
74.9.16 STCU2 MBIST Unrecoverable FM Register 0 (STCU2_MBUFM0).........................................................4640
74.9.17 STCU2 MBIST Unrecoverable FM Register 1 (STCU2_MBUFM1).........................................................4644
74.9.18 STCU2 MBIST Unrecoverable FM Register 2 (STCU2_MBUFM2).........................................................4647
74.9.19 STCU2 LBIST Control Register (STCU2_LB_CTRLn).............................................................................4649
74.9.20 STCU2 LBIST PC Stop Register (STCU2_LB_PCSn)...............................................................................4652
74.9.21 STCU2 On-Line LBIST MISR Expected Low Register (STCU2_LB_MISRELSWn)..............................4652
74.9.22 STCU2 On-Line LBIST MISR Expected High Register (STCU2_LB_MISREHSWn).............................4653
74.9.23 STCU2 On-Line LBIST MISR Read Low Register (STCU2_LB_MISRRLSWn).................................... 4654
74.9.24 STCU2 On-Line LBIST MISR Read High Register (STCU2_LB_MISRRHSWn)................................... 4654
74.9.25 STCU2 Algorithm Select Register (STCU2_ALGOSEL)...........................................................................4655
74.9.26 STCU2 MBIST Stagger Register (STCU2_STGGR)..................................................................................4656
74.9.27 STCU2 BIST Start Register (STCU2_BSTART)........................................................................................4657
74.9.28 STCU2 MBIST Control Register (STCU2_MB_CTRLn).......................................................................... 4658
74.10 Use cases and limitations..............................................................................................................................................4659
74.10.1 Online self test sequence..............................................................................................................................4659
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74.10.2 Design implementation information............................................................................................................ 4661
Chapter 75
Memory test and repair (MTR)
75.1 Introduction...................................................................................................................................................................4663
75.2 Failure Diagnostic Technique.......................................................................................................................................4665
75.2.1 Finding Failing BIST................................................................................................................................... 4665
75.2.2 Finding Failing Memory with in a BIST..................................................................................................... 4666
75.2.3 BIST Fault Diagnostic routine..................................................................................................................... 4667
75.2.4 Fail Mode..................................................................................................................................................... 4668
75.3 MCT Memory Map and Registers................................................................................................................................ 4669
75.3.1 MCT Algorithm Select Register (MCT_ALGOSEL)..................................................................................4669
75.3.2 BIST Start register (MCT_BSTART)..........................................................................................................4671
75.3.3 Stagger delay register (MCT_STAG_D)..................................................................................................... 4672
75.4 BIST Memory Map and Registers................................................................................................................................ 4672
75.4.1 Memory selection register (BIST_MSRn)...................................................................................................4673
75.4.2 BIST start register (BIST_BSTART).......................................................................................................... 4674
75.4.3 BIST reset register (BIST_BRST)............................................................................................................... 4675
75.4.4 BIST status register (BIST_BSTAT)...........................................................................................................4676
75.4.5 BIST Fail Per Memory register (BIST_BFPMn).........................................................................................4677
75.4.6 ROM Selection register (BIST_ROM_SEL)............................................................................................... 4678
75.4.7 ROM General Status register (BIST_ROM_STAT)....................................................................................4680
75.4.8 Address Debug register (BIST_ADDR_DBG)............................................................................................4682
75.4.9 Data Debug register (BIST_DBGn).............................................................................................................4683
75.5 BCTRL Memory Map and Registers............................................................................................................................4683
75.5.1 BIST All register (BCTRL_BISTALL).......................................................................................................4684
75.5.2 BIST Select Register (BCTRL_BSEL)........................................................................................................4685
75.5.3 BIST Status register (BCTRL_BIST_STAT).............................................................................................. 4686
75.6 MTR IPS Bridge Memory Map and Registers............................................................................................................. 4687
75.6.1 MTR IPS Address register (MTR_IPS_ADD)............................................................................................ 4687
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75.6.2 MTR IPS Data register (MTR_IPS_DATA)............................................................................................... 4688
75.6.3 MTR IPS Control register (MTR_IPS_CTRL)............................................................................................4688
75.6.4 Accessing MTR using IPS bridge................................................................................................................4689
75.7 MTR memory map........................................................................................................................................................4689
Chapter 76
Cyclic Redundancy Check (CRC)
76.1 Chip specific CRC information.................................................................................................................................... 4693
76.1.1 CRC Instances..............................................................................................................................................4693
76.2 Introduction...................................................................................................................................................................4693
76.3 Main features................................................................................................................................................................ 4693
76.3.1 Standard features..........................................................................................................................................4694
76.4 Block diagram...............................................................................................................................................................4694
76.5 External signal description............................................................................................................................................4694
76.5.1 Peripheral bus interface................................................................................................................................4694
76.6 CRC memory map and registers...................................................................................................................................4696
76.6.1 Configuration Register (CRC_CFGn)......................................................................................................... 4697
76.6.2 Input Register (CRC_INPn).........................................................................................................................4698
76.6.3 Current Status Register (CRC_CSTATn).................................................................................................... 4699
76.6.4 Output Register (CRC_OUTPn).................................................................................................................. 4699
76.7 Functional description...................................................................................................................................................4700
76.8 Use cases.......................................................................................................................................................................4702
76.8.1 Programming example................................................................................................................................. 4702
76.8.2 Register programming..................................................................................................................................4703
Chapter 77
Safe State Engine (SSE)
77.1 Introduction...................................................................................................................................................................4705
77.2 Features.........................................................................................................................................................................4705
77.3 Block Diagram..............................................................................................................................................................4706
77.4 Interrupts.......................................................................................................................................................................4707
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77.5 Signal Description.........................................................................................................................................................4707
77.5.1 Signal Description........................................................................................................................................4707
77.6 Memory Map and Register Description........................................................................................................................4707
77.6.1 Configuration Register (SSE_CFG).............................................................................................................4708
77.6.2 Input Register (SSE_IR).............................................................................................................................. 4710
77.6.3 Compare Register (SSE_CR).......................................................................................................................4710
77.6.4 First Look Up Table Register (SSE_LUT_LSB).........................................................................................4711
77.6.5 Second Look Up Table Register (SSE_LUT_MSB)................................................................................... 4711
77.6.6 Watchdog Window Value (SSE_WD_WIN)...............................................................................................4712
77.6.7 Watchdog Timeout (SSE_WD_TO)............................................................................................................ 4712
77.6.8 Interrupt Enable Register (SSE_INT_EN)...................................................................................................4713
77.6.9 State Register (SSE_STATE)...................................................................................................................... 4714
77.7 Functional Description..................................................................................................................................................4715
77.7.1 Glitch Filter.................................................................................................................................................. 4715
77.7.2 Parity Checker..............................................................................................................................................4716
77.7.3 Watchdog Counter....................................................................................................................................... 4717
Chapter 78
Register Protection (REG_PROT)
78.1 Chip specific REG_PROT information........................................................................................................................ 4719
78.1.1 Register Protected on Device.......................................................................................................................4719
78.2 Overview.......................................................................................................................................................................4741
78.3 Features.........................................................................................................................................................................4742
78.4 Modes of operation....................................................................................................................................................... 4742
78.5 External signal description............................................................................................................................................4743
78.6 Memory map and register definition.............................................................................................................................4743
78.6.1 Memory map................................................................................................................................................ 4744
78.6.2 Register descriptions.................................................................................................................................... 4746
78.7 Memory map and registers............................................................................................................................................4746
78.7.1 Soft Lock Bit Register n (REG_PROT_SLBRn).........................................................................................4747
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78.7.2 Global Configuration Register (REG_PROT_GCR)...................................................................................4749
78.8 Functional description...................................................................................................................................................4750
78.8.1 General......................................................................................................................................................... 4750
78.8.2 Change lock settings.................................................................................................................................... 4750
78.8.3 Access errors................................................................................................................................................ 4753
78.9 Initialization/application information........................................................................................................................... 4754
78.9.1 Reset.............................................................................................................................................................4754
78.9.2 Writing C code using the register protection scheme.................................................................................. 4754
Chapter 79
Debug Architecture
79.1 Introduction...................................................................................................................................................................4757
79.2 Features.........................................................................................................................................................................4757
79.3 Debug Architecture.......................................................................................................................................................4760
79.3.1 Debug related NCFs.....................................................................................................................................4762
79.3.2 Test and Debug Access Port Connectivity...................................................................................................4762
79.3.3 Debug Port Pin Descriptions........................................................................................................................4764
79.3.4 JTAG to SWD cJTAG switching sequence................................................................................................. 4764
79.3.5 System JTAG Controller (JTAGC)..............................................................................................................4765
79.3.6 Debug Access Port (DAP) TAP...................................................................................................................4766
79.3.7 Secure JTAG Controller (SJC).................................................................................................................... 4769
79.4 Trace Architecture........................................................................................................................................................ 4771
79.4.1 Trace Port Pin Descriptions......................................................................................................................... 4771
79.4.2 Trace Modules and Connectivity................................................................................................................. 4771
79.5 Embedded Cross Trigger.............................................................................................................................................. 4773
79.5.1 Cortex-M4 CTI Triggers..............................................................................................................................4774
79.5.2 HTM CTI Triggers.......................................................................................................................................4775
79.5.3 Cortex-A53 CTI Triggers.............................................................................................................................4776
79.5.4 Cortex-M0  DWT CTI Triggers..................................................................................................................4776
79.5.5 IPUS CTI Triggers....................................................................................................................................... 4777
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79.5.6 APEX and IPUV CTI Triggers.................................................................................................................... 4777
79.6 Platform Debug Control Registers................................................................................................................................4778
79.6.1 Platform Debug Trace Control Register...................................................................................................... 4778
79.6.2 Platform Debug Page Control Register........................................................................................................4779
79.6.3 Platform Debug Miscellaneous Control Register........................................................................................ 4780
79.7 Debug Status and Control Registers............................................................................................................................. 4782
79.7.1 Miscellaneous Debug Module (MDM) AP Control Register...................................................................... 4783
79.7.2 Miscellaneous Debug Module (MDM) AP Status Register.........................................................................4784
79.7.3 Miscellaneous Debug Module (MDM) AP Status Register2.......................................................................4785
79.8 Debug Resets................................................................................................................................................................ 4786
79.9 References.....................................................................................................................................................................4786
Chapter 80
JTAG Controller (JTAGC)
80.1 Chip specific JTAGC information................................................................................................................................4789
80.1.1 JTAG signal properties................................................................................................................................ 4789
80.2 Block diagram...............................................................................................................................................................4789
80.3 Features.........................................................................................................................................................................4790
80.4 Modes of operation....................................................................................................................................................... 4791
80.4.1 Reset.............................................................................................................................................................4791
80.4.2 IEEE 1149.1-2001 defined test modes.........................................................................................................4791
80.4.3 Bypass mode................................................................................................................................................ 4792
80.5 Introduction................................................................................................................................................................... 0
80.5.1 Block diagram.............................................................................................................................................. 4792
80.5.2 Features........................................................................................................................................................ 0
80.5.3 Modes of operation...................................................................................................................................... 0
80.6 TCK—Test clock input.................................................................................................................................................4792
80.7 TDI—Test data input.................................................................................................................................................... 4792
80.8 TDO—Test data output.................................................................................................................................................4793
80.9 TMS—Test mode select............................................................................................................................................... 4793
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80.10 JCOMP—JTAG compliancy........................................................................................................................................ 4793
80.11 External signal description............................................................................................................................................ 0
80.11.1 TCK Test clock input...................................................................................................................................4794
80.11.2 TDI Test data input...................................................................................................................................... 0
80.11.3 TDO Test data output................................................................................................................................... 0
80.11.4 TMS Test mode select.................................................................................................................................. 0
80.11.5 JCOMP JTAG compliancy.......................................................................................................................... 0
80.12 Instruction register........................................................................................................................................................ 4794
80.13 Bypass register..............................................................................................................................................................4794
80.14 Device identification register........................................................................................................................................4795
80.15 Boundary scan register..................................................................................................................................................4795
80.16 Register description...................................................................................................................................................... 0
80.16.1 Instruction register....................................................................................................................................... 4796
80.16.2 Bypass register............................................................................................................................................. 0
80.16.3 Device identification register....................................................................................................................... 0
80.16.4 Boundary scan register................................................................................................................................. 0
80.17 JTAGC reset configuration...........................................................................................................................................4796
80.18 IEEE 1149.1-2001 (JTAG) Test Access Port............................................................................................................... 4796
80.19 TAP controller state machine........................................................................................................................................4797
80.19.1 Enabling the TAP controller........................................................................................................................ 4798
80.19.2 Selecting an IEEE 1149.1-2001 register...................................................................................................... 4799
80.20 JTAGC block instructions.............................................................................................................................................4799
80.20.1 IDCODE instruction.................................................................................................................................... 4800
80.20.2 SAMPLE/PRELOAD instruction................................................................................................................ 4800
80.20.3 SAMPLE instruction....................................................................................................................................4801
80.20.4 EXTEST External test instruction................................................................................................................4801
80.20.5 TEST_LEAKAGE instruction..................................................................................................................... 4801
80.20.6 HIGHZ instruction....................................................................................................................................... 4801
80.20.7 CLAMP instruction......................................................................................................................................4802
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80.20.8 BYPASS instruction.................................................................................................................................... 4802
80.21 Boundary scan...............................................................................................................................................................4802
80.22 Functional description................................................................................................................................................... 0
80.22.1 JTAGC reset configuration.......................................................................................................................... 4803
80.22.2 IEEE 11491-2001 JTAG Test Access Port.................................................................................................. 0
80.22.3 TAP controller state machine....................................................................................................................... 0
80.22.4 JTAGC block instructions............................................................................................................................ 0
80.22.5 Boundary scan.............................................................................................................................................. 0
80.23 Initialization Application information.......................................................................................................................... 0
Chapter 81
IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
81.1 References.....................................................................................................................................................................4805
81.2 Abbreviations................................................................................................................................................................4805
81.3 Introduction...................................................................................................................................................................4806
81.3.1 Types of operation....................................................................................................................................... 4807
81.3.2 Deployment by class.................................................................................................................................... 4807
81.3.3 1149.7 TAP signals...................................................................................................................................... 4808
81.3.4 TAP.7 architecture....................................................................................................................................... 4809
81.3.5 Protocols.......................................................................................................................................................4810
81.4 Operating models..........................................................................................................................................................4812
81.5 CJTAG implementation summary................................................................................................................................ 4812
81.5.1 T0 functions................................................................................................................................................. 4812
81.5.2 T1 functions................................................................................................................................................. 4813
81.5.3 T2 functions................................................................................................................................................. 4813
81.5.4 T3 functions................................................................................................................................................. 4813
81.5.5 T4 functions................................................................................................................................................. 4813
81.6 Ancillary services..........................................................................................................................................................4813
81.6.1 Overview......................................................................................................................................................4813
81.6.2 Resets........................................................................................................................................................... 4814
S32V234 Reference Manual, Rev. 5, 11/2019
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Section number Title Page
81.6.3 Start-up Options........................................................................................................................................... 4817
81.6.4 RSU operation..............................................................................................................................................4818
81.6.5 TAPC State Machine................................................................................................................................... 4820
81.7 EPU (Extended Protocol Unit) Operation.....................................................................................................................4821
81.7.1 EPU Operation............................................................................................................................................. 4821
81.7.2 EPU Registers.............................................................................................................................................. 4824
81.7.3 EPU Commands...........................................................................................................................................4835
81.7.4 EPU operating states.................................................................................................................................... 4843
81.7.5 System and EPU Paths.................................................................................................................................4844
81.8 APU (Advanced Protocol Unit) Operation...................................................................................................................4844
81.8.1 Overview......................................................................................................................................................4844
81.8.2 Operation......................................................................................................................................................4847
81.8.3 Escape sequences......................................................................................................................................... 4849
81.8.4 Signal behaviors...........................................................................................................................................4849
81.8.5 APU Functions.............................................................................................................................................4850
81.8.6 Configuration Change Packets (CP)............................................................................................................ 4856
81.8.7 Scan Packet.................................................................................................................................................. 4857
81.8.8 SP Format.....................................................................................................................................................4857
81.9 Functional Description..................................................................................................................................................4864
81.9.1 Switching from Standard Protocol to Advanced Protocol........................................................................... 4864