Lattice DDR3 SDRAM IP core资料

【实例截图】

【核心代码】

Contents
Acronyms in This Document ................................................................................................................................................. 6
1. Introduction .................................................................................................................................................................. 7
1.1. Quick Facts .......................................................................................................................................................... 7
1.2. Features .............................................................................................................................................................. 9
2. Functional Description ................................................................................................................................................ 10
2.1. Overview ........................................................................................................................................................... 10
2.2. DDR3 MC Module .............................................................................................................................................. 11
2.2.1. Command Decode Logic ............................................................................................................................... 11
2.2.2. Command Application Logic ......................................................................................................................... 11
2.2.3. On-Die Termination ...................................................................................................................................... 11
2.3. DDR3 PHY Module ............................................................................................................................................. 12
2.3.1. Initialization Module .................................................................................................................................... 12
2.3.2. Write Leveling .............................................................................................................................................. 12
2.3.3. Read Training ................................................................................................................................................ 12
2.4. Selecting READ_PULSE_TAP Value (Only for LatticeECP3 Device) .................................................................... 14
2.4.1. Data Path Logic ............................................................................................................................................. 14
2.5. Signal Descriptions ............................................................................................................................................ 15
2.6. Using the Local User Interface .......................................................................................................................... 18
2.6.1. Initialization Control ..................................................................................................................................... 18
2.6.2. Command and Address ................................................................................................................................ 19
2.6.3. User Commands ........................................................................................................................................... 20
2.6.4. WRITE ........................................................................................................................................................... 21
2.6.5. WRITEA ......................................................................................................................................................... 22
2.6.6. READ ............................................................................................................................................................. 22
2.6.7. READA ........................................................................................................................................................... 23
2.6.8. REFRESH Support .......................................................................................................................................... 23
2.7. Local-to-Memory Address Mapping .................................................................................................................. 24
2.8. Mode Register Programming ............................................................................................................................ 25
3. Parameter Settings ..................................................................................................................................................... 27
3.1. Type Tab ............................................................................................................................................................ 29
3.1.1. Device Information ....................................................................................................................................... 30
3.1.2. Memory Configuration ................................................................................................................................. 30
3.1.3. Additional Configuration .............................................................................................................................. 31
3.1.4. Data_rdy to Write Data Delay ...................................................................................................................... 31
3.1.5. Write Leveling ............................................................................................................................................... 31
3.1.6. Controller Reset to Memory......................................................................................................................... 31
3.2. Setting Tab ........................................................................................................................................................ 32
3.2.1. Address ......................................................................................................................................................... 32
3.2.2. Auto Refresh Control .................................................................................................................................... 32
3.2.3. Mode Register initial Setting ........................................................................................................................ 33
3.2.4. Burst Length ................................................................................................................................................. 33
3.3. Memory Device Timing Tab .............................................................................................................................. 34
3.3.1. Manually Adjust ........................................................................................................................................... 34
3.3.2. tCLK - Memory clock ..................................................................................................................................... 34
3.4. Pin Selection Tab ................................................................................................................................................ 36
3.4.1. Manually Adjust ............................................................................................................................................ 36
3.4.2. Pin Side ......................................................................................................................................................... 36
3.4.3. clk_in/PLL Locations ..................................................................................................................................... 37
3.4.4. DDR3 SDRAM Memory Clock Pin Location ................................................................................................... 37
3.4.5. DQS Locations............................................................................................................................................... 37
3.5. Design Tools Options and Info Tab ..................................................................................................................... 38
3.5.1. Support Synplify ........................................................................................................................................... 38
3.5.2. Support ModelSim........................................................................................................................................ 38
Double Data Rate (DDR3) SDRAM Controller IP Core
User Guide
© 2010-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-IPUG-02047-2.2
3.5.3. Support ALDEC .............................................................................................................................................. 38
3.5.4. Memory I/F Pins ........................................................................................................................................... 38
3.5.5. User I/F Pins .................................................................................................................................................. 39
4. IP Core Generation and Evaluation for LatticeECP3 DDR3 ......................................................................................... 40
4.1. Getting Started .................................................................................................................................................. 40
4.2. IPexpress-Created Files and Top Level Directory Structure ................................................................................ 42
4.2.1. DDR3 Memory Controller IP File Structure .................................................................................................. 45
4.2.2. Simulation Files for IP Evaluation ................................................................................................................. 46
4.3. Hardware Evaluation ......................................................................................................................................... 47
4.3.1. Enabling Hardware Evaluation in Diamond: ................................................................................................. 47
4.4. Updating/Regenerating the IP Core .................................................................................................................. 48
5. IP Core Generation and Evaluation for ECP5 DDR3 .................................................................................................... 49
5.1. Getting Started .................................................................................................................................................. 49
5.2. Created Files and IP Top Level Directory Structure ........................................................................................... 52
5.3. DDR3 Memory Controller IP File Structure ....................................................................................................... 55
5.3.1. Top-level Wrapper ........................................................................................................................................ 55
5.3.2. Clock Synchronization Module ..................................................................................................................... 55
5.4. Simulation Files for IP Evaluation ...................................................................................................................... 56
5.4.1. Test Bench Top ............................................................................................................................................. 56
5.4.2. Obfuscated Controller Simulation Model ..................................................................................................... 56
5.4.3. Command Generator .................................................................................................................................... 56
5.4.4. Monitor......................................................................................................................................................... 56
5.4.5. Test Bench Configuration Parameter ............................................................................................................ 57
5.4.6. Memory Model ............................................................................................................................................. 57
5.4.7. Memory Model Parameter ........................................................................................................................... 57
5.4.8. Evaluation Script File ..................................................................................................................................... 57
5.4.9. Note on Shortening Simulation Run Time ..................................................................................................... 57
5.5. Hardware Evaluation ......................................................................................................................................... 57
5.5.1. Enabling Hardware Evaluation in Diamond .................................................................................................. 57
5.6. Regenerating/Recreating the IP Core ................................................................................................................ 58
5.6.1. Regenerating an IP Core in Clarity Designer Tool ......................................................................................... 58
5.6.2. Recreating an IP Core in Clarity Designer Tool ............................................................................................. 58
6. Application Support .................................................................................................................................................... 59
6.1. Understanding Preferences ............................................................................................................................... 59
6.1.1. FREQUENCY Preferences .............................................................................................................................. 59
6.1.2. MAXDELAY NET ............................................................................................................................................ 59
6.1.3. MULTICYCLE/BLOCK PATH ............................................................................................................................ 59
6.1.4. IOBUF ............................................................................................................................................................ 59
6.1.5. LOCATE .......................................................................................................................................................... 59
6.2. Handling DDR3 IP Preferences in User Designs ................................................................................................. 59
6.3. Reset Handling .................................................................................................................................................. 60
6.4. Dummy Logic Removal ...................................................................................................................................... 60
6.5. Top-level Wrapper File Only for Evaluation Implementation ........................................................................... 60
6.6. Top-level Wrapper file for All Simulation Cases and Implementation in a User’s Design ................................. 60
6.7. RDIMM Module Support ................................................................................................................................... 61
7. Core Validation ........................................................................................................................................................... 62
References .......................................................................................................................................................................... 63
Technical Support Assistance ............................................................................................................................................. 63
Appendix A. Resource Utilization ....................................................................................................................................... 64
ECP5 Devices ................................................................................................................................................................... 64
LatticeECP3 Devices ........................................................................................................................................................ 65
Appendix B. Lattice Device Versus DDR3 IP Matrix ............................................................................................................ 66
Appendix C. LatticeECP3 DDR3 IP Locate Constraints ........................................................................................................ 67
Revision History .................................................................................................................................................................. 69
 Double Data Rate (DDR3) SDRAM Controller IP Core
User Guide
© 2010-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02047-2.2 5
Figures
Figure 2.1. DDR3 SDRAM Controller Block Diagram ........................................................................................................... 10
Figure 2.2. Timing of Memory Initialization Control ........................................................................................................... 18
Figure 2.3. Timing of Command and Address ..................................................................................................................... 20
Figure 2.4. One-Clock vs. Two-Clock Write Data Delay ...................................................................................................... 21
Figure 2.5. User-Side Read Operation ................................................................................................................................ 22
Figure 2.6. Local-to-Memory Address Mapping for Memory Access ................................................................................. 24
Figure 2.7. Mapped Address for the Example .................................................................................................................... 24
Figure 2.8. User-to-Memory Address Mapping for MR Programming ............................................................................... 25
Figure 3.1. DDR3 SDRAM Controller IP Core Type Options in the IPexpress Tool .............................................................. 29
Figure 3.2. DDR3 SDRAM IP Core Setting Options in the IPexpress Tool ............................................................................ 32
Figure 3.3. DDR3 SDRAM IP Core Memory Device Timing Options in the IPexpress Tool .................................................. 34
Figure 3.4. DDR3 SDRAM IP Core Pin Selection Options in the IPexpress Tool .................................................................. 36
Figure 3.5. DDR3 SDRAM IP Core Design Tools Options and Info Options in the IPexpress Tool ....................................... 38
Figure 4.1. IPexpress Tool Dialog Box ................................................................................................................................. 40
Figure 4.2. Configuration Interface ..................................................................................................................................... 41
Figure 4.3. LatticeECP3 DDR3 Core Directory Structure ..................................................................................................... 42
Figure 4.4. File Structure of DDR3 Memory Controller IP................................................................................................... 45
Figure 4.5. Simulation Structure for DDR3 Memory Controller Core Evaluation ............................................................... 46
Figure 5.1. Clarity Designer Tool Dialog Box ....................................................................................................................... 49
Figure 5.2. Clarity Designer IP Catalog Window ................................................................................................................. 50
Figure 5.3. IP Generation Dialog Box .................................................................................................................................. 50
Figure 5.4. IP Configuration Interface ................................................................................................................................. 51
Figure 5.5. ECP5 DDR3 Core Directory Structure ................................................................................................................ 52
Figure 5.6. File Structure of DDR3 Memory Controller IP................................................................................................... 55
Figure 5.7. Simulation Structure for DDR3 Memory Controller Core Evaluation ............................................................... 56
Tables
Table 1.1. DDR3 IP Core Quick Facts for ECP5 1, 2 .................................................................................................................. 7
Table 1.2. DDR3 IP Core Quick Facts for LatticeECP3 ........................................................................................................... 8
Table 2.1. DDR3 SDRAM Memory Controller Top-Level I/O List ........................................................................................ 15
Table 2.2. Local User Interface Functional Groups ............................................................................................................. 18
Table 2.3. Defined User Commands ................................................................................................................................... 20
Table 2.4. Address Mapping Example ................................................................................................................................. 24
Table 2.5. Transmit MAC Statistics Vector .......................................................................................................................... 25
Table 2.6. Initialization Default Values for Mode Register Setting ..................................................................................... 25
Table 3.1. IP Core Parameters ............................................................................................................................................ 27
Table 4.1. File List ............................................................................................................................................................... 43
Table 5.1. IPexpress File List ............................................................................................................................................... 53
Table A.1. Performance and Resource Utilization 1, 4 .......................................................................................................... 64
Table A.2. Performance and Resource Utilization 1, 2, 4 ........................................................................................................ 65
Table C.1. Left Side Second Clock Input Pin Locations (LatticeECP3-150; LatticeECP3-95) ................................................ 67
Table C.2. Left Side Second Clock Input Pin Locations (LatticeECP3-70; LatticeECP3-35) .................................................. 67
Table C.3. Right Side Second Clock Input Pin Locations (LatticeECP3-150; LatticeECP3-95) .............................................. 68
Table C.4. Right Side Second Clock Input Pin Locations (LatticeECP3-70; LatticeECP3-35) ................................................ 68