实例介绍
【实例简介】ASIC Design and Synthesis. RTL Design Using Verilog
【实例截图】
【核心代码】
Contents
1 Introduction ..........................................
1
1.1 ASIC Design ....................................
2
1.2 Types of ASIC ...................................
2
1.3 Abstraction Levels ................................
6
1.4 Design Examples .................................
9
1.5 What We Should Know? ............................
9
1.6 Important Terms Used Throughout Design Cycle ..........
11
1.7 Chapter Summary .................................
12
2 ASIC Design Flow......................................
13
2.1 ASIC Design Flow ................................
13
2.1.1 Logic Design ..............................
16
2.1.2 Physical Design ............................
20
2.2 FPGA Design Flow ................................
22
2.3 Examples and Thought Process .......................
24
2.4 Design Challenges.................................
25
2.5 Chapter Summary .................................
25
3 Let Us Build Design Foundation ...........................
27
3.1 Combinational Design Elements.......................
27
3.2 Logic Understanding and Use of Construct ...............
28
3.3 Arithmetic Resources and Area .......................
29
3.4 Code Converter...................................
31
3.4.1 Binary to Gray Code Converter .................
31
3.4.2 Gray to Binary Code Converter .................
33
3.5 Multiplexers .....................................
35
3.6 Cascading Stages of MUX Using Instantiation ............
38
3.7 Decoders .......................................
40
3.8 Encoders .......................................
43
3.9 Priority Encoders .................................
43
xiii3.10 Strategies During ASIC Design .......................
46
3.11 Exercises .......................................
47
3.12 Chapter Summary .................................
47
4 Sequential Design Concepts...............................
49
4.1 Sequential Design Elements ..........................
49
4.2 Let Us Understand Blocking Versus Non-blocking
Assignments .....................................
50
4.2.1 Blocking Assignments .......................
51
4.2.2 Reordering of the Blocking Assignments ..........
51
4.2.3 Non-blocking Assignments ....................
53
4.2.4 Reordering of the Non-blocking Assignments.......
54
4.3 Latch-Based Designs ...............................
55
4.4 Flip-Flop-Based Designs ............................
58
4.5 Reset Strategies...................................
60
4.5.1 Asynchronous Reset .........................
61
4.5.2 Synchronous Reset ..........................
64
4.6 Frequency Divider.................................
65
4.7 Synchronous Design ...............................
68
4.8 Asynchronous Design ..............................
70
4.9 RTL Design and Verifification for Complex Designs.........
70
4.10 Exercises .......................................
71
4.11 Chapter Summary .................................
72
5 Important Design Considerations ..........................
73
5.1 Timing Parameters ................................
74
5.2 Metastability .....................................
75
5.3 Clock Skew .....................................
75
5.3.1 Positive Clock Skew .........................
77
5.3.2 Negative Clock Skew ........................
79
5.4 Slack ..........................................
80
5.4.1 Setup Slack ...............................
80
5.4.2 Hold Slack ................................
80
5.5 Clock Latency ...................................
80
5.6 Area for the Design ................................
81
5.7 Speed Requirements ...............................
81
5.8 Power Requirements ...............................
82
5.9 What Are Design Constraints? ........................
83
5.10 Exercises .......................................
83
5.11 Chapter Summary .................................
84
6 Important Considerations for ASIC Designs ..................
85
6.1 Synchronous Design and Considerations.................
85
6.2 Positive Clock Skew and Impact on Speed ...............
86
6.3 Negative Clock Skew and Impact on the Speed ...........
88
xiv
Contents6.4 Clock and Network Latency .........................
89
6.5 Timing Paths in the Design ..........................
89
6.5.1 Input to Reg Path ...........................
90
6.5.2 Reg to Output Path ..........................
90
6.5.3 Reg to Reg Path ............................
91
6.5.4 Input to Output Path .........................
91
6.6 Frequency Calculations .............................
91
6.7 What Is On-Chip Variations .........................
93
6.8 Exercises .......................................
94
6.9 Chapter Summary .................................
94
7 Multiple Clock Domain Designs ...........................
97
7.1 General Strategies for Multiple Clock Domain Designs ......
97
7.2 What Are Issues in the Multiple Clock Domain Design ......
98
7.3 Architecture Design Strategies ........................
99
7.4 Control Path and Synchronization .....................
102
7.4.1 Level or Multiflflop Synchronizer ................
102
7.4.2 Pulse Synchronizers .........................
106
7.4.3 MUX Synchronizer..........................
106
7.5 Challenges in the Multiple Bit Data Transfer .............
106
7.6 Data Path Synchronizers ............................
108
7.6.1 Handshaking Mechanism .....................
108
7.6.2 FIFO Synchronizer ..........................
110
7.6.3 Gray Encoding .............................
111
7.7 Summary and Future Discussions......................
111
8 Low Power Design Considerations .........................
113
8.1 Introduction to Low Power Design .....................
113
8.2 Sources of Power .................................
114
8.3 Power Optimization During the RTL Design .............
116
8.4 Switching and Leakage Power Reduction Techniques .......
121
8.4.1 Clock Gating and Clock Tree Optimizations .......
122
8.4.2 Operand Isolations ..........................
122
8.4.3 Multiple Vth ............................... 123
8.4.4 Multiple Supply Voltages (MSV) ...............
123
8.4.5 Dynamic Voltage and Frequency Scaling (DVSF) ...
123
8.4.6 Power Gating (Power Shut Off) .................
123
8.4.7 Isolation Logic .............................
124
8.4.8 State Retention .............................
124
8.5 Low-Power Design Architecture and Use of UPF ..........
124
8.6 Chapter Summary .................................
127
9 Architecture and Micro-architecture Design ..................
129
9.1 Architecture Design ................................
129
9.2 Micro-architecture Design ...........................
131
Contents
xv9.3 Use of Document During Various Design Phases ..........
131
9.4 Design Partitioning ................................
132
9.5 Multiple Clock Domains and Clock Grouping ............
132
9.6 Architecture Tweaking and Performance Improvement ......
133
9.7 Strategies for the Micro-architecture Design of Processor ....
134
9.8 Chapter Summary .................................
138
10 Design Constraints and SDC Commands ....................
139
10.1 Important Design Concepts ..........................
140
10.1.1 Clock Tree ................................
140
10.1.2 Reset Tree ................................
140
10.1.3 Clock and Reset Strategies ....................
141
10.1.4 What Impacts on Design Performance? ...........
141
10.2 How to Interpret the Constraints ......................
142
10.2.1 Area Constraints ............................
142
10.2.2 Speed Constraints ...........................
142
10.2.3 Power Constraints...........................
143
10.3 Issues in the Design ...............................
143
10.4 Important SDC Commands Used During Synthesis .........
143
10.4.1 Synopsys DC Commands .....................
144
10.4.2 Checking of the Design ......................
145
10.4.3 Clock Defifinitions ...........................
145
10.4.4 Skew Defifinition ............................
146
10.4.5 Defifining Input and Output Delay ................
147
10.4.6 Specifying the Minimum (min) and Maximum (max)
Delay ....................................
147
10.4.7 Design Synthesis ...........................
149
10.4.8 Save the Design ............................
149
10.5 Constraint Validation ...............................
149
10.6 Commands for the DRC, Power, and Optimization .........
150
10.7 Chapter Summary .................................
151
11 Design Synthesis and Optimization Using RTL Tweaks .........
153
11.1 ASIC Synthesis...................................
153
11.2 Synthesis Guidelines ...............................
154
11.3 FSM Design and Synthesis ..........................
155
11.4 Strategies for the Complex FSM Controllers..............
158
11.5 How RTL Tweaks Are Useful During Synthesis? ..........
158
11.6 Synthesis Optimization Techniques Using RTL Tweaks .....
165
11.6.1 Resource Allocation .........................
165
11.6.2 Dead Zone Elimination .......................
167
11.6.3 Use of Parentheses ..........................
171
11.6.4 Grouping the Terms .........................
173
xvi
Contents11.7 FPGA Synthesis ..................................
175
11.8 Chapter Summary .................................
177
12 Synthesis and Optimization Techniques .....................
179
12.1 Introduction .....................................
179
12.2 Synthesis Using Design Compiler .....................
180
12.3 Synthesis and Optimization Flow ......................
182
12.4 Area Optimization Techniques ........................
186
12.4.1 Avoid Use of Combinational Logic as Individual
Block ....................................
187
12.4.2 Avoid Use of Glue Logic Between Two Modules ...
187
12.4.3 Use of set_max_area Attribute ..................
188
12.4.4 Area Report ...............................
189
12.5 Design Partitioning and Structuring ....................
190
12.6 Compilation Strategy ...............................
192
12.6.1 Top-Down Compilation ......................
192
12.6.2 Bottom-Up Compilation ......................
193
12.7 Chapter Summary .................................
193
13 Design Optimization and Scenarios .........................
195
13.1 Design Rule Constraints (DRC) .......................
195
13.1.1 max_fanout ...............................
196
13.1.2 max_transition .............................
196
13.1.3 max_capacitance ............................
197
13.2 Clock Defifinitions and Latency ........................
198
13.2.1 Clock Network Latency ......................
198
13.2.2 Generated Clock ............................
198
13.2.3 Clock Muxing and False Paths .................
199
13.2.4 Clock Gating ..............................
199
13.3 Commands Useful During Design Synthesis and
Optimization ..................................... 200
13.3.1 set_dont_use ............................... 201
13.3.2 set_dont_touch ............................. 201
13.3.3 set_prefer ................................. 202
13.3.4 Command for the Design Flattening ............. 202
13.3.5 Commands Used for Structuring ................ 203
13.3.6 Group and Ungroup Commands ................ 203
13.4 Timing Optimization and Performance Improvement ........ 204
13.4.1 Design Compilation with ‘map_effort high’ ........ 204
13.4.2 Logical Flattening ........................... 205
13.4.3 Use of group_path Command .................. 205
13.4.4 Submodule Characterizing ..................... 208
13.4.5 Register Balancing .......................... 209
13.5 FSM Optimization................................. 209
Contents
xvii13.6 Fixing Hold Violations ............................. 210
13.7 Report Command ................................. 211
13.7.1 report_qor ................................ 211
13.7.2 report_constraints ........................... 212
13.7.3 report_contraints_all ......................... 212
13.8 Multicycle Paths .................................. 214
13.9 Chapter Summary ................................. 214
14 Design for Testability ................................... 217
14.1 What Is Need of DFT? ............................. 217
14.2 Testing for Faults in the Design ....................... 218
14.3 Testing ......................................... 218
14.4 Strategies Used During the DFT ...................... 219
14.5 Scan Methods .................................... 220
14.5.1 Mux-Based Scan ........................... 221
14.5.2 Boundary Scan ............................. 221
14.5.3 Built-In Self-Test (BIST) ..................... 221
14.6 Scan Insertion .................................... 223
14.7 Challenges During the DFT .......................... 223
14.8 DFT Flow and Test Compiler Commands ............... 224
14.9 The Scan Design Rules to Avoid DRC Violations ......... 224
14.10 Chapter Summary ................................. 227
15 Timing Analysis ....................................... 229
15.1 Introduction ..................................... 229
15.2 What Are Timing Paths for Design .................... 230
15.2.1 Input to Reg Path ........................... 231
15.2.2 Reg to Output Path .......................... 231
15.2.3 Reg to Reg Path ............................ 231
15.2.4 Input to Output Path ......................... 232
15.3 Let Us Specify the Timing Goals ...................... 232
15.4 Timing Reports ................................... 235
15.5 Strategies to Fix Timing Violations .................... 236
15.5.1 Fixing Setup Violations in the Design ............ 238
15.5.2 Hold Violation Fix .......................... 242
15.5.3 Timing Exceptions .......................... 242
15.6 Chapter Summary ................................. 242
16 Physical Design ........................................ 245
16.1 Physical Design Flow .............................. 245
16.2 Foundation and Important Terms ...................... 246
16.3 Floor Planning and Power Planning .................... 248
16.4 Power Planning ................................... 249
16.5 Clock Tree Synthesis............................... 251
16.6 Place and Route .................................. 252
xviii
Contents16.7 Routing ........................................ 253
16.8 Back Annotation .................................. 255
16.9 Signoff STA and Layout ............................ 255
16.10 Chapter Summary ................................. 257
Reference ............................................. 258
17 Case Study: Processor ASIC Implementation ................. 259
17.1 Functional Understanding ........................... 259
17.2 Strategies During Architecture Design .................. 260
17.3 Micro-architecture Strategies ......................... 263
17.4 Strategies During RTL Design and Verifification ........... 265
17.5 The Sample Script Used During Synthesis ............... 267
17.6 Synthesis Issues and Fixes........................... 267
17.7 Pre-layout STA Issues .............................. 268
17.8 Physical Design Issues ............................. 269
17.9 Chapter Summary ................................. 270
18 Programmable ASIC.................................... 271
18.1 Programmable ASIC ............................... 271
18.2 Design Flow ..................................... 273
18.3 Modern FPGA Fabric and Elements .................... 274
18.4 RTL Design and Verifification ......................... 279
18.5 FPGA Synthesis .................................. 283
18.5.1 Arithmetic Operators and Synthesis .............. 283
18.5.2 Relational Operator and Synthesis ............... 284
18.5.3 Equality Operator Synthesis ................... 287
18.6 Design at Fabric Level ............................. 288
18.7 Chapter Summary ................................. 290
19 Prototyping Design ..................................... 293
19.1 FPGAs for Prototyping ............................. 293
19.2 Synthesis Strategies During Prototyping ................. 295
19.2.1 Fast Synthesis for Initial Resource Estimation ...... 295
19.2.2 Incremental Synthesis ........................ 295
19.3 Constraints During FPGA Synthesis .................... 297
19.4 Important Considerations and Tweaks .................. 299
19.5 IO Pad Synthesis for FPGA .......................... 301
19.6 Prototyping Tools ................................. 301
19.7 Chapter Summary ................................. 301
20 Case Study: IP Design and Development .................... 303
20.1 IP Design and Development ......................... 303
20.2 What We Consider During the IP Selection .............. 304
20.3 Strategies Useful During the IP Design ................. 304
20.4 Prototyping Using Multiple FPGA ..................... 307
Contents
xix20.5 H.264. Encoder IP Design and Development ............. 309
20.5.1 Features and Micro-architecture Design Strategies ... 309
20.5.2 Strategies During RTL Design and Verifification ..... 310
20.5.3 Strategies During Synthesis and DFT............. 311
20.5.4 Strategies During Pre-layout STA ............... 311
20.5.5 Strategies During Physical Design ............... 312
20.6 ULSI and ASIC Design ............................. 312
20.7 Chapter Summary ................................. 313
Appendix A .................................................
315
Appendix B .................................................
321
Bibliography ................................................
323
Index ......................................................
325
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