实例介绍
【实例简介】HDMI2.1协议
【实例截图】
【实例截图】
【核心代码】
Table of Contents
57
Preface.........................................................................................................................................................................2
58
Notice ...............................................................................................................................................................................2
59
Document Revision History...............................................................................................................................................3
60
Intellectual Property.........................................................................................................................................................4
61
Contact Information .........................................................................................................................................................4
62
1
Introduction, Purpose, and Scope.......................................................................................................................25
63
2
Overview ............................................................................................................................................................25
64
3
References..........................................................................................................................................................27
65
Normative References........................................................................................................................................27
66
3.1.1
References Incorporated From HDMI 1.4b ................................................................................................27
67
3.1.2
References Introduced in This Specification ..............................................................................................27
68
Informative References ......................................................................................................................................29
69
Usages and Conventions ....................................................................................................................................29
70
4
Definitions..........................................................................................................................................................30
71
Conformance Levels............................................................................................................................................30
72
Glossary of Terms...............................................................................................................................................31
73
4.2.1
Terms Incorporated From HDMI 1.4b (Informative)..................................................................................31
74
4.2.2
Terms Defined in This Specification ...........................................................................................................34
75
Acronyms............................................................................................................................................................38
76
4.3.1
Acronyms Incorporated from HDMI 1.4b (Informative).............................................................................38
77
4.3.2
Acronyms that are introduced by This Specification..................................................................................40
78
5
Cables and Connectors .......................................................................................................................................42
79
Overview of Connectors and Cables...................................................................................................................42
80
Connector Pin Assignments................................................................................................................................42
81
Contact sequence ...............................................................................................................................................43
82
Connector Mechanical Performance ..................................................................................................................43
83
Connector Electrical Characteristics...................................................................................................................43
84
Connector Environmental Characteristics ..........................................................................................................43
85
5.6.1
Environmental Performance ......................................................................................................................43
86
Connector Drawings...........................................................................................................................................43
87
5.7.1
Type A with Power Receptacle Mating Interface Dimensions ...................................................................43
88
5.7.2
Type D with Power Receptacle Mating Interface Dimensions ...................................................................47
89
Category 3 Cable Assembly Characteristics........................................................................................................49
90
5.8.1
Category 3 Cable Assembly Radiated Emissions Requirements.................................................................51
91
5.8.1.1 Cable Construction Guidelines for EMI Reduction (Informative)...........................................................51
92
Category 3 Cable Assembly Characteristics........................................................................................................52
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Category 3 Contact Sequence.............................................................................................................................53
94
Category 3 Connector Mechanical Performance................................................................................................53
95
Category 3 Connector Electrical Performance....................................................................................................54
96
5.12.1
Data0±, Data1±, Data2±, and Data3±.........................................................................................................54
97
5.12.2
All other pins..............................................................................................................................................57
98
Category 3 Connector Environmental Characteristics........................................................................................57
99
6
Link Layer ...........................................................................................................................................................58
100
340 Mcsc to 600 Mcsc TMDS Character Rate Support .......................................................................................58
101
6.1.1
Electrical Characteristics for TMDS Character Rate above 340 Mcsc and up to 600 Mcsc ........................58
102
6.1.1.1 TMDS Overview......................................................................................................................................58
103
6.1.1.2 Jitter and Eye Diagram Measurements ..................................................................................................59
104
6.1.1.3 Reference Cable Equalizer......................................................................................................................59
105
6.1.1.4 HDMI Source TMDS Characteristics .......................................................................................................61
106
6.1.1.5 HDMI Sink TMDS Characteristics............................................................................................................62
107
6.1.2
Scrambling for EMI/RFI Reduction with TMDS coding ...............................................................................64
108
6.1.2.1 Operating Modes Overview ...................................................................................................................65
109
6.1.2.2 Scrambling LFSR......................................................................................................................................67
110
6.1.2.3 Scrambling Video Data, Data Island, and Guard Bands..........................................................................68
111
6.1.2.4 Scrambler Synchronization Control Periods...........................................................................................70
112
6.1.2.4.1 CTS Testing Considerations..............................................................................................................70
113
6.1.2.5 Scrambled Control Periods.....................................................................................................................71
114
6.1.3
Control........................................................................................................................................................72
115
6.1.3.1 Scrambling Control .................................................................................................................................72
116
6.1.3.2 Control for TMDS Bit Period/TMDS Clock-Period Ratio .........................................................................73
117
Character Error Detection ..................................................................................................................................74
118
6.2.1
Feature Overview.......................................................................................................................................74
119
6.2.2
Error Counters............................................................................................................................................76
120
6.2.3
Reference Implementation ........................................................................................................................77
121
Auxiliary Channel Electrical Characteristics........................................................................................................84
122
6.3.1
CEC..............................................................................................................................................................84
123
FRL Electrical Characteristics..............................................................................................................................85
124
6.4.1
Electrical Characteristics for Fixed Bit Rates of 3, 6, 8, 10, and 12 Gbps....................................................86
125
6.4.1.1 Jitter and Eye Diagram Measurements ..................................................................................................86
126
6.4.1.2 Reference Cable Equalizer......................................................................................................................86
127
6.4.1.3 16b18b mode Source Characteristics.....................................................................................................88
128
6.4.1.4 16b18b mode Sink Characteristics .........................................................................................................89
129
6.4.2
Fixed Rate Link Training..............................................................................................................................93
130
6.4.2.1 Link Training Control ..............................................................................................................................93
131
6.4.2.2 Link Training Pattern ..............................................................................................................................94
132
6.4.2.3 Link Training Procedure..........................................................................................................................96
133
Fixed Rate Link - Link Layer.................................................................................................................................97
134
6.5.1
FRL Packets.................................................................................................................................................99
135
6.5.1.1 FRL Packets: Gap ................................................................................................................................. 100
136
6.5.1.2 FRL Packets: Active Video, Uncompressed.......................................................................................... 101
137
6.5.1.3 FRL Packets: Active Video, Compressed.............................................................................................. 103
138
6.5.1.4 Management of Zero Padding in Active Video FRL Packets................................................................ 106
139
6.5.1.4.1 Active Video FRL Packet Loading Case 1: MOD(Hactivebytes,6)=0 ................................................. 107
140
6.5.1.4.2 Active Video FRL Packet Loading Case 2: MOD(Hactivebytes,6)=1 ................................................. 108
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6.5.1.4.3 Active Video FRL Packet Loading Case 3: MOD(Hactivebytes,6)=2 ................................................. 109
142
6.5.1.4.4 Active Video FRL Packet Loading Case 4: MOD(Hactivebytes,6)=3 ................................................. 110
143
6.5.1.4.5 Active Video FRL Packet Loading Case 5: MOD(Hactivebytes,6)=4 ................................................. 111
144
6.5.1.4.6 Active Video FRL Packet Loading Case 6: MOD(Hactivebytes,6)=5 ................................................. 112
145
6.5.1.5 Video Blanking Period Coding ............................................................................................................. 113
146
6.5.2
FRL Character Blocks ............................................................................................................................... 115
147
6.5.3
FRL Super Block ....................................................................................................................................... 116
148
6.5.4
Reed Solomon (RS) Forward Error Correction (FEC) ............................................................................... 117
149
6.5.4.1 Reed Solomon Parity Data Source, Three Lane Operation.................................................................. 118
150
6.5.4.2 Reed Solomon Parity Data Source, Four Lane Operation.................................................................... 120
151
6.5.5
Mapping Character Blocks onto FRL Lanes.............................................................................................. 126
152
6.5.5.1 Three Lane Operation.......................................................................................................................... 126
153
6.5.5.2 Four Lane Operation............................................................................................................................ 127
154
6.5.6
Data Flow Metering................................................................................................................................. 132
155
6.5.6.1 Data Flow Metering Requirement....................................................................................................... 133
156
6.5.6.2 Data Flow Metering Computations..................................................................................................... 134
157
6.5.7
16b18b Coding for FRL ............................................................................................................................ 140
158
6.5.8
Scrambling for EMI/RFI Reduction with 16b18b coding.......................................................................... 142
159
6.5.8.1 Scrambling LFSR for 16b18b coding .................................................................................................... 142
160
7
Video Extensions ..............................................................................................................................................145
161
YCBCR 4:2:0 Pixel Encoding............................................................................................................................... 145
162
7.1.1
Deep Color 4:2:0 Pixel Encoding and Packing ......................................................................................... 147
163
7.1.2
Signaling for YCBCR 4:2:0 Pixel Encoding.................................................................................................. 149
164
Colorimetry...................................................................................................................................................... 150
165
7.2.1
Default Colorimetry................................................................................................................................. 150
166
7.2.2
BT.2020 Colorimetry................................................................................................................................ 150
167
Video Quantization Ranges............................................................................................................................. 151
168
7.3.1
Video Quantization Ranges Signaling (RGB)............................................................................................ 151
169
7.3.2
Video Quantization Ranges Signaling (YCC) ............................................................................................ 152
170
3D Video Extension.......................................................................................................................................... 152
171
7.4.1
3D OSD Disparity Indication .................................................................................................................... 152
172
7.4.2
3D Dual-View Signaling............................................................................................................................ 155
173
7.4.3
3D Independent View Signaling .............................................................................................................. 155
174
7.4.3.1 3D_ViewDependency .......................................................................................................................... 155
175
7.4.3.2 3D_Preferred2DView .......................................................................................................................... 156
176
Additional Video Formats................................................................................................................................ 156
177
Variable Refresh Rate and Fast Vactive .......................................................................................................... 156
178
7.6.1
Setting FVA_Factor.................................................................................................................................. 158
179
7.6.2
Determining fpixel,FVA................................................................................................................................. 159
180
7.6.3
Setting MVRR............................................................................................................................................. 159
181
7.6.4
VRRFVA Extended Metadata Structure ................................................................................................... 160
182
Compressed Video Transport .......................................................................................................................... 161
183
7.7.1
Compressed Video Transport.................................................................................................................. 161
184
7.7.1.1 Video Timing with Compressed Video Transport................................................................................ 161
185
7.7.1.1.1 Vertical Timing for Compressed Video Transport......................................................................... 162
186
7.7.1.1.2 Horizontal Timing for Compressed Video Transport .................................................................... 163
187
7.7.1.1.3 Data Metering for Compressed Video Transport.......................................................................... 164
188
7.7.1.1.4 Selection of the Nominal Recommended bpp.............................................................................. 164
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7.7.1.1.5 Utilizing Hblank Period to transmit additional video data............................................................ 166
190
7.7.1.1.6 Deep Color and Compressed Video Transport.............................................................................. 167
191
7.7.2
VESA DSC Picture Parameter Set (PPS).................................................................................................... 167
192
7.7.2.1 Slice Width Determination .................................................................................................................. 170
193
7.7.2.2 Slice Height Determination ................................................................................................................. 172
194
7.7.2.3 Configuring bits_per_pixel .................................................................................................................. 172
195
7.7.2.4 Determination of available Audio Bandwidth ..................................................................................... 173
196
7.7.2.5 Compressed Video Transport and Content Protection ....................................................................... 176
197
7.7.2.6 Discovery ............................................................................................................................................. 176
198
7.7.2.6.1 Receiver Buffer Sizing Requirements for VESA DSC...................................................................... 176
199
8
Packet Definitions.............................................................................................................................................178
200
3D Audio Sample Packet.................................................................................................................................. 179
201
One Bit 3D Audio Sample Packet..................................................................................................................... 180
202
Audio Metadata Packet................................................................................................................................... 181
203
8.3.1
Audio Metadata Packet for 3D Audio...................................................................................................... 184
204
8.3.2
Audio Metadata Packet for Multi-Stream Audio..................................................................................... 189
205
Multi-Stream Audio Sample Packet................................................................................................................. 192
206
One Bit Multi-Stream Audio Sample Packet.................................................................................................... 193
207
Audio InfoFrame.............................................................................................................................................. 194
208
Dynamic Range and Mastering InfoFrame...................................................................................................... 194
209
Extended Metadata Packet............................................................................................................................. 194
210
9
Audio Extensions..............................................................................................................................................200
211
Supported Audio Formats................................................................................................................................ 200
212
Supported Audio Rates.................................................................................................................................... 201
213
9.2.1
Recommended N and Expected CTS Values............................................................................................ 202
214
9.2.1.1 16b18b Audio Clock Regeneration ...................................................................................................... 207
215
3D Audio.......................................................................................................................................................... 207
216
9.3.1
Maximum 3D Audio Transport Capacity ................................................................................................. 207
217
9.3.2
3D Audio Channel/Speaker Assignment.................................................................................................. 209
218
9.3.3
3D Audio Data Packetization ................................................................................................................... 209
219
9.3.4
One Bit 3D Audio Packetization............................................................................................................... 213
220
9.3.5
Audio Metadata Packetization for 3D Audio........................................................................................... 213
221
9.3.6
CTA 3D Audio Channel/Speaker Assignment .......................................................................................... 213
222
Multi-Stream Audio ......................................................................................................................................... 214
223
9.4.1
Multi-Stream Audio Data Packetization .................................................................................................. 214
224
9.4.2
One Bit Multi-Stream Audio Packetization.............................................................................................. 217
225
9.4.3
Audio Metadata Packetization for Multi-Stream Audio.......................................................................... 217
226
Enhanced Audio Return Channel (eARC) ......................................................................................................... 218
227
9.5.1
Overview ................................................................................................................................................. 218
228
9.5.1.1 eARC Audio transport and Communications....................................................................................... 219
229
9.5.1.2 eARC Differential Audio Signaling ....................................................................................................... 220
230
9.5.1.3 Common Mode Data Channel Communication Signaling ................................................................... 222
231
9.5.2
eARC Audio.............................................................................................................................................. 223
232
9.5.2.1 Audio Falling Edge Modulation. .......................................................................................................... 223
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9.5.2.2 Multi-Channel and 192KHz Sampled Audio......................................................................................... 224
234
9.5.2.2.1 Layout ........................................................................................................................................... 224
235
9.5.2.2.2 Channel Status Bits ....................................................................................................................... 224
236
9.5.2.3 Error Correction for 16 bit Audio......................................................................................................... 225
237
9.5.3
eARC Common Mode Data Channel........................................................................................................ 227
238
9.5.3.1 Basic Common Mode Data Channel Operation................................................................................... 227
239
9.5.3.2 eARC Discovery & Disconnect process................................................................................................ 227
240
9.5.3.3 eARC Discovery / Disconnect State Descriptions ................................................................................ 227
241
9.5.3.3.1 Discovery process for eARC RX ..................................................................................................... 230
242
9.5.3.3.2 Disconnection process for eARC RX.............................................................................................. 230
243
9.5.3.3.3 Discovery process for eARC TX ..................................................................................................... 231
244
9.5.3.3.4 Disconnection process for eARC TX .............................................................................................. 231
245
9.5.3.4 Interaction between eARC and legacy ARC modes............................................................................. 231
246
9.5.3.5 COMMA Sequence during Discovery................................................................................................... 231
247
9.5.3.6 Packet Structure .................................................................................................................................. 233
248
9.5.3.7 Commands........................................................................................................................................... 235
249
9.5.3.8 Data ..................................................................................................................................................... 236
250
9.5.3.9 Transactions ........................................................................................................................................ 237
251
9.5.3.10
eARC Heartbeat and Status Bits ...................................................................................................... 240
252
9.5.3.11
Audio Latency Control ..................................................................................................................... 243
253
9.5.4
eARC RX Capabilities and Status Data Structure ..................................................................................... 246
254
9.5.4.1 eARC Capabilities and Status Data Structure Communication............................................................ 246
255
9.5.4.2 eARC Capability Data Structure........................................................................................................... 247
256
9.5.5
Electrical Specifications........................................................................................................................... 249
257
9.5.5.1 Differential Mode Electrical Specifications.......................................................................................... 251
258
9.5.5.2 Common Mode Data Channel Electrical Specifications....................................................................... 251
259
9.5.5.3 Cable Assembly Electrical Specifications............................................................................................. 252
260
10
Control and Configuration.............................................................................................................................253
261
Use of the AVI InfoFrame in This Specification ................................................................................................ 253
262
10.1.1
Signaling of 3D Video Formats ................................................................................................................ 253
263
HDMI Forum Vendor Specific InfoFrame ......................................................................................................... 253
264
10.2.1
HF-VSIF Transitions.................................................................................................................................. 259
265
E-EDID.............................................................................................................................................................. 259
266
10.3.1
Signaling of supported Video Formats.................................................................................................... 259
267
10.3.2
HDMI Forum Vendor Specific Data Block ................................................................................................ 260
268
10.3.3
HDMI Audio Data Block ........................................................................................................................... 266
269
10.3.4
HDR Static Metadata Data Block ............................................................................................................. 269
270
10.3.5
CTA-861-G HDR Dynamic Metadata Data Block...................................................................................... 269
271
Status and Control Data Channel .................................................................................................................... 270
272
10.4.1
Status and Control Data Channel Structure ............................................................................................ 271
273
10.4.1.1
Format Overview............................................................................................................................. 271
274
10.4.1.2
Version............................................................................................................................................. 271
275
10.4.1.3
Update Flags.................................................................................................................................... 272
276
10.4.1.3.1 Update Flag Polling ..................................................................................................................... 273
277
10.4.1.4
TMDS Configuration ........................................................................................................................ 275
278
10.4.1.5
Scrambler Status.............................................................................................................................. 275
279
10.4.1.6
Configuration................................................................................................................................... 276
280
10.4.1.7
Status Flags...................................................................................................................................... 280
281
10.4.1.8
Character Error Detection ............................................................................................................... 283
282
10.4.1.9
Test Configuration........................................................................................................................... 284
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10.4.1.10 Manufacturer Specific Registers...................................................................................................... 285
284
10.4.2
Timing...................................................................................................................................................... 286
285
10.4.3
Data Transfer Protocols........................................................................................................................... 287
286
10.4.4
SCDC Read Request ................................................................................................................................. 289
287
10.4.5
SCDC Sink................................................................................................................................................. 292
288
10.4.6
SCDC Source ............................................................................................................................................ 292
289
Relative Audio / Video Latency........................................................................................................................ 293
290
Auto Lipsync Correction Feature...................................................................................................................... 294
291
10.6.1
EDID Latency Info .................................................................................................................................... 294
292
10.6.1.1
Devices without HDMI output......................................................................................................... 294
293
10.6.1.2
Devices with HDMI output .............................................................................................................. 295
294
10.6.1.3
Supporting a Range of Latency Values ............................................................................................ 297
295
10.6.2
Compensation ......................................................................................................................................... 297
296
Supporting Dynamic Latency Changes: Dynamic Auto Lipsync ....................................................................... 298
297
10.7.1
CEC transport for Dynamic Auto Lipsync................................................................................................. 300
298
10.7.2
Dynamic Auto Lipsync operation............................................................................................................. 302
299
10.7.3
Latency of TV’s Audio Outputs................................................................................................................ 304
300
10.7.4
1 Auto Low Latency Mode....................................................................................................................... 305
301
10.7.4.1
Additional ALLM Requirements for Repeaters................................................................................ 306
302
Handling of Hot Plug Detect (HPD) and 5V Power signals ............................................................................ 307
303
Discovery Algorithm ........................................................................................................................................ 307
304
Extended Metadata Transport .................................................................................................................... 308
305
10.10.1
General EM Packet Transmission Requirements................................................................................. 308
306
10.10.1.1 FAPA Definition ............................................................................................................................... 308
307
10.10.1.2 EM Packet Transmission Requirements.......................................................................................... 309
308
10.10.1.3 EM Timeout..................................................................................................................................... 311
309
10.10.2
Extended Metadata Types................................................................................................................... 312
310
10.10.2.1 Vendor Specific EM Data Sets ......................................................................................................... 312
311
10.10.2.2 Compressed Video Transport EM Packets ...................................................................................... 312
312
10.10.2.3 CTA-861-G Dynamic HDR InfoFrame ............................................................................................... 313
313
10.10.2.4 VRRFVA Extended Metadata Packets.............................................................................................. 314
314
Multi-Touch ................................................................................................................................................. 315
315
10.11.1
Standards............................................................................................................................................. 315
316
10.11.2
Feature Positioning.............................................................................................................................. 316
317
10.11.3
Feature Discovery and Configuration.................................................................................................. 316
318
10.11.4
Profiles................................................................................................................................................. 316
319
10.11.5
Transport-Dependent Mapping........................................................................................................... 317
320
Power Status and Configuration Request Update Signaling ....................................................................... 317
321
10.12.1
Updates to Power Status related to Power Delivery........................................................................... 317
322
10.12.2
Conformance Levels............................................................................................................................ 318
323
11
CEC 2.0, Consumer Electronic Control ...........................................................................................................319
324
Introduction..................................................................................................................................................... 319
325
11.1.1
Relationship and compatibility with earlier version................................................................................ 319
326
11.1.2
Behavior with earlier versions................................................................................................................. 321
327
Feature overview............................................................................................................................................. 322
328
11.2.1
Conformance Levels................................................................................................................................ 322
329
11.2.2
Classification and declaration of features............................................................................................... 322
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11.2.2.1
Mandatory features ........................................................................................................................ 322
331
11.2.2.2
Optional features............................................................................................................................. 324
332
11.2.2.3
Other features in CEC 1.4b .............................................................................................................. 325
333
11.2.2.4
Other features using CEC messaging............................................................................................... 325
334
11.2.3
Feature Discovery.................................................................................................................................... 325
335
11.2.4
Version Discovery.................................................................................................................................... 326
336
Addressing ....................................................................................................................................................... 326
337
11.3.1
Physical Addresses .................................................................................................................................. 326
338
11.3.2
Device Types and Logical Addresses ....................................................................................................... 327
339
11.3.3
Logical Address allocation ....................................................................................................................... 330
340
11.3.4
Logical Addressing for Special Devices.................................................................................................... 331
341
11.3.5
Logical Addressing for Recording Devices............................................................................................... 332
342
Polling.............................................................................................................................................................. 332
343
Power state changes ....................................................................................................................................... 333
344
11.5.1
Normal Power State Changes – Sending ................................................................................................. 333
345
11.5.2
Normal Power State Changes – Receiving............................................................................................... 334
346
11.5.3
Power State Changes when using mixed system (with legacy devices) - Sending .................................. 334
347
11.5.4
Power State Changes when using mixed system (with legacy devices) - Receiving................................ 335
348
11.5.5
Power States and Power State Transitions ............................................................................................. 335
349
11.5.6
System Standby ....................................................................................................................................... 338
350
11.5.7
Recording ................................................................................................................................................ 339
351
Remote Control Pass Through ......................................................................................................................... 340
352
11.6.1
Relationship with other features............................................................................................................. 340
353
11.6.2
Feature Description................................................................................................................................. 340
354
11.6.3
Press and Hold Operation ....................................................................................................................... 342
355
11.6.4
RC Button Forwarding Principles of Operation ....................................................................................... 343
356
11.6.5
Reporting of capabilities related to Remote Control Pass Through........................................................ 344
357
11.6.6
Other uses of <User Control Pressed> .................................................................................................... 345
358
Audio Return Channel Control ......................................................................................................................... 345
359
Vendor Specific Messages ............................................................................................................................... 345
360
Other topics and clarifications......................................................................................................................... 347
361
11.9.1
Electrical parameters............................................................................................................................... 347
362
11.9.2
Measuring data bit timing ....................................................................................................................... 348
363
11.9.3
Re-transmissions and errors.................................................................................................................... 348
364
11.9.4
Protocol Extensions................................................................................................................................. 349
365
11.9.5
Message response timing........................................................................................................................ 349
366
11.9.6
Source Declaration .................................................................................................................................. 350
367
11.9.7
Protocol General Rules............................................................................................................................ 350
368
11.9.8
Feature Abort.......................................................................................................................................... 350
369
11.9.9
Routing Control ....................................................................................................................................... 351
370
11.9.10
Device OSD Name Transfer ................................................................................................................. 352
371
11.9.11
System Audio Control.......................................................................................................................... 352
372
11.9.11.1 Reporting Audio Status.................................................................................................................... 353
373
11.9.11.2 System Audio Mode and Volume Control ....................................................................................... 354
374
11.9.11.3 Discovering the Amplifier’s Audio Format support......................................................................... 355
375
11.9.11.4 Usage of remote control pass through............................................................................................ 356
376
Message tables............................................................................................................................................ 356
377
Message Dependencies............................................................................................................................... 375
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Operand Descriptions.................................................................................................................................. 377
379
12
Power Delivery .............................................................................................................................................389
380
Support Requirements based on Device Capabilities ...................................................................................... 390
381
Power Delivery Limits ...................................................................................................................................... 391
382
12.2.1
Over-Current protection.......................................................................................................................... 392
383
12.2.1.1
In-rush current................................................................................................................................. 392
384
12.2.1.2
Normal operation............................................................................................................................ 392
385
12.2.1.3
IR Drop Detection............................................................................................................................ 392
386
Sink as PSource Cable Attach/Detach Detection ............................................................................................. 392
387
HPD when Power Delivery is Active ................................................................................................................. 396
388
Initial Power State ........................................................................................................................................... 396
389
Power Negotiation and Configuration ............................................................................................................ 396
390
12.6.1
Source as PSource State Machine ........................................................................................................... 398
391
12.6.2
Source as PSink State Machine................................................................................................................ 404
392
12.6.3
Sink as PSource State Machine................................................................................................................ 405
393
12.6.4
Sink as PSink State Machine .................................................................................................................... 405
394
Power Delivery while in Standby ..................................................................................................................... 405
395
Special Case Power Applications ..................................................................................................................... 406
396
Power Delivery in Repeaters............................................................................................................................ 406
397
Dead Battery Operation .............................................................................................................................. 406
398
Appendix A 3D Audio and Multi-Stream Audio Applications (Informative)...........................................................408
399
A.1
Example Scenario for 3D Audio ....................................................................................................................... 408
400
A.2
Example scenario for Multi-Stream Audio....................................................................................................... 414
401
A.3
Example use-cases for Multi-Stream Audio..................................................................................................... 418
402
Appendix B 3D Audio Speaker Placement & Channel Allocation (informative).....................................................424
403
Appendix C Recommended N and Expected CTS Values.......................................................................................426
404
Appendix D Dynamic Auto Lipsync and Source Devices (Informative)...................................................................435
405
Appendix E Signaling in AVI InfoFrame and VSIF for various Video Formats.........................................................436
406
Appendix F
Use of H14b VSIF for 3D-2D Transitions (Informative) .......................................................................439
407
Appendix G Auto Low Latency Mode (Informative) ..............................................................................................440
408
G.1
The Relationship Between ALLM and the Content Type Feature..................................................................... 440
409
Appendix H eARC Capabilities and E-EDID Relationship Examples (informative) ..................................................442
410
Appendix I
Advanced DDC...................................................................................................................................445
411
12.10.1
Overview ............................................................................................................................................. 445
412
12.10.2
AdDDC Layers...................................................................................................................................... 445
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12.10.3
Physical Layer ...................................................................................................................................... 446
414
12.10.3.1 Overview ......................................................................................................................................... 446
415
12.10.3.2 AdDDC Source Characteristics......................................................................................................... 449
416
12.10.3.3 AdDDC Sink Characteristics ............................................................................................................. 452
417
12.10.3.4 Cable Assembly Characteristics....................................................................................................... 455
418
12.10.4
Link Layer............................................................................................................................................. 456
419
12.10.4.1 AdDDC Capability Discovery ............................................................................................................ 456
420
12.10.4.2 Entering and Exiting......................................................................................................................... 456
421
12.10.4.3 Time Division Multiplexing (TDM) Mode......................................................................................... 459
422
12.10.5
Slot 0 Transport................................................................................................................................... 462
423
12.10.6
DDC Tunneling..................................................................................................................................... 464
424
12.10.7
Transport Layer ................................................................................................................................... 467
425
12.10.7.1 Transport Container Sub-layer........................................................................................................ 467
426
12.10.7.2 Fragmentation and Protocol Flow Control Sub-layer...................................................................... 473
427
12.10.8
Higher Layer Protocols ........................................................................................................................ 478
428
429
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Table of Figures
431
Figure 5-1: Type A with Power Receptacle Mating Interface Dimensions.........................................................................44
432
Figure 5-2: Type A with Power Plug Mating Interface Dimensions....................................................................................45
433
Figure 5-3: Type D with Power Receptacle Mating Interface Dimensions.........................................................................46
434
Figure 5-4: Type D with Power Plug Mating Interface Dimensions....................................................................................48
435
Figure 5-5: ACR between Data Lanes.................................................................................................................................49
436
Figure 5-6: Category 3 Cable Data Lane Attenuation Limits ..............................................................................................50
437
Figure 5-7: 12 Gbps TP1 Eye Mask for Category 3 cable test.............................................................................................50
438
Figure 5-8: 12Gbps TP2_EQ Eye Mask for Category 3 cable test .......................................................................................51
439
Figure 5-9: Differential Insertion Loss of Mated Connector...............................................................................................56
440
Figure 5-10: Differential ACR (Attenuation Crosstalk Ratio) of Mated Connector.............................................................56
441
Figure 6-1: TMDS Link Test Points......................................................................................................................................59
442
Figure 6-2: Reference Cable Equalizer for 3.4 Gbps < Rbit ≤ 6.0 Gbps................................................................................60
443
Figure 6-3: HDMI Source Test Point for Eye Diagram ........................................................................................................62
444
Figure 6-4: Eye diagram at TP2_EQ....................................................................................................................................63
445
Figure 6-5: Plots of the Functions defining horizontal and vertical dimensions for the eye diagram at TP2_EQ..............63
446
Figure 6-6: Overview of HDMI Data Transport periods......................................................................................................65
447
Figure 6-7: LFSR Diagram ...................................................................................................................................................67
448
Figure 6-8: HDMI Signals when 16b18b mode is active .....................................................................................................85
449
Figure 6-9: Reference CTLE for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps.................................................................87
450
Figure 6-10: Reference DFE for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps................................................................88
451
Figure 6-11: Eye diagram at TP2_EQ..................................................................................................................................90
452
Figure 6-12: Frequency Normalized Sink Sinusoidal Jitter Tolerance Curve. .....................................................................92
453
Figure 6-13: Link Training Status Machine in Source .........................................................................................................96
454
Figure 6-14: High level Video data flow .............................................................................................................................97
455
Figure 6-15: Overview of Steps to package a TMDSUnencoded Stream into an FRL stream, Four Lane Example...................99
456
Figure 6-16: FRL Packet Structure ................................................................................................................................... 100
457
Figure 6-17: Loading the First Active Video FRL Packet in a Video Line.......................................................................... 102
458
Figure 6-18: Relationship between uncompressed and compressed video timing ........................................................ 103
459
Figure 6-19: VESA DSC Output Bytes............................................................................................................................... 104
460
Figure 6-20: Loading compressed video data bytes into FRL packets, example shows omission of zero padding......... 105
461
Figure 6-21: Loading compressed video data bytes into FRL packets, example shows inclusion of zero padding ......... 106
462
Figure 6-22: Active Video FRL Packet Loading Case 1 – MOD(Hactivebytes,6) = 0 ............................................................ 107
463
Figure 6-23: Active Video FRL Packet Loading Case 2 – MOD(Hactivebytes,6) = 1 ............................................................ 108
464
Figure 6-24: Active Video FRL Packet Loading Case 3 – MOD(Hactivebytes,6) = 2 ............................................................ 109
465
Figure 6-25: Active Video FRL Packet Loading Case4 – MOD(Hactivebytes,6) = 3 ............................................................. 110
466
Figure 6-26: Active Video FRL Packet Loading Case5 – MOD(Hactivebytes,6) = 4 ............................................................. 111
467
Figure 6-27: Active Video FRL Packet Loading Case6 – MOD(Hactivebytes,6) = 5 ............................................................. 112
468
Figure 6-28: Loading the Video Blanking FRL Packets..................................................................................................... 114
469
Figure 6-29: Example of Repeat Count Compression...................................................................................................... 115
470
Figure 6-30: Character Block Structure ........................................................................................................................... 116
471
Figure 6-31: FRL SSB/SR and Super Block High Level Structure ...................................................................................... 116
472
Figure 6-32: Basic RS Encoder for use in conjunction with FRL Transmission................................................................. 118
473
Figure 6-33: Character Block 0, 1, 2, and 3 after concatenation of RS Parity Data, Three Lanes.................................... 119
474
Figure 6-34: Character Block 0 after concatenation of RS Parity Data, Four Lanes ........................................................ 122
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Figure 6-35: Character Block 1 after concatenation of RS Parity Data, Four Lanes ........................................................ 123
476
Figure 6-36: Character Block 2 after concatenation of RS Parity Data, Four Lanes ........................................................ 124
477
Figure 6-37: Character Block 3 after concatenation of RS Parity Data, Four Lanes ........................................................ 125
478
Figure 6-38: Character Block 0 as Transmitted on Three Lanes...................................................................................... 126
479
Figure 6-39: Character Block 0 as Transmitted on Four Lanes........................................................................................ 128
480
Figure 6-40: Character Block 1 as Transmitted on Four Lanes........................................................................................ 129
481
Figure 6-41: Character Block 2 as Transmitted on Four Lanes........................................................................................ 130
482
Figure 6-42: Character Block 3 as Transmitted on Four Lanes........................................................................................ 131
483
Figure 6-43: Packet Jitter when there is excess FRL bandwidth ..................................................................................... 132
484
Figure 6-44: Packet Jitter when there is insufficient FRL Bandwidth for real time video transmission.......................... 133
485
Figure 6-45: Determination of CFRLDifference ....................................................................................................................... 134
486
Figure 6-46: Placement of Start Super Block (SSB) and Scrambler Reset (SR) Characters.............................................. 142
487
Figure 7-1: YCBCR 4:2:0 mapping for progressive Video Formats.................................................................................... 146
488
Figure 7-2: Sub-sampling position of YCBCR 4:2:0 for progressive Video Formats.......................................................... 147
489
Figure 7-3: Relationship between uncompressed and compressed video timing .......................................................... 162
490
Figure 7-4: Comparison of Time Periods for Compressed Video Transport.................................................................... 163
491
Figure 9-1: Audio Clock Regeneration Model ................................................................................................................. 203
492
Figure 9-2: Example Audio Sample Timing for 3D Audio transmission with 480p/576p Video (Informative) ................ 211
493
Figure 9-3: Example Audio Sample Timing for 3D Audio transmission with 1080p Video (Informative)........................ 212
494
Figure 9-4: Example Audio Sample Timing for 3D Audio transmission with 1080p Video, Samples split across two video
495
lines (Informative)........................................................................................................................................................... 212
496
Figure 9-5: Example Audio Sample Timings for 2 Stream and 4 Stream Multi-Stream Audio transmission (Informative)
497
......................................................................................................................................................................................... 216
498
Figure 9-6: eARC overview .............................................................................................................................................. 219
499
Figure 9-7: eARC Functional Circuit Structure................................................................................................................. 220
500
Figure 9-8: Relationship between SPDIF and eARC Signals............................................................................................. 220
501
Figure 9-9: Differential Audio Signal ............................................................................................................................... 221
502
Figure 9-10: eARC Data Eye Diagram (TP2, eARC Source)............................................................................................... 221
503
Figure 9-11: Combined eARC Signal ................................................................................................................................ 223
504
Figure 9-12: eARC TX Audio Data Flow............................................................................................................................ 223
505
Figure 9-13: eARC RX Audio Data Flow ........................................................................................................................... 223
506
Figure 9-14: Audio transport using Falling-Edge Modulation ......................................................................................... 224
507
Figure 9-15: Insertion of Error Correction Syndrome Bits into Compressed Audio Stream............................................ 226
508
Figure 9-16: eARC TX (e.g. TV) Discovery and Disconnect State Diagram....................................................................... 228
509
Figure 9-17: eARC RX (e.g. Amplifier) Discovery and Disconnect State Diagram............................................................ 229
510
Figure 9-18: eARC COMMA Sequence............................................................................................................................. 232
511
Figure 9-19: Encoded eARC COMMA sequence .............................................................................................................. 232
512
Figure 9-20: eARC Common Mode Data Channel Command / data packet structure.................................................... 233
513
Figure 9-21: ECC in eARC Common Mode Data Channel Packets................................................................................... 233
514
Figure 9-22: Encoded command/data packets ............................................................................................................... 234
515
Figure 9-23: eARC Common Mode Data Channel Bit Timings......................................................................................... 234
516
Figure 9-24: eARC Common Mode Data Channel Transaction Timings.......................................................................... 234
517
Figure 9-25: eARC_READ Transaction at eARC TX (Master)............................................................................................ 238
518
Figure 9-26: eARC_READ Transaction at eARC RX (Slave)............................................................................................... 239
519
Figure 9-27: eARC_WRITE Transaction at TX (Master).................................................................................................... 239
520
Figure 9-28: eARC_WRITE Transaction at eARC RX (Slave) ............................................................................................. 239
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Figure 9-29: ERX_LATENCY_REQ Register Use Example ................................................................................................. 244
522
Figure 9-30: eARC example circuit depicting Differential Audio and Common Mode Data Channel Data ..................... 250
523
Figure 9-31: eARC Eye Diagram Mask at TP2, eARC Source for Audio data output........................................................ 250
524
Figure 10-1: SCDC Update Read ...................................................................................................................................... 287
525
Figure 10-2: SCDC Combined Format Read..................................................................................................................... 287
526
Figure 10-3: SCDC Write.................................................................................................................................................. 288
527
Figure 10-4: Read Request signal .................................................................................................................................... 290
528
Figure 10-5: Read Request signal with STOP condition................................................................................................... 291
529
Figure 10-6: Read Request Timeout................................................................................................................................ 292
530
Figure 10-7: EDID Latency Handling for a Repeater with Video Processing.................................................................... 295
531
Figure 10-8: EDID Latency Handling for an Amplifier...................................................................................................... 296
532
Figure 10-9: EDID Latency Handling for an Amplifier with Video Processing ................................................................. 297
533
Figure 10-10: Dynamic Auto Lipsync Example of Operation........................................................................................... 299
534
Figure 10-11: Example of the use of [Low Latency Mode] flag ....................................................................................... 302
535
Figure 10-12: TV reports updated latency value(s) and flags when changing latency.................................................... 303
536
Figure 10-13: TV reports current latency value(s) and flags upon request..................................................................... 303
537
Figure 10-14: Three-device scenario, initiation by Amplifier’s request .......................................................................... 304
538
Figure 10-15: Operation of audio delay when [Audio Output Compensated]=1 versus 2.............................................. 305
539
Figure 10-16: Timing of the FAPA Relative to the Video Timing, FAPA_start_location=0 .............................................. 310
540
Figure 10-17: Timing of the FAPA Relative to the Video Timing, FAPA_start_location=1 .............................................. 311
541
Figure 10-18: Scope of Multi-Touch definition covered by This Specification................................................................ 315
542
Figure 11-1: Logical Address Allocation (Clarified from H14b CEC Figure 8)................................................................... 331
543
Figure 11-2: A typical scenario for a device waking up (transitions #1 and #2).............................................................. 337
544
Figure 11-3: A typical scenario for a device waking up (transition #4) ........................................................................... 338
545
Figure 11-4: A typical scenario for the broadcast (system) Standby feature (from H14b CEC Figure 13) ...................... 338
546
Figure 11-5: A typical scenario for the Standby feature to a specific device (Clarified from H14b CEC Figure 14) ........ 339
547
Figure 11-6: A typical scenario where the user presses and quickly releases the same button (Clarified from H14b CEC
548
Figure 22) ........................................................................................................................................................................ 341
549
Figure 11-7: A typical scenario where the user quickly presses a second button........................................................... 341
550
Figure 11-8: The messages sent in the Vendor Specific Commands feature (from H14b CEC Figure 21)....................... 347
551
Figure 11-9: Example message flow, when a CEC Switch is manually switched (from H14b CEC Figure 12).................. 352
552
Figure 11-10: An example of TV and Amplifier implementing Press and Hold behavior (Clarified from H14b CEC Figure
553
32) ................................................................................................................................................................................... 353
554
Figure 11-11: A Typical Operation of the volume control where the user presses and quickly releases a button......... 354
555
Figure 11-12: An example of TV and STB implementing Press and Hold behavior......................................................... 355
556
Figure 11-13: Typical Operation to discover the Audio Format capability of an Amplifier (Clarified from H14b CEC Figure
557
34) ................................................................................................................................................................................... 356
558
Figure 12-1: Standard Power Delivery Cases .................................................................................................................. 389
559
Figure 12-2: Power Delivery with a Repeater, Simple Cases........................................................................................... 390
560
Figure 12-3: Power Delivery with a Repeater, Compound Cases.................................................................................... 390
561
Figure 12-4: Example of Possible Sink Device Cable Detach/Attach Detection .............................................................. 394
562
Figure 12-5: Initial Power Provisioning ........................................................................................................................... 395
563
Figure 12-6: Power Use Case: Source Operates as a PSink, Sink operates as a PSource ................................................ 397
564
Figure 12-7: Power Use Case: Source Operates as a PSource, Sink operates as a PSink ................................................ 398
565
Figure 12-8: Power Delivery State Machine for Sources Capable of functioning as a PSource ...................................... 400
566
Figure 12-9: AdDDC Channel Layers................................................................................................................................ 445
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Figure 12-10: AdDDC Electrical Circuitry ......................................................................................................................... 446
568
Figure 12-11: Differential AdDDC Signal Waveform from Source to Sink at TP1 without Backward Signal ................... 447
569
Figure 12-12: Differential AdDDC Signal Waveform from Sink to Source at TP2 without Forward Signal...................... 447
570
Figure 12-13: Differential AdDDC Signal Waveform at TP2 with Matching Waveform and Delay between Source and
571
Sink without Interconnection.......................................................................................................................................... 447
572
Figure 12-14: TP1 Input Eye Diagram for AdDDC Backward Signal................................................................................. 450
573
Figure 12-15: AdDDC Reference Cable Equalizer Gain Curve.......................................................................................... 451
574
Figure 12-16: TP2 Input Eye Diagram for AdDDC Forward Signal ................................................................................... 454
575
Figure 12-17: Category 3 Cable DDC Attenuation Limits – Informative.......................................................................... 455
576
Figure 12-18: AdDDC State Diagram ............................................................................................................................... 457
577
Figure 12-19: TDM Structure........................................................................................................................................... 459
578
Figure 12-20: TDM State Machine Example.................................................................................................................... 460
579
Figure 12-21: Slot 0 Transaction...................................................................................................................................... 462
580
Figure 12-22: Slot 0 Transport CRC Code Generator....................................................................................................... 463
581
Figure 12-23: DDC vs. DDC Tunneling Transactions........................................................................................................ 466
582
Figure 12-24: Slots 1…24 Channel................................................................................................................................... 467
583
Figure 12-25: Transport Container Transaction .............................................................................................................. 468
584
Figure 12-26: Transport Container CRC Code Generator................................................................................................ 469
585
Figure 12-27: Transport Container Credit Exchange Example ........................................................................................ 471
586
Figure 12-28: Transport Container structure .................................................................................................................. 472
587
Figure 12-29: Message Fragmentation Example............................................................................................................. 474
588
Figure 12-30: Unfair Transport Container Buffer Usage Example................................................................................... 475
589
Figure 12-31: Fair Transport Container Buffer Usage Example....................................................................................... 476
590
Figure 12-32: Protocol Flow Control Example................................................................................................................. 477
591
592
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Table of Tables
594
Table 5-1: Type A with Power Connector Pin Assignment.................................................................................................42
595
Table 5-2: Type D with Power Connector Pin Assignment.................................................................................................42
596
Table 5-3: Connector Contact Sequence for Type A Connector.........................................................................................43
597
Table 5-4: Cable Assembly Parameters..............................................................................................................................49
598
Table 5-5: Type A, Category 1, 2 vs. Category 3 Connector Pin Assignment Comparison .................................................52
599
Table 5-6: Type C, Category 1, 2 vs.to Category 3 Connector Pin Assignment Comparison ..............................................53
600
Table 5-7: Type D, Category 1, 2 vs. Category 3 Connector Pin Assignment Comparison .................................................53
601
Table 5-8: Electrical Performance ......................................................................................................................................55
602
Table 6-1: DC Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP1 ...................................................................................61
603
Table 6-2: AC Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP1 ...................................................................................61
604
Table 6-3: Source Impedance Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP1..........................................................61
605
Table 6-4: HDMI Source Jitter Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP2_EQ...................................................62
606
Table 6-5: Functions defining horizontal and vertical dimensions for the eye diagram at TP2_EQ ..................................63
607
Table 6-6: Sink Operating DC Input Characteristics for devices supporting 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP2..................64
608
Table 6-7: Sink AC Input Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP2 ..................................................................64
609
Table 6-8: Sink Impedance Characteristics for 3.4 Gbps < Rbit ≤ 6.0 Gbps at TP2 ..............................................................64
610
Table 6-9: Summary of scrambling periods........................................................................................................................66
611
Table 6-10: First 32 LFSR Values for all Data Channels ......................................................................................................68
612
Table 6-11: Bit assignments for XOR logic operation for 8-bit data...................................................................................69
613
Table 6-12: Bit assignments for XOR logic operation for 4-bit data...................................................................................69
614
Table 6-13: 8-bit values that map to the TMDS Video Guard Band Codes ........................................................................69
615
Table 6-14: 8-bit values that map to the TMDS Data Island Guard Band Codes................................................................69
616
Table 6-15: IToggle Bit Generation Variables.....................................................................................................................71
617
Table 6-16: Bit assignments for XOR logic operation for 4-bit data...................................................................................72
618
Table 6-17: 10-bit codes for scrambled control periods....................................................................................................72
619
Table 6-18: CEC line Electrical Specifications for all Configurations ..................................................................................84
620
Table 6-19: FRL Lane link rates...........................................................................................................................................86
621
Table 6-20: DC Characteristics for 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1.............................................................88
622
Table 6-21: AC Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1 ................................................89
623
Table 6-22: Source Impedance Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1 (Informative) 89
624
Table 6-23: Parameters defining horizontal and vertical dimensions for the 16b18b eye diagram at TP2_EQ ................90
625
Table 6-24: TP2_EQ Source Jitter Requirement (unit is Tbit = 1/Rbit)..................................................................................90
626
Table 6-25: Sink operating DC Input Characteristics for Devices supporting 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12
627
Gbps at TP2 ........................................................................................................................................................................91
628
Table 6-26: Sink AC Input Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP2 ...............................91
629
Table 6-27: Sink Impedance Characteristics for 3 Gbps, 6.0 Gbps, 8 Gbps, 10 Gbps, 12 Gbps at TP2 (Informative).........91
630
Table 6-28: P2_EQ Sink Jitter Tolerance Requirement (unit is Tbit = 1/Rbit)........................................................................92
631
Table 6-29: Sinusoidal Jitter Frequency and Jitter Amplitude for Sink Jitter Tolerance Test.............................................92
632
Table 6-30: HF-VSDB registers for Sink Link Training Capability ........................................................................................93
633
Table 6-31: SCDC registers for Link Training ......................................................................................................................93
634
Table 6-32: Link Training Patterns in 16b18b mode ..........................................................................................................94
635
Table 6-33: First 11 LFSR values for 16b18b PRBS .............................................................................................................95
636
Table 6-34: Link Training States .........................................................................................................................................96
637
Table 6-35: FRL Map Character – FRL Packet Type ......................................................................................................... 100
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Table 6-36: Video Guard Band symbols and TMDS-decoded symbols for the TMDS Data Channels............................. 101
639
Table 6-37: Mapping Video Blanking Data (Control Period, Island Guard Bands, and Island Data) to FRL Characters .. 113
640
Table 6-38: Conditions for FRL Examples....................................................................................................................... 135
641
Table 6-39: Compute Parameters based on the Source Video ....................................................................................... 136
642
Table 6-40: Compute Bit Rate related Items................................................................................................................... 136
643
Table 6-41: Active Video Period Infrastructure............................................................................................................... 136
644
Table 6-42: Video Blank Period Infrastructure................................................................................................................ 137
645
Table 6-43: Pixel Format Computations.......................................................................................................................... 138
646
Table 6-44: Video Pixel Results ....................................................................................................................................... 138
647
Table 6-45: Audio Support Verification Computations................................................................................................... 139
648
Table 6-46: Additional Computations for Compressed Video......................................................................................... 139
649
Table 6-47: Encoding of FRL Packet Characters .............................................................................................................. 141
650
Table 6-48: FRL Special Characters.................................................................................................................................. 142
651
Table 6-49: First 16 LFSR Values for all Data Lanes with 16b18b Coding........................................................................ 143
652
Table 6-50: Bit assignments for XOR logic operation for 16-bit data.............................................................................. 144
653
Table 7-1: Video Timings that may be used with YCBCR 4:2:0 Pixel Encoding ................................................................. 145
654
Table 7-2: Mapping Two 8-bit per component 4:2:0 Pixels to one 24-bit 4:4:4 Pixel prior to Deep Color Packing........ 148
655
Table 7-3: Mapping Two 10-bit per component 4:2:0 Pixels to one 30-bit 4:4:4 Pixel prior to Deep Color Packing...... 148
656
Table 7-4: Mapping Two 12-bit per component 4:2:0 Pixels to one 36-bit 4:4:4 Pixel prior to Deep Color Packing...... 149
657
Table 7-5: Mapping Two 16-bit per component 4:2:0 Pixels to one 48-bit 4:4:4 Pixel prior to Deep Color Packing...... 149
658
Table 7-6: Video Formats defined in ITU-R BT.2020 that are supported by This Specification ...................................... 151
659
Table 7-7: Video Quantization signaling (values for Q1, Q0) for RGB encoding ............................................................. 152
660
Table 7-8: Video Quantization signaling (values for YQ1 and YQ0) for YCBCR Pixel Encoding......................................... 152
661
Table 7-9: 3D_Disparity_Data for 3D_DisparityData_version=001................................................................................. 153
662
Table 7-10: 3D_Disparity_Data for 3D_DisparityData_version=010............................................................................... 154
663
Table 7-11: Definition and values of multi_region_disparity_length and 3D_DisparityData_length ............................. 154
664
Table 7-12: Computing FVA_FACTORMAX......................................................................................................................... 158
665
Table 7-13: VRRFVA Extended Metadata Structure........................................................................................................ 160
666
Table 7-14: Nominal Recommended bpp Settings.......................................................................................................... 166
667
Table 7-15: Extended Recommended bpp Settings........................................................................................................ 167
668
Table 7-16: VESA DSC PPS Summary............................................................................................................................... 169
669
Table 7-17: VESA DSC rc parameter set summary .......................................................................................................... 170
670
Table 7-18: Example VESA DSC PPS Element “slice_width” computation results........................................................... 172
671
Table 7-19: Sample Results for 3 Lane applications........................................................................................................ 174
672
Table 7-20: Sample Results for 4 Lane applications........................................................................................................ 174
673
Table 7-21: Determining Max Supportable Audio Rate .................................................................................................. 175
674
Table 8-1: Packet Types................................................................................................................................................... 178
675
Table 8-2: 3D Audio Sample Packet Header.................................................................................................................... 179
676
Table 8-3: One Bit 3D Audio Packet Header.................................................................................................................... 180
677
Table 8-4: Audio Metadata Packet Header..................................................................................................................... 181
678
Table 8-5: Valid Bit Configurations for Audio Metadata Header .................................................................................... 183
679
Table 8-6: Audio Metadata Packet contents for 3D_AUDIO=1 ....................................................................................... 184
680
Table 8-7: 3D_CC field..................................................................................................................................................... 185
681
Table 8-8: Audio Channel Allocation Standard Type field............................................................................................... 185
682
Table 8-9: 3D_CA field for 10.2 Channels(1) (ACAT = 0x01)............................................................................................. 186
683
Table 8-10: 3D_CA field for 22.2 Channels(2)(ACAT = 0x02) (Part 1 of 2) ........................................................................ 186
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Table 8-11: 3D_CA field for 30.2 Channels(3) (ACAT = 0x03) (Part 1 of 3) ....................................................................... 187
685
Table 8-12: Audio Metadata Packet contents when 3D_Audio=0 and CTA_3D_AUDIO=0............................................. 189
686
Table 8-13: Audio Metadata Descriptor.......................................................................................................................... 189
687
Table 8-14: Supplementary Audio Type.......................................................................................................................... 191
688
Table 8-15: Multi-Stream Audio Sample Packet Header................................................................................................. 192
689
Table 8-16: One Bit Multi-Stream Audio Packet Header................................................................................................. 193
690
Table 8-17: Extended Metadata Packet Header ............................................................................................................. 195
691
Table 8-18: Extended Metadata Packet Contents for Sequence_Index=0, First=1......................................................... 196
692
Table 8-19: Extended Metadata Packet Contents when First is cleared (=0) ................................................................. 199
693
Table 9-1: Operand Description of [Audio Format ID and Code] .................................................................................... 200
694
Table 9-2: Allowed Values for Channel Status bits 24 to 27, 30, and 31......................................................................... 201
695
Table 9-3: Supported Sample Frequency or Frame Rate for each Packet Type .............................................................. 202
696
Table 9-4: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 32 kHz and
697
Multiples thereof ............................................................................................................................................................ 204
698
Table 9-5: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 44.1 kHz and
699
multiples thereof............................................................................................................................................................. 205
700
Table 9-6: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 48 kHz and
701
multiples thereof............................................................................................................................................................. 206
702
Table 9-7: Max 3D Audio Sampling Frequencies for 24-bit Video Format Timings (Informative) .................................. 208
703
Table 9-8: Max 3D Audio Sampling Frequencies for 24-bit 4:2:0 Video Format Timings (Informative) ......................... 209
704
Table 9-9: Channel Mapping for 12 Channel 3D Audio Sample Packet........................................................................... 210
705
Table 9-10: Channel Mapping for 24 Channel 3D Audio Sample Packet......................................................................... 210
706
Table 9-11: Channel Mapping for 32-Channel 3D Audio Sample Packet ........................................................................ 210
707
Table 9-12: Valid Sample_Present Bit Configurations for 3D Audio ............................................................................... 211
708
Table 9-13: Mapping for Multi-Stream Audio Sample Packet with 2 audio streams...................................................... 214
709
Table 9-14: mapping for Multi-Stream Audio Sample Packet with 3 audio streams...................................................... 214
710
Table 9-15: Mapping for Multi-Stream Audio Sample Packet with 4 audio streams...................................................... 214
711
Table 9-16: Valid Stream_Present Bit Configurations for Multi-Stream Audio transmission ......................................... 215
712
Table 9-17: eARC Naming Convention ............................................................................................................................ 218
713
A comparison of SPDIF, ARC, and eARC has been provided in Table 9-18.Table 9-18: eARC Audio Electrical Parameters
714
......................................................................................................................................................................................... 222
715
Table 9-19: Audio Packet Layout and Layout Value ........................................................................................................ 224
716
Table 9-20: Discovery and Disconnection Timing ........................................................................................................... 232
717
Table 9-21: eARC Common Mode Data Channel Timings............................................................................................... 235
718
Table 9-22: eARC Common Mode Data Channel Commands ......................................................................................... 236
719
Table 9-23: eARC Common Mode Data Channel Device IDs........................................................................................... 237
720
Table 9-24: Summary of Command or Data Packets for eARC Transaction Types.......................................................... 240
721
Table 9-25: eARC RX and Source Status Registers........................................................................................................... 241
722
Table 9-26: eARC Latency Registers................................................................................................................................ 243
723
Table 9-27: eARC Capabilities and Status Data Structure ............................................................................................... 247
724
Table 9-28: Capabilities and Status Block........................................................................................................................ 247
725
Table 9-29: BLOCK_ID Values.......................................................................................................................................... 247
726
Table 9-30: Type A Connector Pin Assignment................................................................................................................ 249
727
Table 9-31: Differential Mode Electrical Specifications .................................................................................................. 251
728
Table 9-32: Common Mode Data Channel Electrical Specifications ............................................................................... 251
729
Table 9-33: Cable Assembly Electrical Specifications (from H14b HEAC Table 2-17)...................................................... 252
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Table 10-1: List of features that require transmission of the HF-VSIF ............................................................................ 254
731
Table 10-2: H14b HDMI_VIC to CTA-861-G VIC Cross Reference.................................................................................... 254
732
Table 10-3: HDMI Forum Vendor Specific InfoFrame Packet Header............................................................................. 255
733
Table 10-4: HDMI Forum Vendor Specific InfoFrame Packet Contents .......................................................................... 255
734
Table 10-5: List of features that require inclusion of the HF-VSDB................................................................................. 260
735
Table 10-6: HDMI Forum Vendor Specific Data Block ..................................................................................................... 261
736
Table 10-7: HDMI Audio Data Block................................................................................................................................ 267
737
Table 10-8: Max_Stream_Count field ............................................................................................................................. 268
738
Table 10-9: HDMI 3D Audio Descriptor for Audio Format Code = 1 (L-PCM).................................................................. 268
739
Table 10-10: HDMI 3D Audio Descriptor for Audio Format Code 9 ................................................................................ 268
740
Table 10-11: HDMI 3D Speaker Allocation Descriptor for 10.2 channels (ITU-R BS.2159-4 (Type B 10.2ch)) ................ 268
741
Table 10-12: HDMI 3D Speaker Allocation Descriptor for 22.2 channels (SMPTE 2036-2)............................................. 268
742
Table 10-13: HDMI 3D Speaker Allocation Descriptor for 30.2 channels (IEC 62574 ed 1.0) ......................................... 269
743
Table 10-14: Audio Channel Allocation Type (ACAT) field .............................................................................................. 269
744
Table 10-15: Status and Control Data Channel Structure ............................................................................................... 271
745
Table 10-16: SCDCS - Sink Version, Read Only ................................................................................................................ 271
746
Table 10-17: SCDCS - Source Version, Read/Write ......................................................................................................... 272
747
Table 10-18: SCDCS - Update Flags ................................................................................................................................. 273
748
Table 10-19: SCDCS – TMDS Configuration..................................................................................................................... 275
749
Table 10-20: SCDCS - Status Flags ................................................................................................................................... 275
750
Table 10-21: SCDCS – Config_0 ....................................................................................................................................... 276
751
Table 10-22: SCDCS - Status Flags ................................................................................................................................... 280
752
Table 10-23: SCDCS - Character Error Detection............................................................................................................. 283
753
Table 10-24: SCDCS - Test Read Request, Read/Write.................................................................................................... 284
754
Table 10-25: SCDCS – ManufacturerSpecific................................................................................................................... 285
755
Table 10-26: Video Latency (VL) and Audio Latency (AL) in EDID of Device without HDMI output................................ 294
756
Table 10-27: Message Descriptions for the Dynamic Auto Lipsync feature.................................................................... 300
757
Table 10-28: Operand Descriptions for Dynamic LipSync ............................................................................................... 301
758
Table 10-29: [Need a Table Heading].............................................................................................................................. 306
759
Table 10-30: Mapping Data into the Compressed Video Transport EM Packets............................................................ 312
760
Table 10-31: Requirements for HID Data Structures....................................................................................................... 316
761
Table 10-32: Touch Profiles............................................................................................................................................. 316
762
Table 10-33: List of features that require support of Power Status Update Signaling ................................................... 317
763
Table 11-1: Behavior extensions..................................................................................................................................... 321
764
Table 11-2: Mandatory CEC features.............................................................................................................................. 323
765
Table 11-3: Optional CEC features .................................................................................................................................. 324
766
Table 11-4: When to set bits to 1 in [Device Features]................................................................................................... 324
767
Table 11-5: When to set ARC bits to 1 in [Device Features]............................................................................................ 325
768
Table 11-6: Other CEC features....................................................................................................................................... 325
769
Table 11-7: Device Types................................................................................................................................................. 327
770
Table 11-8: Combinations of Device Types that may try to allocate multiple Logical Addresses................................... 328
771
Table 11-9: Logical Addresses (extended from H14b CEC Table 5)................................................................................. 330
772
Table 11-10: Power States .............................................................................................................................................. 335
773
Table 11-11: Power State Transitions ............................................................................................................................. 336
774
Table 11-12: CEC Electrical Specifications during the fully powered-Off state............................................................... 348
775
Table 11-13: Message Descriptions for the Routing Control Feature ............................................................................. 358
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Table 11-14: Message Descriptions for the Standby Feature ......................................................................................... 359
777
Table 11-15: Message Descriptions for the One Touch Record Feature......................................................................... 360
778
Table 11-16: Message Descriptions for the System Information Feature....................................................................... 361
779
Table 11-17: Message Descriptions for the Deck Control Feature.................................................................................. 363
780
Table 11-18: Message Descriptions for the Vendor Specific Commands Feature .......................................................... 365
781
Table 11-19: Message Descriptions for the OSD Display Feature ................................................................................... 366
782
Table 11-20: Message Descriptions for the Device OSD Name Transfer Feature ........................................................... 366
783
Table 11-21: Message Descriptions for the Remote Control Pass Through Feature ...................................................... 367
784
Table 11-22: Message Descriptions for the Power Status Feature ................................................................................. 368
785
Table 11-23: Message Descriptions for General Protocol messages .............................................................................. 369
786
Table 11-24: Message Descriptions for the System Audio Control Feature ................................................................... 370
787
Table 11-25: Message Descriptions for the Audio Rate Control Feature........................................................................ 373
788
Table 11-26: Message Descriptions for the Audio Return Channel Control Feature ...................................................... 374
789
Table 11-27: Message Descriptions for the Dynamic Auto Lipsync feature.................................................................... 375
790
Table 11-28: Message dependencies when receiving a message ................................................................................... 376
791
Table 11-29: Message dependencies when sending a message ..................................................................................... 376
792
Table 11-30: Operand Descriptions................................................................................................................................. 378
793
Table 11-31: UI Command Codes.................................................................................................................................... 382
794
Table 12-1: Valid Power Use Cases ................................................................................................................................. 391
795
Table 12-2: PSource Power Delivery Limits..................................................................................................................... 392
796
Table 12-3: Source AdDDC DC Characteristics at TP1 ..................................................................................................... 449
797
Table 12-4: Source AdDDC AC Characteristics at TP1 ..................................................................................................... 449
798
Table 12-5: AdDDC Source Impedance at TP1 ................................................................................................................ 449
799
Table 12-6: AdDDC Source Jitter at TP1 .......................................................................................................................... 450
800
Table 12-7: Amplitude Transfer Function Parameters for AdDDC Reference Cable Equalizer ....................................... 452
801
Table 12-8: Sink AdDDC DC Characteristics at TP2.......................................................................................................... 452
802
Table 12-9: Sink AdDDC AC Characteristics at TP2.......................................................................................................... 452
803
Table 12-10: AdDDC Sink Impedance at TP2................................................................................................................... 453
804
Table 12-11: AdDDC Sink Jitter at TP2............................................................................................................................. 453
805
Table 12-12: Cable Assembly Parameters for DDC/AdDDC pair for Category ................................................................ 455
806
Table 12-13: Category 3 Cable DDC Attenuation Limit Endpoints – Informative............................................................ 455
807
Table 12-14: AdDDC Timings........................................................................................................................................... 458
808
Table 12-15: TDM Synchronization Characters............................................................................................................... 459
809
Table 12-16: TDM Timing Requirements ........................................................................................................................ 461
810
Table 12-17: Slot 0 Control Characters ........................................................................................................................... 462
811
Table 12-18: Slot 0 Transport Forward Sequence........................................................................................................... 462
812
Table 12-19: Slot 0 Transport Timing requirements ....................................................................................................... 464
813
Table 12-20: DDC Tunneling Control Codes.................................................................................................................... 464
814
Table 12-21: DDC Tunneling Timing requirements......................................................................................................... 467
815
Table 12-22: Transport Container Sub-layer Commands................................................................................................ 468
816
Table 12-23: Transport Container Structure ................................................................................................................... 468
817
Table 12-24: Transport Container Structure without Payload........................................................................................ 470
818
Table 12-25: Transport Container Sub-layer Parameters ............................................................................................... 473
819
Table 12-26: Message Fragment Structure ..................................................................................................................... 473
820
Table 12-27: Fragment Message with PR_CREDIT Only .................................................................................................. 475
821
Table 12-28: Flow Control Error Indication..................................................................................................................... 475
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823
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Table of Equations
825
Equation 6-1: Jitter Transfer Function of Ideal CRU for Ideal Recovery Clock Definition Defined in H14b Equation 4-1..59
826
Equation 6-2: Reference Equalizer Equations for 3.4 Gbps < Rbit ≤ 6.0 Gbps.....................................................................60
827
Equation 6-3: LFSR Generator Polynomial .........................................................................................................................67
828
Equation 6-4: Jitter Transfer Function of Ideal CRU for Ideal Recovery Clock for 3.0, 6.0 Gbps, 8 Gbps, 10 Gbps, 12.0
829
Gbps ...................................................................................................................................................................................86
830
Equation 6-5: Reference CTLE Equalizer Equations for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps............................87
831
Equation 6-6: Determination of the number of bytes in a Line of Chunks ..................................................................... 104
832
Equation 6-7: Determination of the number of Hactive tri-bytes in a Line of Chunks.................................................... 104
833
Equation 7-1: Calculating Vfront when FVA is active and VRR is not active ................................................................... 157
834
Equation 7-2: Calculating Vtotal when FVA is active and VRR is not active .................................................................... 157
835
Equation 7-3: Calculating Vfront when FVA is not active and VRR is active ................................................................... 157
836
Equation 7-4: Calculating Vtotal when FVA is not active and VRR is active.................................................................... 157
837
Equation 7-5: Calculating Vfront when both FVA and VRR are active ............................................................................ 157
838
Equation 7-6: Calculating Vtotal when both FVA and VRR are active............................................................................. 157
839
Equation 7-7: Computing 𝒇𝑷𝒊𝒙𝒆𝒍, 𝑭𝑽𝑨 when FVA is active........................................................................................... 159
840
Equation 7-8: Maxiumum number of lines transmitted per frame when VRR is active ................................................. 159
841
Equation 7-9: Maximum number of lines that can be added per frame when VRR and FVA are enabled..................... 160
842
Equation 7-10: Maximum number of lines that can be added per frame when VRR is enabled and FVA is not enabled
843
......................................................................................................................................................................................... 160
844
Equation 7-11: Requirements for MVRR when VRR is enabled......................................................................................... 160
845
Equation 7-12: Determination of HCActive based on HSlicesper_line, the SliceWidth, and the bpp setting ......................... 164
846
Equation 7-13: Permissible Compressed Video Transport bpp Settings......................................................................... 164
847
Equation 12-1: Amplitude Transfer function of the AdDDC Reference Cable Equalizer................................................. 451
848
Equation 12-2: Slot 0 Transport CRC polynomial ............................................................................................................ 463
849
Equation 12-3: Equation 3 3 Transport Container CRC polynomial ................................................................................ 469
850
851
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