PCIE Base Specification Revision 4.0 Version 1.0

【实例简介】PCIE Base Specification Revision 4.0 Version 1.0

PCIE Base Specification Revision 4.0 Version 1.0, 包含了完成的SR-IOV spec章节 Single Root IO Virtualization and Sharing Specification Revision 1.1

【实例截图】

【核心代码】

Contents
OBJECTIVE OF THE SPECIFICATION ............................................................................... 42
DOCUMENT ORGANIZATION.............................................................................................. 42
DOCUMENTATION CONVENTIONS ................................................................................... 42
TERMS AND ACRONYMS ...................................................................................................... 43
REFERENCE DOCUMENTS ................................................................................................... 53
1 INTRODUCTION............................................................................................................... 54
1.1 A T HIRD G ENERATION I/O I NTERCONNECT ................................................................... 54
1.2 PCI E XPRESS L INK ......................................................................................................... 56
1.3 PCI E XPRESS F ABRIC T OPOLOGY .................................................................................. 57
1.3.1 Root Complex ............................................................................................................ 57
1.3.2 Endpoints .................................................................................................................. 58
1.3.3 Switch ........................................................................................................................ 60
1.3.4 Root Complex Event Collector .................................................................................. 61
1.3.5 PCI Express to PCI/PCI-X Bridge ............................................................................ 62
1.4 H ARDWARE /S OFTWARE M ODEL FOR D ISCOVERY , C ONFIGURATION AND O PERATION .. 62
1.5 PCI E XPRESS L AYERING O VERVIEW .............................................................................. 63
1.5.1 Transaction Layer ..................................................................................................... 64
1.5.2 Data Link Layer ........................................................................................................ 64
1.5.3 Physical Layer .......................................................................................................... 65
1.5.4 Layer Functions and Services ................................................................................... 65
2 TRANSACTION LAYER SPECIFICATION ................................................................. 69
2.1 T RANSACTION L AYER O VERVIEW .................................................................................. 69
2.1.1 Address Spaces, Transaction Types, and Usage ....................................................... 70
2.1.2 Packet Format Overview .......................................................................................... 72
2.2 T RANSACTION L AYER P ROTOCOL - P ACKET D EFINITION ............................................... 74
2.2.1 Common Packet Header Fields ................................................................................ 74
2.2.2 TLPs with Data Payloads - Rules ............................................................................. 77
2.2.3 TLP Digest Rules ...................................................................................................... 81
2.2.4 Routing and Addressing Rules .................................................................................. 81
2.2.5 First/Last DW Byte Enables Rules ............................................................................ 84
2.2.6 Transaction Descriptor ............................................................................................. 87
2.2.7 Memory, I/O, and Configuration Request Rules ....................................................... 97
2.2.8 Message Request Rules ........................................................................................... 104
2.2.9 Completion Rules .................................................................................................... 125
2.2.10 TLP Prefix Rules ................................................................................................. 128
2.3 H ANDLING OF R ECEIVED TLP S .................................................................................... 132
2.3.1 Request Handling Rules .......................................................................................... 135
2.3.2 Completion Handling Rules .................................................................................... 147
2.4 T RANSACTION O RDERING ............................................................................................ 150
2.4.1 Transaction Ordering Rules ................................................................................... 150
PCI Express Base Specification, Rev. 4.0 Version 1.0
9
2.4.2 Update Ordering and Granularity Observed by a Read Transaction .................... 154
2.4.3 Update Ordering and Granularity Provided by a Write Transaction .................... 155
2.5 V IRTUAL C HANNEL (VC) M ECHANISM ........................................................................ 155
2.5.1 Virtual Channel Identification (VC ID) .................................................................. 157
2.5.2 TC to VC Mapping .................................................................................................. 158
2.5.3 VC and TC Rules ..................................................................................................... 159
2.6 O RDERING AND R ECEIVE B UFFER F LOW C ONTROL ..................................................... 160
2.6.1 Flow Control Rules ................................................................................................. 161
2.7 D ATA I NTEGRITY ......................................................................................................... 173
2.7.1 ECRC Rules ............................................................................................................ 174
2.7.2 Error Forwarding ................................................................................................... 178
2.8 C OMPLETION T IMEOUT M ECHANISM ........................................................................... 180
2.9 L INK S TATUS D EPENDENCIES ...................................................................................... 181
2.9.1 Transaction Layer Behavior in DL_Down Status ................................................... 181
2.9.2 Transaction Layer Behavior in DL_Up Status ....................................................... 182
2.9.3 Transaction Layer Behavior During Downstream Port Containment ................... 183
3 DATA LINK LAYER SPECIFICATION ...................................................................... 185
3.1 D ATA L INK L AYER O VERVIEW .................................................................................... 185
3.2 D ATA L INK C ONTROL AND M ANAGEMENT S TATE M ACHINE ...................................... 187
3.2.1 Data Link Control and Management State Machine Rules .................................... 188
3.3 D ATA L INK F EATURE E XCHANGE ................................................................................ 191
3.4 F LOW C ONTROL I NITIALIZATION P ROTOCOL ............................................................... 193
3.4.1 Flow Control Initialization State Machine Rules ................................................... 193
3.4.2 Scaled Flow Control ............................................................................................... 197
3.5 D ATA L INK L AYER P ACKETS (DLLP S ) ........................................................................ 198
3.5.1 Data Link Layer Packet Rules ................................................................................ 198
3.6 D ATA I NTEGRITY ......................................................................................................... 204
3.6.1 Introduction............................................................................................................. 204
3.6.2 LCRC, Sequence Number, and Retry Management (TLP Transmitter).................. 205
3.6.3 LCRC and Sequence Number (TLP Receiver) ........................................................ 217
4 PHYSICAL LAYER LOGICAL BLOCK...................................................................... 225
4.1 I NTRODUCTION ............................................................................................................ 225
4.2 L OGICAL S UB - BLOCK ................................................................................................... 225
4.2.1 Encoding for 2.5 GT/s and 5.0 GT/s Data Rates .................................................... 226
4.2.2 Encoding for 8.0 GT/s and Higher Data Rates....................................................... 234
4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates ....................... 253
4.2.4 Link Initialization and Training .............................................................................. 263
4.2.5 Link Training and Status State Machine (LTSSM) Descriptions ............................ 283
4.2.6 Link Training and Status State Rules ...................................................................... 287
4.2.7 Clock Tolerance Compensation .............................................................................. 360
4.2.8 Compliance Pattern in 8b/10b Encoding ................................................................ 368
4.2.9 Modified Compliance Pattern in 8b/10b Encoding ................................................ 370
4.2.10 Compliance Pattern in 128b/130b Encoding ...................................................... 371
4.2.11 Modified Compliance Pattern in 128b/130b Encoding ...................................... 373
4.2.12 Jitter Measurement Pattern in 128b/130b .......................................................... 374
PCI Express Base Specification, Rev. 4.0 Version 1.0
10
4.2.13 Lane Margining at Receiver ............................................................................... 374
4.3 R ETIMERS .................................................................................................................... 388
4.3.1 Retimer Requirements ............................................................................................. 388
4.3.2 Supported Topologies ............................................................................................. 389
4.3.3 Variables ................................................................................................................. 391
4.3.4 Receiver Impedance Propagation Rules ................................................................. 391
4.3.5 Switching Between Modes....................................................................................... 391
4.3.6 Forwarding Rules ................................................................................................... 392
4.3.7 Execution Mode Rules ............................................................................................. 409
4.3.8 Retimer Latency ...................................................................................................... 416
4.3.9 SRIS ......................................................................................................................... 416
4.3.10 L1 PM Substates Support .................................................................................... 418
4.3.11 Retimer Configuration Parameters ..................................................................... 421
4.3.12 In Band Register Access...................................................................................... 423
5 POWER MANAGEMENT .............................................................................................. 424
5.1 O VERVIEW ................................................................................................................... 424
5.2 L INK S TATE P OWER M ANAGEMENT ............................................................................. 425
5.3 PCI-PM S OFTWARE C OMPATIBLE M ECHANISMS ......................................................... 431
5.3.1 Device Power Management States (D-States) of a Function .................................. 431
5.3.2 PM Software Control of the Link Power Management State .................................. 436
5.3.3 Power Management Event Mechanisms ................................................................. 441
5.4 N ATIVE PCI E XPRESS P OWER M ANAGEMENT M ECHANISMS ....................................... 448
5.4.1 Active State Power Management (ASPM) .............................................................. 448
5.5 L1 PM S UBSTATES ...................................................................................................... 467
5.5.1 Entry conditions for L1 PM Substates and L1.0 Requirements .............................. 471
5.5.2 L1.1 Requirements .................................................................................................. 472
5.5.3 L1.2 Requirements .................................................................................................. 474
5.5.4 L1 PM Substates Configuration .............................................................................. 477
5.5.5 L1 PM Substates Timing Parameters ..................................................................... 478
5.6 A UXILIARY P OWER S UPPORT ....................................................................................... 479
5.7 P OWER M ANAGEMENT S YSTEM M ESSAGES AND DLLP S ............................................. 479
5.8 PCI F UNCTION P OWER S TATE T RANSITIONS ................................................................ 480
5.9 F UNCTION P OWER M ANAGEMENT P OLICIES ................................................................ 481
5.9.1 State Transition Recovery Time Requirements ....................................................... 485
5.10 PCI B RIDGES AND P OWER M ANAGEMENT ................................................................... 486
5.10.1 Switches and PCI Express to PCI Bridges ......................................................... 487
5.11 P OWER M ANAGEMENT E VENTS ................................................................................... 487
6 SYSTEM ARCHITECTURE .......................................................................................... 489
6.1 I NTERRUPT AND PME S UPPORT ................................................................................... 489
6.1.1 Rationale for PCI Express Interrupt Model............................................................ 489
6.1.2 PCI-compatible INTx Emulation ............................................................................ 490
6.1.3 INTx Emulation Software Model ............................................................................ 490
6.1.4 MSI and MSI-X Operation ...................................................................................... 490
6.1.5 PME Support ........................................................................................................... 498
6.1.6 Native PME Software Model .................................................................................. 499
PCI Express Base Specification, Rev. 4.0 Version 1.0
11
6.1.7 Legacy PME Software Model ................................................................................. 499
6.1.8 Operating System Power Management Notification ............................................... 500
6.1.9 PME Routing Between PCI Express and PCI Hierarchies .................................... 500
6.2 E RROR S IGNALING AND L OGGING ................................................................................ 500
6.2.1 Scope ....................................................................................................................... 501
6.2.2 Error Classification ................................................................................................ 501
6.2.3 Error Signaling ....................................................................................................... 503
6.2.4 Error Logging ......................................................................................................... 511
6.2.5 Sequence of Device Error Signaling and Logging Operations .............................. 518
6.2.6 Error Message Controls ......................................................................................... 519
6.2.7 Error Listing and Rules .......................................................................................... 519
6.2.8 Virtual PCI Bridge Error Handling ........................................................................ 524
6.2.9 Internal Errors ........................................................................................................ 526
6.2.10 Downstream Port Containment (DPC) ............................................................... 526
6.3 V IRTUAL C HANNEL S UPPORT ...................................................................................... 536
6.3.1 Introduction and Scope ........................................................................................... 536
6.3.2 TC/VC Mapping and Example Usage ..................................................................... 537
6.3.3 VC Arbitration ........................................................................................................ 539
6.3.4 Isochronous Support ............................................................................................... 547
6.4 D EVICE S YNCHRONIZATION ......................................................................................... 550
6.5 L OCKED T RANSACTIONS .............................................................................................. 551
6.5.1 Introduction............................................................................................................. 551
6.5.2 Initiation and Propagation of Locked Transactions - Rules ................................... 552
6.5.3 Switches and Lock - Rules....................................................................................... 553
6.5.4 PCI Express/PCI Bridges and Lock - Rules ........................................................... 553
6.5.5 Root Complex and Lock - Rules .............................................................................. 554
6.5.6 Legacy Endpoints .................................................................................................... 554
6.5.7 PCI Express Endpoints ........................................................................................... 554
6.6 PCI E XPRESS R ESET - R ULES ....................................................................................... 554
6.6.1 Conventional Reset ................................................................................................. 554
6.6.2 Function Level Reset (FLR) .................................................................................... 557
6.7 PCI E XPRESS H OT -P LUG S UPPORT .............................................................................. 561
6.7.1 Elements of Hot-Plug .............................................................................................. 561
6.7.2 Registers Grouped by Hot-Plug Element Association ............................................ 568
6.7.3 PCI Express Hot-Plug Events ................................................................................. 570
6.7.4 Firmware Support for Hot-Plug ............................................................................. 573
6.7.5 Async Removal ........................................................................................................ 573
6.8 P OWER B UDGETING C APABILITY ................................................................................. 574
6.8.1 System Power Budgeting Process Recommendations ............................................. 574
6.9 S LOT P OWER L IMIT C ONTROL ..................................................................................... 575
6.10 R OOT C OMPLEX T OPOLOGY D ISCOVERY ..................................................................... 578
6.11 L INK S PEED M ANAGEMENT ......................................................................................... 580
6.12 A CCESS C ONTROL S ERVICES (ACS) ............................................................................ 581
6.12.1 ACS Component Capability Requirements ......................................................... 582
6.12.2 Interoperability ................................................................................................... 587
6.12.3 ACS Peer-to-Peer Control Interactions .............................................................. 587
PCI Express Base Specification, Rev. 4.0 Version 1.0
12
6.12.4 ACS Violation Error Handling ........................................................................... 588
6.12.5 ACS Redirection Impacts on Ordering Rules ..................................................... 589
6.13 A LTERNATIVE R OUTING -ID I NTERPRETATION (ARI) .................................................. 591
6.14 M ULTICAST O PERATIONS ............................................................................................. 595
6.14.1 Multicast TLP Processing ................................................................................... 595
6.14.2 Multicast Ordering.............................................................................................. 599
6.14.3 Multicast Capability Structure Field Updates .................................................... 599
6.14.4 MC Blocked TLP Processing .............................................................................. 600
6.14.5 MC_Overlay Mechanism .................................................................................... 600
6.15 A TOMIC O PERATIONS (A TOMIC O PS ) ........................................................................... 603
6.15.1 AtomicOp Use Models and Benefits ................................................................... 605
6.15.2 AtomicOp Transaction Protocol Summary ......................................................... 605
6.15.3 Root Complex Support for AtomicOps ................................................................ 607
6.15.4 Switch Support for AtomicOps ............................................................................ 608
6.16 D YNAMIC P OWER A LLOCATION (DPA) C APABILITY ................................................... 608
6.16.1 DPA Capability with Multi-Function Devices .................................................... 610
6.17 TLP P ROCESSING H INTS (TPH) ................................................................................... 610
6.17.1 Processing Hints ................................................................................................. 610
6.17.2 Steering Tags ...................................................................................................... 611
6.17.3 ST Modes of Operation ....................................................................................... 612
6.17.4 TPH Capability ................................................................................................... 613
6.18 L ATENCY T OLERANCE R EPORTING (LTR) M ECHANISM .............................................. 613
6.19 O PTIMIZED B UFFER F LUSH /F ILL (OBFF) M ECHANISM ................................................ 620
6.20 PASID TLP P REFIX ..................................................................................................... 624
6.20.1 Managing PASID TLP Prefix Usage .................................................................. 624
6.20.2 PASID TLP Layout ............................................................................................. 625
6.21 L IGHTWEIGHT N OTIFICATION (LN) P ROTOCOL ............................................................ 628
6.21.1 LN Protocol Operation ....................................................................................... 630
6.21.2 LN Registration Management ............................................................................. 631
6.21.3 LN Ordering Considerations .............................................................................. 632
6.21.4 LN Software Configuration ................................................................................. 632
6.21.5 LN Protocol Summary ......................................................................................... 633
6.22 P RECISION T IME M EASUREMENT (PTM) M ECHANISM ................................................ 634
6.22.1 Introduction......................................................................................................... 634
6.22.2 PTM Link Protocol ............................................................................................. 636
6.22.3 Configuration and Operational Requirements ................................................... 638
6.23 R EADINESS N OTIFICATIONS (RN) ................................................................................ 644
6.23.1 Device Readiness Status (DRS) .......................................................................... 644
6.23.2 Function Readiness Status (FRS) ........................................................................ 645
6.23.3 FRS Queuing ....................................................................................................... 646
6.24 E NHANCED A LLOCATION ............................................................................................. 647
6.25 E MERGENCY P OWER R EDUCTION S TATE ..................................................................... 649
6.26 H IERARCHY ID M ESSAGE ............................................................................................ 651
6.27 F LATTENING P ORTAL B RIDGE (FPB) ........................................................................... 655
6.27.1 Introduction......................................................................................................... 655
6.27.2 Hardware and Software Requirements ............................................................... 659
PCI Express Base Specification, Rev. 4.0 Version 1.0
13
6.28 V ITAL P RODUCT D ATA (VPD) ..................................................................................... 666
6.29 N ATIVE PCI E E NCLOSURE M ANAGEMENT ................................................................... 671
7 SOFTWARE INITIALIZATION AND CONFIGURATION ...................................... 675
7.1 C ONFIGURATION T OPOLOGY ........................................................................................ 675
7.2 PCI E XPRESS C ONFIGURATION M ECHANISMS ............................................................. 676
7.2.1 PCI-compatible Configuration Mechanism ............................................................ 677
7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM) ...................... 677
7.2.3 Root Complex Register Block ................................................................................. 682
7.3 C ONFIGURATION T RANSACTION R ULES ....................................................................... 682
7.3.1 Device Number........................................................................................................ 682
7.3.2 Configuration Transaction Addressing................................................................... 683
7.3.3 Configuration Request Routing Rules ..................................................................... 683
7.3.4 PCI Special Cycles .................................................................................................. 685
7.4 C ONFIGURATION R EGISTER T YPES .............................................................................. 685
7.5 PCI AND PCI E C APABILITIES R EQUIRED BY THE B ASE S PEC FOR ALL P ORTS .............. 687
7.5.1 PCI-Compatible Configuration Registers ............................................................... 687
7.5.2 PCI Power Management Capability Structure ....................................................... 717
7.5.3 PCI Express Capability Structure ........................................................................... 724
7.6 PCI E XPRESS E XTENDED C APABILITIES ....................................................................... 796
7.6.1 Extended Capabilities in Configuration Space ....................................................... 796
7.6.2 Extended Capabilities in the Root Complex Register Block ................................... 796
7.6.3 PCI Express Extended Capability Header .............................................................. 797
7.7 PCI AND PCI E C APABILITIES R EQUIRED BY THE B ASE S PEC IN S OME S ITUATIONS ..... 798
7.7.1 MSI Capability Structures....................................................................................... 798
7.7.2 MSI-X Capability and Table Structure ................................................................... 806
7.7.3 Secondary PCI Express Extended Capability ......................................................... 815
7.7.4 Data Link Feature Extended Capability ................................................................. 821
7.7.5 Physical Layer 16.0 GT/s Extended Capability ...................................................... 824
7.7.6 Lane Margining at the Receiver Extended Capability ............................................ 832
7.7.7 ACS Extended Capability ........................................................................................ 836
7.8 C OMMON PCI AND PCI E C APABILITIES ....................................................................... 842
7.8.1 Power Budgeting Capability ................................................................................... 842
7.8.2 Latency Tolerance Reporting (LTR) Capability ..................................................... 847
7.8.3 L1 PM Substates Extended Capability .................................................................... 850
7.8.4 Advanced Error Reporting Capability .................................................................... 856
7.8.5 Enhanced Allocation (EA) Capability Structure ..................................................... 874
7.8.6 Resizable BAR Capability ....................................................................................... 881
7.8.7 ARI Capability ........................................................................................................ 887
7.8.8 PASID Extended Capability Structure .................................................................... 889
7.8.9 Function Readiness Status (FRS) Queuing Extended Capability ........................... 892
7.8.10 Flattening Portal Bridge (FPB) Capability ........................................................ 897
7.9 A DDITIONAL PCI AND PCI E C APABILITIES .................................................................. 908
7.9.1 Virtual Channel Capability ..................................................................................... 908
7.9.2 Multi-Function Virtual Channel Capability ........................................................... 923
7.9.3 Device Serial Number Capability ........................................................................... 935
7.9.4 Vendor-Specific Capability ..................................................................................... 937
PCI Express Base Specification, Rev. 4.0 Version 1.0
14
7.9.5 Vendor-Specific Extended Capability ..................................................................... 938
7.9.6 Designated Vendor-Specific Extended Capability (DVSEC) .................................. 941
7.9.7 RCRB Header Capability ........................................................................................ 943
7.9.8 PCI Express Root Complex Link Declaration Capability ...................................... 946
7.9.9 PCI Express Root Complex Internal Link Control Capability ............................... 952
7.9.10 PCI Express Root Complex Event Collector Endpoint Association Capability . 960
7.9.11 Multicast Capability............................................................................................ 962
7.9.12 Dynamic Power Allocation (DPA) Capability .................................................... 968
7.9.13 TPH Requester Capability .................................................................................. 972
7.9.14 LNR Extended Capability ................................................................................... 976
7.9.15 DPC Extended Capability ................................................................................... 978
7.9.16 Precision Time Management (PTM) Capability ................................................. 992
7.9.17 Readiness Time Reporting Extended Capability ................................................. 995
7.9.18 Hierarchy ID Extended Capability ..................................................................... 999
7.9.19 VPD Capability ................................................................................................. 1008
7.9.20 Native PCIe Enclosure Management Extended Capability .............................. 1010
8 ELECTRICAL SUB-BLOCK........................................................................................ 1016
8.1 E LECTRICAL S PECIFICATION I NTRODUCTION ............................................................. 1016
8.2 I NTEROPERABILITY C RITERIA .................................................................................... 1016
8.2.1 Data Rates ............................................................................................................. 1016
8.2.2 Refclk Architectures .............................................................................................. 1016
8.3 T RANSMITTER S PECIFICATION ................................................................................... 1017
8.3.1 Measurement Setup for Characterizing Transmitters ........................................... 1017
8.3.2 Voltage Level Definitions ...................................................................................... 1018
8.3.3 Tx Voltage Parameters ......................................................................................... 1019
8.3.4 Transmitter Margining ......................................................................................... 1029
8.3.5 Tx Jitter Parameters ............................................................................................. 1030
8.3.6 Data Rate Dependent Parameters ........................................................................ 1037
8.3.7 Tx and Rx Return Loss .......................................................................................... 1040
8.3.8 Transmitter PLL Bandwidth and Peaking ............................................................ 1041
8.3.9 Data Rate Independent Tx Parameters ................................................................. 1042
8.4 R ECEIVER S PECIFICATIONS ........................................................................................ 1043
8.4.1 Receiver Stressed Eye Specification ..................................................................... 1043
8.4.2 Stressed Eye Test ................................................................................................... 1053
8.4.3 Common Receiver Parameters ............................................................................. 1061
8.4.4 Lane Margining at the Receiver – Electrical Requirements ................................. 1064
8.4.5 Low Frequency and Miscellaneous Signaling Requirements ............................... 1067
8.5 C HANNEL T OLERANCING ........................................................................................... 1070
8.5.1 Channel Compliance Testing ................................................................................ 1070
8.6 R EFCLK S PECIFICATIONS ........................................................................................... 1079
8.6.1 Refclk Test Setup ................................................................................................... 1079
8.6.2 REFCLK AC Specifications .................................................................................. 1080
8.6.3 Data Rate Independent Refclk Parameters ........................................................... 1083
8.6.4 Refclk Architectures Supported ............................................................................. 1084
8.6.5 Filtering Functions Applied to Raw Data ............................................................. 1084
8.6.6 Common Refclk Rx Architecture (CC) .................................................................. 1085
PCI Express Base Specification, Rev. 4.0 Version 1.0
15
8.6.7 Jitter Limits for Refclk Architectures .................................................................... 1088
8.6.8 Form Factor Requirements for RefClock Architectures ....................................... 1088
9 SINGLE ROOT I/O VIRTUALIZATION AND SHARING ...................................... 1090
9.1 A RCHITECTURAL O VERVIEW ..................................................................................... 1090
9.1.1 PCI Technologies Interoperability ....................................................................... 1102
9.2 I NITIALIZATION AND R ESOURCE A LLOCATION .......................................................... 1103
9.2.1 SR-IOV Resource Discovery ................................................................................. 1103
9.2.2 Reset Mechanisms ................................................................................................. 1107
9.2.3 IOV Re-initialization and Reallocation ................................................................ 1108
9.2.4 VF Migration ........................................................................................................ 1108
9.3 C ONFIGURATION ........................................................................................................ 1112
9.3.1 Overview ............................................................................................................... 1112
9.3.2 Configuration Space ............................................................................................. 1112
9.3.3 SR-IOV Extended Capability ................................................................................ 1112
9.3.4 PF/VF Configuration Space Header .................................................................... 1130
9.3.5 PCI Express Capability ......................................................................................... 1134
9.3.6 PCI Standard Capabilities .................................................................................... 1140
9.3.7 PCI Express Extended Capabilities ...................................................................... 1141
9.4 A LL VF S ASSOCIATED WITH THE SAME PF SHALL REPORT THE SAME TIME
VALUES .E RROR H ANDLING .................................................................................................... 1152
9.4.1 Baseline Error Reporting ...................................................................................... 1152
9.4.2 Advanced Error Reporting .................................................................................... 1153
9.5 I NTERRUPTS ............................................................................................................... 1158
9.5.1 Interrupt Mechanisms ........................................................................................... 1158
9.6 P OWER M ANAGEMENT ............................................................................................... 1159
9.6.1 VF Device Power Management States .................................................................. 1160
9.6.2 PF Device Power Management States .................................................................. 1161
9.6.3 Link Power Management State ............................................................................. 1161
9.6.4 VF Power Management Capability ...................................................................... 1161
9.6.5 VF EmergencyPower Reduction State .................................................................. 1162
10 ATS SPECIFICATION .................................................................................................. 1163
10.1 A RCHITECTURAL O VERVIEW ..................................................................................... 1163
10.1.1 Address Translation Services (ATS) Overview ................................................. 1165
10.1.2 Page Request Interface Extension .................................................................... 1170
10.1.3 Process Address Space ID (PASID) ................................................................. 1172
10.2 ATS T RANSLATION S ERVICES ................................................................................... 1173
10.2.1 Memory Requests with Address Type ............................................................... 1173
10.2.2 Translation Requests ......................................................................................... 1174
10.2.3 Translation Completion .................................................................................... 1177
10.2.4 Completions with Multiple Translations ........................................................... 1185
10.3 ATS I NVALIDATION ................................................................................................... 1187
10.3.1 Invalidate Request ............................................................................................. 1187
10.3.2 Invalidate Completion ....................................................................................... 1188
10.3.3 Invalidate Completion Semantics ..................................................................... 1190
10.3.4 Request Acceptance Rules................................................................................. 1191
PCI Express Base Specification, Rev. 4.0 Version 1.0
16
10.3.5 Invalidate Flow Control .................................................................................... 1191
10.3.6 Invalidate Ordering Semantics ......................................................................... 1192
10.3.7 Implicit Invalidation Events .............................................................................. 1193
10.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1194
10.4 P AGE R EQUEST S ERVICES .......................................................................................... 1195
10.4.1 Page Request Message ...................................................................................... 1196
10.4.2 Page Request Group Response Message .......................................................... 1200
10.5 C ONFIGURATION ........................................................................................................ 1202
10.5.1 ATS Extended Capability Structure .................................................................. 1202
10.5.2 Page Request Extended Capability Structure ................................................... 1205
A. ISOCHRONOUS APPLICATIONS ................................................................................. 1212
A.1. I NTRODUCTION .......................................................................................................... 1212
A.2. I SOCHRONOUS C ONTRACT AND C ONTRACT P ARAMETERS ......................................... 1214
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1215
A.2.2. Isochronous Payload Size ................................................................................. 1216
A.2.3. Isochronous Bandwidth Allocation ................................................................... 1216
A.2.4. Isochronous Transaction Latency ..................................................................... 1217
A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1218
A.3. I SOCHRONOUS T RANSACTION R ULES ......................................................................... 1219
A.4. T RANSACTION O RDERING .......................................................................................... 1219
A.5. I SOCHRONOUS D ATA C OHERENCY ............................................................................. 1219
A.6. F LOW C ONTROL ......................................................................................................... 1220
A.7. C ONSIDERATIONS FOR B ANDWIDTH A LLOCATION ..................................................... 1220
A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1220
A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1220
A.7.3. Isochronous Bandwidth of Switches ................................................................. 1220
A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1221
A.8. C ONSIDERATIONS FOR PCI E XPRESS C OMPONENTS ................................................... 1221
A.8.1. An Endpoint as a Requester .............................................................................. 1221
A.8.2. An Endpoint as a Completer ............................................................................. 1221
A.8.3. Switches............................................................................................................. 1222
A.8.4. Root Complex .................................................................................................... 1223
B. SYMBOL ENCODING .................................................................................................... 1224
C. PHYSICAL LAYER APPENDIX .................................................................................... 1233
C.1. 8 B /10 B D ATA S CRAMBLING E XAMPLE ....................................................................... 1233
C.2. 128 B /130 B D ATA S CRAMBLING E XAMPLE ................................................................. 1239
D. REQUEST DEPENDENCIES .......................................................................................... 1242
E. ID-BASED ORDERING USAGE .................................................................................... 1245
E.1. I NTRODUCTION .......................................................................................................... 1245
E.2. P OTENTIAL B ENEFITS WITH IDO U SE ........................................................................ 1246
E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1246
E.2.2. Benefits for Switched Environments ................................................................. 1246
E.2.3. Benefits for Integrated Endpoints ..................................................................... 1247
PCI Express Base Specification, Rev. 4.0 Version 1.0
17
E.2.4. IDO Use in Conjunction with RO ..................................................................... 1247
E.3. W HEN TO U SE IDO .................................................................................................... 1247
E.4. W HEN N OT TO U SE IDO ............................................................................................ 1248
E.4.1. When Not to Use IDO with Endpoints .............................................................. 1248
E.4.2. When Not to Use IDO with Root Ports ............................................................. 1248
E.5. S OFTWARE C ONTROL OF IDO U SE ............................................................................. 1249
E.5.1. Software Control of Endpoint IDO Use ............................................................ 1249
E.5.2. Software Control of Root Port IDO Use ........................................................... 1250
F. MESSAGE CODE USAGE .............................................................................................. 1251
G. PROTOCOL MULTIPLEXING ................................................................................... 1253
G.1. P ROTOCOL M ULTIPLEXING I NTERACTIONS WITH PCI E XPRESS ................................. 1256
G.2. PMUX P ACKETS ........................................................................................................ 1261
G.3. PMUX P ACKET L AYOUT ........................................................................................... 1262
G.3.1. PMUX Packet Layout for 8b/10b Encoding ..................................................... 1262
G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1264
G.4. PMUX C ONTROL ....................................................................................................... 1267
G.5. PMUX E XTENDED C APABILITY ................................................................................. 1267
G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1268
G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1269
G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1270
G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1272
G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) .......................................... 1275
H. FLOW CONTROL UPDATE LATENCY AND ACK UPDATE LATENCY
CALCULATIONS .................................................................................................................... 1277
H.1. F LOW C ONTROL U PDATE L ATENCY ........................................................................... 1277
H.2. A CK L ATENCY ........................................................................................................... 1279
ACKNOWLEDGEMENTS ...................................................................................................... 1282
PCI Express Base Specification, Rev. 4.0 Version 1.0
18
Figures
F IGURE 1-1: PCI E XPRESS L INK .................................................................................................... 56
F IGURE 1-2: E XAMPLE T OPOLOGY ................................................................................................ 57
F IGURE 1-3: L OGICAL B LOCK D IAGRAM OF A S WITCH ................................................................. 61
F IGURE 1-4: H IGH -L EVEL L AYERING D IAGRAM ........................................................................... 63
F IGURE 1-5: P ACKET F LOW T HROUGH THE L AYERS ..................................................................... 64
F IGURE 2-1: L AYERING D IAGRAM H IGHLIGHTING THE T RANSACTION L AYER .............................. 69
F IGURE 2-2: S ERIAL V IEW OF A TLP ............................................................................................. 72
F IGURE 2-3: G ENERIC TLP F ORMAT ............................................................................................. 73
F IGURE 2-4: F IELDS P RESENT IN A LL TLP S .................................................................................. 74
F IGURE 2-5: F IELDS P RESENT IN A LL TLP H EADERS .................................................................... 75
F IGURE 2-6: E XAMPLES OF C OMPLETER T ARGET M EMORY A CCESS FOR F ETCH A DD ................... 80
F IGURE 2-7: 64- BIT A DDRESS R OUTING ........................................................................................ 82
F IGURE 2-8: 32- BIT A DDRESS R OUTING ........................................................................................ 82
F IGURE 2-9: ID R OUTING WITH 4 DW H EADER ............................................................................ 84
F IGURE 2-10: ID R OUTING WITH 3 DW H EADER .......................................................................... 84
F IGURE 2-11: L OCATION OF B YTE E NABLES IN TLP H EADER ....................................................... 85
F IGURE 2-12: T RANSACTION D ESCRIPTOR .................................................................................... 88
F IGURE 2-13: T RANSACTION ID .................................................................................................... 88
F IGURE 2-14: A TTRIBUTES F IELD OF T RANSACTION D ESCRIPTOR ................................................ 95
F IGURE 2-15: R EQUEST H EADER F ORMAT FOR 64- BIT A DDRESSING OF M EMORY ........................ 98
F IGURE 2-16: R EQUEST H EADER F ORMAT FOR 32- BIT A DDRESSING OF M EMORY ........................ 98
F IGURE 2-17: R EQUEST H EADER F ORMAT FOR I/O T RANSACTIONS .............................................. 99
F IGURE 2-18: R EQUEST H EADER F ORMAT FOR C ONFIGURATION T RANSACTIONS ...................... 100
F IGURE 2-19: TPH TLP P REFIX .................................................................................................. 101
F IGURE 2-20: L OCATION OF PH[1:0] IN A 4 DW R EQUEST H EADER ........................................... 101
F IGURE 2-21: L OCATION OF PH[1:0] IN A 3 DW R EQUEST H EADER ........................................... 102
F IGURE 2-22: L OCATION OF ST[7:0] IN THE M EMORY W RITE R EQUEST H EADER ....................... 102
F IGURE 2-23: L OCATION OF ST[7:0] IN M EMORY R EAD AND A TOMIC O P R EQUEST H EADERS ... 103
F IGURE 2-24: M ESSAGE R EQUEST H EADER ................................................................................ 105
F IGURE 2-25: H EADER FOR V ENDOR -D EFINED M ESSAGES ......................................................... 114
F IGURE 2-26: H EADER FOR PCI-SIG-D EFINED VDM S ................................................................ 116
F IGURE 2-27: LN M ESSAGE ......................................................................................................... 117
F IGURE 2-28: DRS M ESSAGE ...................................................................................................... 118
F IGURE 2-29: FRS M ESSAGE ...................................................................................................... 120
F IGURE 2-30: H IERARCHY ID M ESSAGE ..................................................................................... 121
F IGURE 2-31: LTR M ESSAGE ...................................................................................................... 123
F IGURE 2-32: OBFF M ESSAGE ................................................................................................... 123
F IGURE 2-33: PTM R EQUEST /R ESPONSE M ESSAGE ..................................................................... 124
F IGURE 2-34: PTM R ESPONSE D M ESSAGE (4 DW HEADER AND 1 DW PAYLOAD ) ...................... 125
F IGURE 2-35: C OMPLETION H EADER F ORMAT ............................................................................ 126
F IGURE 2-36: (N ON -ARI) C OMPLETER ID .................................................................................. 126
F IGURE 2-37: ARI C OMPLETER ID .............................................................................................. 127
F IGURE 2-38: F LOWCHART FOR H ANDLING OF R ECEIVED TLP S ................................................. 133
F IGURE 2-39: F LOWCHART FOR S WITCH H ANDLING OF TLP S ..................................................... 135
PCI Express Base Specification, Rev. 4.0 Version 1.0
19
F IGURE 2-40: F LOWCHART FOR H ANDLING OF R ECEIVED R EQUEST ........................................... 140
F IGURE 2-41: E XAMPLE C OMPLETION D ATA WHEN SOME B YTE E NABLES ARE 0 B ..................... 144
F IGURE 2-42: V IRTUAL C HANNEL C ONCEPT – A N I LLUSTRATION .............................................. 156
F IGURE 2-43: V IRTUAL C HANNEL C ONCEPT – S WITCH I NTERNALS (U PSTREAM F LOW ) ............. 157
F IGURE 2-44: A N E XAMPLE OF TC/VC C ONFIGURATIONS .......................................................... 159
F IGURE 2-45: R ELATIONSHIP B ETWEEN R EQUESTER AND U LTIMATE C OMPLETER ..................... 160
F IGURE 2-46: C ALCULATION OF 32- BIT ECRC FOR TLP E ND TO E ND D ATA I NTEGRITY
P ROTECTION ........................................................................................................................ 177
F IGURE 3-1: L AYERING D IAGRAM H IGHLIGHTING THE D ATA L INK L AYER ................................ 185
F IGURE 3-2: D ATA L INK C ONTROL AND M ANAGEMENT S TATE M ACHINE .................................. 188
F IGURE 3-3: VC0 F LOW C ONTROL I NITIALIZATION E XAMPLE WITH 8 B /10 B E NCODING - BASED
F RAMING ............................................................................................................................. 196
F IGURE 3-4: DLLP T YPE AND CRC F IELDS ................................................................................ 198
F IGURE 3-5: D ATA L INK L AYER P ACKET F ORMAT FOR A CK AND N AK ....................................... 201
F IGURE 3-6: NOP D ATA L INK L AYER P ACKET F ORMAT ............................................................. 201
F IGURE 3-7: D ATA L INK L AYER P ACKET F ORMAT FOR I NIT FC1 ................................................ 201
F IGURE 3-8: D ATA L INK L AYER P ACKET F ORMAT FOR I NIT FC2 ................................................ 201
F IGURE 3-9: D ATA L INK L AYER P ACKET F ORMAT FOR U PDATE FC ............................................ 202
F IGURE 3-10: PM D ATA L INK L AYER P ACKET F ORMAT ............................................................. 202
F IGURE 3-11: V ENDOR - SPECIFIC D ATA L INK L AYER P ACKET F ORMAT ...................................... 202
F IGURE 3-12: D ATA L INK F EATURE DLLP ................................................................................. 202
F IGURE 3-13: D IAGRAM OF CRC C ALCULATION FOR DLLP S ..................................................... 204
F IGURE 3-14: TLP WITH LCRC AND TLP S EQUENCE N UMBER A PPLIED ................................... 204
F IGURE 3-15: TLP F OLLOWING A PPLICATION OF TLP S EQUENCE N UMBER AND R ESERVED B ITS
............................................................................................................................................. 207
F IGURE 3-16: C ALCULATION OF LCRC ...................................................................................... 209
F IGURE 3-17: R ECEIVED DLLP E RROR C HECK F LOWCHART ...................................................... 215
F IGURE 3-18: A CK /N AK DLLP P ROCESSING F LOWCHART .......................................................... 216
F IGURE 3-19: R ECEIVE D ATA L INK L AYER H ANDLING OF TLP S ................................................ 220
F IGURE 4-1: L AYERING D IAGRAM H IGHLIGHTING P HYSICAL L AYER .......................................... 225
F IGURE 4-2: C HARACTER TO S YMBOL M APPING ......................................................................... 226
F IGURE 4-3: B IT T RANSMISSION O RDER ON P HYSICAL L ANES - X 1 E XAMPLE ............................ 227
F IGURE 4-4: B IT T RANSMISSION O RDER ON P HYSICAL L ANES - X 4 E XAMPLE ............................ 227
F IGURE 4-5: TLP WITH F RAMING S YMBOLS A PPLIED ................................................................. 230
F IGURE 4-6: DLLP WITH F RAMING S YMBOLS A PPLIED .............................................................. 231
F IGURE 4-7: F RAMED TLP ON A X 1 L INK .................................................................................... 231
F IGURE 4-8: F RAMED TLP ON A X 2 L INK .................................................................................... 232
F IGURE 4-9: F RAMED TLP ON A X 4 L INK .................................................................................... 232
F IGURE 4-10: LFSR WITH 8 B /10 B S CRAMBLING P OLYNOMIAL ................................................... 234
F IGURE 4-11: E XAMPLE OF B IT T RANSMISSION O RDER IN A X 1 L INK S HOWING 130 B ITS OF A
B LOCK ................................................................................................................................. 235
F IGURE 4-12: E XAMPLE OF B IT P LACEMENT IN A X 4 L INK WITH O NE B LOCK PER L ANE ............ 236
F IGURE 4-13: L AYOUT OF F RAMING T OKENS .............................................................................. 239
F IGURE 4-14: TLP AND DLLP L AYOUT ...................................................................................... 241
F IGURE 4-15: P ACKET T RANSMISSION IN A X 8 L INK ................................................................... 241
F IGURE 4-16: N ULLIFIED TLP L AYOUT IN A X 8 L INK WITH O THER P ACKETS ............................. 242
PCI Express Base Specification, Rev. 4.0 Version 1.0
20
F IGURE 4-17: SKP O RDERED S ET OF L ENGTH 66- BIT IN A X 8 L INK ............................................ 242
F IGURE 4-18: LFSR WITH S CRAMBLING P OLYNOMIAL IN 8.0 GT/ S AND A BOVE D ATA R ATE .... 250
F IGURE 4-19: A LTERNATE I MPLEMENTATION OF THE LFSR FOR D ESCRAMBLING ...................... 252
F IGURE 4-20: 8.0 GT/ S E QUALIZATION F LOW ............................................................................. 260
F IGURE 4-21: 16.0 GT/ S E QUALIZATION F LOW ........................................................................... 261
F IGURE 4-22: E LECTRICAL I DLE E XIT O RDERED S ET FOR 8.0 GT/ S AND A BOVE D ATA R ATES ... 273
F IGURE 4-23: M AIN S TATE D IAGRAM FOR L INK T RAINING AND S TATUS S TATE M ACHINE ........ 288
F IGURE 4-24: D ETECT S UBSTATE M ACHINE ............................................................................... 290
F IGURE 4-25: P OLLING S UBSTATE M ACHINE .............................................................................. 301
F IGURE 4-26: C ONFIGURATION S UBSTATE M ACHINE .................................................................. 317
F IGURE 4-27: R ECOVERY S UBSTATE M ACHINE ........................................................................... 344
F IGURE 4-28: L0 S S UBSTATE M ACHINE ...................................................................................... 350
F IGURE 4-29: L1 S UBSTATE M ACHINE ........................................................................................ 352
F IGURE 4-30: L2 S UBSTATE M ACHINE ........................................................................................ 354
F IGURE 4-31: L OOPBACK S UBSTATE M ACHINE ........................................................................... 359
F IGURE 4-32: R ECEIVER N UMBER A SSIGNMENT ......................................................................... 376
F IGURE 4-33: S UPPORTED T OPOLOGIES ................................................................................. 390
F IGURE 4-34: R ETIMER CLKREQ# C ONNECTION T OPOLOGY .................................................... 420
F IGURE 5-1: L INK P OWER M ANAGEMENT S TATE F LOW D IAGRAM ............................................. 428
F IGURE 5-2: E NTRY INTO THE L1 L INK S TATE ............................................................................ 437
F IGURE 5-3: E XIT FROM L1 L INK S TATE I NITIATED BY U PSTREAM C OMPONENT ........................ 440
F IGURE 5-4: C ONCEPTUAL D IAGRAMS S HOWING T WO E XAMPLE C ASES OF WAKE# R OUTING . 443
F IGURE 5-5: A C ONCEPTUAL PME C ONTROL S TATE M ACHINE .................................................. 447
F IGURE 5-6: L1 T RANSITION S EQUENCE E NDING WITH A R EJECTION (L0 S E NABLED ) ................ 460
F IGURE 5-7: L1 S UCCESSFUL T RANSITION S EQUENCE ................................................................ 461
F IGURE 5-8: E XAMPLE OF L1 E XIT L ATENCY C OMPUTATION ..................................................... 463
F IGURE 5-9: S TATE D IAGRAM FOR L1 PM S UBSTATES ................................................................ 468
F IGURE 5-10: D OWNSTREAM P ORT WITH A S INGLE PLL ............................................................. 469
F IGURE 5-11: M ULTIPLE D OWNSTREAM P ORTS WITH A SHARED PLL ......................................... 470
F IGURE 5-12: E XAMPLE : L1.1 W AVEFORMS I LLUSTRATING U PSTREAM P ORT I NITIATED E XIT ... 472
F IGURE 5-13: E XAMPLE : L1.1 W AVEFORMS I LLUSTRATING D OWNSTREAM P ORT I NITIATED E XIT
............................................................................................................................................. 473
F IGURE 5-14: L1.2 S UBSTATES .................................................................................................... 474
F IGURE 5-15: E XAMPLE : I LLUSTRATION OF B OUNDARY C ONDITION DUE TO D IFFERENT S AMPLING
OF CLKREQ# ...................................................................................................................... 475
F IGURE 5-16: E XAMPLE : L1.2 W AVEFORMS I LLUSTRATING U PSTREAM P ORT I NITIATED E XIT ... 477
F IGURE 5-17: E XAMPLE : L1.2 W AVEFORMS I LLUSTRATING D OWNSTREAM P ORT I NITIATED E XIT
............................................................................................................................................. 477
F IGURE 5-18: F UNCTION P OWER M ANAGEMENT S TATE T RANSITIONS ....................................... 480
F IGURE 5-19: N ON -B RIDGE F UNCTION P OWER M ANAGEMENT D IAGRAM .................................. 481
F IGURE 5-20: PCI E XPRESS B RIDGE P OWER M ANAGEMENT D IAGRAM ...................................... 486
F IGURE 6-1: E RROR C LASSIFICATION .......................................................................................... 501
F IGURE 6-2: F LOWCHART S HOWING S EQUENCE OF D EVICE E RROR S IGNALING AND L OGGING
O PERATIONS ........................................................................................................................ 518
F IGURE 6-3: P SEUDO L OGIC D IAGRAM FOR E RROR M ESSAGE C ONTROLS .................................. 519
F IGURE 6-4: TC F ILTERING E XAMPLE ......................................................................................... 538
PCI Express Base Specification, Rev. 4.0 Version 1.0
21
F IGURE 6-5: TC TO VC M APPING E XAMPLE ............................................................................... 538
F IGURE 6-6: A N E XAMPLE OF T RAFFIC F LOW I LLUSTRATING I NGRESS AND E GRESS .................. 540
F IGURE 6-7: A N E XAMPLE OF D IFFERENTIATED T RAFFIC F LOW T HROUGH A S WITCH ................ 540
F IGURE 6-8: S WITCH A RBITRATION S TRUCTURE ......................................................................... 541
F IGURE 6-9: VC ID AND P RIORITY O RDER – A N E XAMPLE ......................................................... 543
F IGURE 6-10: M ULTI -F UNCTION A RBITRATION M ODEL .............................................................. 546
F IGURE 6-11: R OOT C OMPLEX R EPRESENTED AS A S INGLE C OMPONENT ................................... 579
F IGURE 6-12: R OOT C OMPLEX R EPRESENTED AS M ULTIPLE C OMPONENTS ................................ 580
F IGURE 6-13: E XAMPLE S YSTEM T OPOLOGY WITH ARI D EVICES ............................................... 593
F IGURE 6-14: S EGMENTATION OF THE M ULTICAST A DDRESS R ANGE ......................................... 595
F IGURE 6-15: L ATENCY F IELDS F ORMAT FOR LTR M ESSAGES ................................................... 614
F IGURE 6-16: CLKREQ# AND C LOCK P OWER M ANAGEMENT ................................................... 618
F IGURE 6-17: U SE OF LTR AND C LOCK P OWER M ANAGEMENT .................................................. 619
F IGURE 6-18: C ODES AND E QUIVALENT WAKE# P ATTERNS ...................................................... 621
F IGURE 6-19: E XAMPLE P LATFORM T OPOLOGY S HOWING A L INK W HERE OBFF IS C ARRIED BY
M ESSAGES ........................................................................................................................... 622
F IGURE 6-20: PASID TLP P REFIX : ............................................................................................. 625
F IGURE 6-21: S AMPLE S YSTEM B LOCK D IAGRAM ....................................................................... 629
F IGURE 6-22: LN P ROTOCOL B ASIC O PERATION ......................................................................... 630
F IGURE 6-23: E XAMPLE S YSTEM T OPOLOGIES USING PTM ......................................................... 635
F IGURE 6-24: P RECISION T IME M EASUREMENT L INK P ROTOCOL ................................................ 636
F IGURE 6-25: P RECISION T IME M EASUREMENT E XAMPLE ........................................................... 637
F IGURE 6-26: PTM R EQUESTER O PERATION ............................................................................... 640
F IGURE 6-27: PTM T IMESTAMP C APTURE E XAMPLE ................................................................... 643
F IGURE 6-28: E XAMPLE I LLUSTRATING A PPLICATION OF E NHANCED A LLOCATION .................... 647
F IGURE 6-29: E MERGENCY P OWER R EDUCTION S TATE : E XAMPLE A DD - IN C ARD ...................... 651
F IGURE 6-30: FPB H IGH L EVEL D IAGRAM AND E XAMPLE T OPOLOGY ....................................... 656
F IGURE 6-31: E XAMPLE I LLUSTRATING “F LATTENING ” OF A S WITCH ......................................... 657
F IGURE 6-32: V ECTOR M ECHANISM FOR A DDRESS R ANGE D ECODING ....................................... 657
F IGURE 6-33: R ELATIONSHIP BETWEEN FPB AND NON -FPB D ECODE M ECHANISMS .................. 658
F IGURE 6-34: R OUTING ID S (RID S ) AND S UPPORTED G RANULARITIES ...................................... 660
F IGURE 6-35: A DDRESSES IN M EMORY B ELOW 4 GB AND E FFECT OF G RANULARITY ................ 662
F IGURE 6-36: VPD F ORMAT ....................................................................................................... 667
F IGURE 6-37: E XAMPLE NPEM C ONFIGURATION USING A D OWNSTREAM P ORT ........................ 672
F IGURE 6-38: E XAMPLE NPEM C ONFIGURATION USING AN U PSTREAM P ORT ............................ 672
F IGURE 6-39: NPEM C OMMAND F LOW ...................................................................................... 673
F IGURE 7-1: PCI E XPRESS R OOT C OMPLEX D EVICE M APPING ................................................... 676
F IGURE 7-2: PCI E XPRESS S WITCH D EVICE M APPING ................................................................ 676
F IGURE 7-3: PCI E XPRESS C ONFIGURATION S PACE L AYOUT ...................................................... 677
F IGURE 7-4: C OMMON C ONFIGURATION S PACE H EADER ............................................................ 688
F IGURE 7-5: C OMMAND R EGISTER .............................................................................................. 688
F IGURE 7-6: S TATUS R EGISTER ................................................................................................... 693
F IGURE 7-7: C LASS C ODE R EGISTER ........................................................................................... 696
F IGURE 7-8: H EADER T YPE R EGISTER ......................................................................................... 697
F IGURE 7-9: BIST R EGISTER ....................................................................................................... 698
F IGURE 7-10: T YPE 0 C ONFIGURATION S PACE H EADER .............................................................. 700
PCI Express Base Specification, Rev. 4.0 Version 1.0
22
F IGURE 7-11: B ASE A DDRESS R EGISTER FOR M EMORY .............................................................. 701
F IGURE 7-12: B ASE R EGISTER FOR I/O ........................................................................................ 701
F IGURE 7-13: E XPANSION ROM B ASE A DDRESS R EGISTER L AYOUT ......................................... 706
F IGURE 7-14: T YPE 1 C ONFIGURATION S PACE H EADER .............................................................. 708
F IGURE 7-15: S ECONDARY S TATUS R EGISTER ............................................................................ 711
F IGURE 7-16: B RIDGE C ONTROL R EGISTER ................................................................................. 715
F IGURE 7-17: P OWER M ANAGEMENT C APABILITY S TRUCTURE .................................................. 717
F IGURE 7-18: P OWER M ANAGEMENT C APABILITIES R EGISTER ................................................... 718
F IGURE 7-19: P OWER M ANAGEMENT C ONTROL /S TATUS R EGISTER ............................................ 721
F IGURE 7-20: PCI E XPRESS C APABILITY S TRUCTURE ................................................................. 725
F IGURE 7-21: PCI E XPRESS C APABILITY L IST R EGISTER ............................................................ 726
F IGURE 7-22: PCI E XPRESS C APABILITIES R EGISTER ................................................................. 726
F IGURE 7-23: D EVICE C APABILITIES R EGISTER .......................................................................... 729
F IGURE 7-24: D EVICE C ONTROL R EGISTER ................................................................................. 733
F IGURE 7-25: D EVICE S TATUS R EGISTER .................................................................................... 740
F IGURE 7-26: L INK C APABILITIES R EGISTER ............................................................................... 742
F IGURE 7-27: L INK C ONTROL R EGISTER ..................................................................................... 748
F IGURE 7-28: L INK S TATUS R EGISTER ........................................................................................ 756
F IGURE 7-29: S LOT C APABILITIES R EGISTER .............................................................................. 759
F IGURE 7-30: S LOT C ONTROL R EGISTER ..................................................................................... 762
F IGURE 7-31: S LOT S TATUS R EGISTER ....................................................................................... 765
F IGURE 7-32: R OOT C ONTROL R EGISTER .................................................................................... 767
F IGURE 7-33: R OOT C APABILITIES R EGISTER .............................................................................. 768
F IGURE 7-34: R OOT S TATUS R EGISTER ....................................................................................... 769
F IGURE 7-35: D EVICE C APABILITIES 2 R EGISTER ........................................................................ 770
F IGURE 7-36: D EVICE C ONTROL 2 R EGISTER .............................................................................. 777
F IGURE 7-37: L INK C APABILITIES 2 R EGISTER ............................................................................ 782
F IGURE 7-38: L INK C ONTROL 2 R EGISTER .................................................................................. 786
F IGURE 7-39: L INK S TATUS 2 R EGISTER ..................................................................................... 791
F IGURE 7-40: PCI E XPRESS E XTENDED C ONFIGURATION S PACE L AYOUT .................................. 796
F IGURE 7-41: PCI E XPRESS E XTENDED C APABILITY H EADER .................................................... 797
F IGURE 7-42: MSI C APABILITY S TRUCTURE FOR 32- BIT M ESSAGE A DDRESS ............................ 798
F IGURE 7-43: MSI C APABILITY S TRUCTURE FOR 64- BIT M ESSAGE A DDRESS ............................ 798
F IGURE 7-44: MSI C APABILITY S TRUCTURE FOR 32- BIT M ESSAGE A DDRESS AND PVM ........... 799
F IGURE 7-45: MSI C APABILITY S TRUCTURE FOR 64- BIT M ESSAGE A DDRESS AND PVM ........... 799
F IGURE 7-46: MSI C APABILITY H EADER .................................................................................... 800
F IGURE 7-47: M ESSAGE C ONTROL R EGISTER FOR MSI ............................................................... 800
F IGURE 7-48: M ESSAGE A DDRESS R EGISTER FOR MSI ............................................................... 803
F IGURE 7-49: M ESSAGE U PPER A DDRESS R EGISTER FOR MSI .................................................... 803
F IGURE 7-50: M ESSAGE D ATA R EGISTER FOR MSI ..................................................................... 804
F IGURE 7-51: E XTENDED M ESSAGE D ATA R EGISTER FOR MSI (O PTIONAL ) ............................... 804
F IGURE 7-52: M ASK B ITS R EGISTER FOR MSI ............................................................................ 805
F IGURE 7-53: P ENDING B ITS R EGISTER FOR MSI ........................................................................ 806
F IGURE 7-54: MSI-X C APABILITY S TRUCTURE ........................................................................... 807
F IGURE 7-55: MSI-X T ABLE S TRUCTURE ................................................................................... 807
F IGURE 7-56: MSI-X PBA S TRUCTURE ...................................................................................... 807
PCI Express Base Specification, Rev. 4.0 Version 1.0
23
F IGURE 7-57: MSI-X C APAB FPB ILITY H EADER ......................................................................... 809
F IGURE 7-58: M ESSAGE C ONTROL R EGISTER FOR MSI-X .......................................................... 810
F IGURE 7-59: T ABLE O FFSET /T ABLE BIR R EGISTER FOR MSI-X ............................................... 810
F IGURE 7-60: PBA O FFSET /PBA BIR R EGISTER FOR MSI-X ..................................................... 811
F IGURE 7-61: M ESSAGE A DDRESS R EGISTER FOR MSI-X T ABLE E NTRIES ................................. 812
F IGURE 7-62: M ESSAGE U PPER A DDRESS R EGISTER FOR MSI-X T ABLE E NTRIES ...................... 813
F IGURE 7-63: M ESSAGE D ATA R EGISTER FOR MSI-X T ABLE E NTRIES ....................................... 813
F IGURE 7-64: V ECTOR C ONTROL R EGISTER FOR MSI-X T ABLE E NTRIES ................................... 814
F IGURE 7-65: P ENDING B ITS R EGISTER FOR MSI-X PBA E NTRIES ............................................. 814
F IGURE 7-66: S ECONDARY PCI E XPRESS E XTENDED C APABILITY S TRUCTURE .......................... 815
F IGURE 7-67: S ECONDARY PCI E XPRESS E XTENDED C APABILITY H EADER ................................ 816
F IGURE 7-68: L INK C ONTROL 3 R EGISTER .................................................................................. 816
F IGURE 7-69: L ANE E RROR S TATUS R EGISTER ........................................................................... 818
F IGURE 7-70: L ANE E QUALIZATION C ONTROL R EGISTER ........................................................... 818
F IGURE 7-71: L ANE E QUALIZATION C ONTROL R EGISTER E NTRY ............................................... 819
F IGURE 7-72: D ATA L INK F EATURE E XTENDED C APABILITY ...................................................... 822
F IGURE 7-73: D ATA L INK F EATURE E XTENDED C APABILITY H EADER ....................................... 822
F IGURE 7-74: D ATA L INK F EATURE C APABILITIES R EGISTER ..................................................... 823
F IGURE 7-75: D ATA L INK F EATURE S TATUS R EGISTER .............................................................. 824
F IGURE 7-76: P HYSICAL L AYER 16.0 GT/ S E XTENDED C APABILITY ........................................... 825
F IGURE 7-77: 16.0 GT/ S S TATUS R EGISTER ................................................................................ 826
F IGURE 7-78: 16.0 GT/ S L OCAL D ATA P ARITY M ISMATCH S TATUS R EGISTER ........................... 828
F IGURE 7-79: 16.0 GT/ S F IRST R ETIMER D ATA P ARITY M ISMATCH S TATUS R EGISTER .............. 828
F IGURE 7-80: 16.0 GT/ S S ECOND R ETIMER D ATA P ARITY M ISMATCH S TATUS R EGISTER ......... 829
F IGURE 7-81: H IGH L EVEL S TRUCTURE OF 16.0 GT/ S L ANE E QUALIZATION C ONTROL R EGISTER
............................................................................................................................................. 830
F IGURE 7-82: 16.0 GT/ S L ANE ((M AXIMUM L INK W IDTH – 1):0) E QUALIZATION C ONTROL
R EGISTER E NTRY ................................................................................................................. 830
F IGURE 7-83: M ARGINING E XTENDED C APABILITY .................................................................... 832
F IGURE 7-84: P HYSICAL L AYER 16.0 GT/ S M ARGINING E XTENDED C APABILITY H EADER ......... 833
F IGURE 7-85: M ARGINING P ORT C APABILITIES R EGISTER .......................................................... 833
F IGURE 7-86: M ARGINING P ORT S TATUS R EGISTER .................................................................... 834
F IGURE 7-87: L ANE N: M ARGINING L ANE C ONTROL R EGISTER E NTRY ...................................... 835
F IGURE 7-88: L ANE N: M ARGINING L ANE S TATUS R EGISTER E NTRY ......................................... 836
F IGURE 7-89: ACS E XTENDED C APABILITY ................................................................................ 837
F IGURE 7-90: ACS E XTENDED C APABILITY H EADER ................................................................. 837
F IGURE 7-91: ACS C APABILITY R EGISTER ................................................................................. 838
F IGURE 7-92: ACS C ONTROL R EGISTER ..................................................................................... 839
F IGURE 7-93: E GRESS C ONTROL V ECTOR R EGISTER ................................................................... 841
F IGURE 7-94: PCI E XPRESS P OWER B UDGETING C APABILITY S TRUCTURE ................................. 842
F IGURE 7-95: P OWER B UDGETING E XTENDED C APABILITY H EADER .......................................... 843
F IGURE 7-96: P OWER B UDGETING D ATA R EGISTER .................................................................... 844
F IGURE 7-97: P OWER B UDGET C APABILITY R EGISTER ............................................................... 846
F IGURE 7-98: LTR E XTENDED C APABILITY S TRUCTURE ............................................................ 847
F IGURE 7-99: LTR E XTENDED C APABILITY H EADER .................................................................. 847
F IGURE 7-100: M AX S NOOP L ATENCY R EGISTER ....................................................................... 848
PCI Express Base Specification, Rev. 4.0 Version 1.0
24
F IGURE 7-101: M AX N O -S NOOP L ATENCY R EGISTER ................................................................. 849
F IGURE 7-102: L1 PM S UBSTATES C APABILITY .......................................................................... 850
F IGURE 7-103: L1 PM S UBSTATES E XTENDED C APABILITY H EADER ......................................... 850
F IGURE 7-104: L1 PM S UBSTATES C APABILITIES R EGISTER ....................................................... 851
F IGURE 7-105: L1 PM S UBSTATES C ONTROL 1 R EGISTER .......................................................... 853
F IGURE 7-106: L1 PM S UBSTATES C ONTROL 2 R EGISTER .......................................................... 855
F IGURE 7-107: PCI E XPRESS A DVANCED E RROR R EPORTING E XTENDED C APABILITY S TRUCTURE
............................................................................................................................................. 857
F IGURE 7-108: A DVANCED E RROR R EPORTING E XTENDED C APABILITY H EADER ...................... 857
F IGURE 7-109: U NCORRECTABLE E RROR S TATUS R EGISTER ...................................................... 859
F IGURE 7-110: U NCORRECTABLE E RROR M ASK R EGISTER ......................................................... 861
F IGURE 7-111: U NCORRECTABLE E RROR S EVERITY R EGISTER ................................................... 863
F IGURE 7-112: C ORRECTABLE E RROR S TATUS R EGISTER ........................................................... 865
F IGURE 7-113: C ORRECTABLE E RROR M ASK R EGISTER ............................................................. 866
F IGURE 7-114: A DVANCED E RROR C APABILITIES AND C ONTROL R EGISTER ............................... 867
F IGURE 7-115: H EADER L OG R EGISTER ...................................................................................... 868
F IGURE 7-116: R OOT E RROR C OMMAND R EGISTER .................................................................... 869
F IGURE 7-117: R OOT E RROR S TATUS R EGISTER ......................................................................... 871
F IGURE 7-118: E RROR S OURCE I DENTIFICATION R EGISTER ........................................................ 872
F IGURE 7-119: TLP P REFIX L OG R EGISTER ................................................................................ 874
F IGURE 7-120: F IRST DW OF E NHANCED A LLOCATION C APABILITY .......................................... 874
F IGURE 7-121: F IRST DW OF E ACH E NTRY FOR E NHANCED A LLOCATION C APABILITY ............. 875
F IGURE 7-122: F ORMAT OF E NTRY FOR E NHANCED A LLOCATION C APABILITY .......................... 878
F IGURE 7-123: E XAMPLE E NTRY WITH 64 B B ASE AND 64 B M AX O FFSET .................................... 880
F IGURE 7-124: E XAMPLE E NTRY WITH 64 B B ASE AND 32 B M AX O FFSET .................................... 880
F IGURE 7-125: E XAMPLE E NTRY WITH 32 B B ASE AND 64 B M AX O FFSET .................................... 881
F IGURE 7-126: E XAMPLE E NTRY WITH 32 B B ASE AND 32 B M AX O FFSET .................................... 881
F IGURE 7-127: R ESIZABLE BAR C APABILITY ............................................................................. 883
F IGURE 7-128: R ESIZABLE BAR E XTENDED C APABILITY H EADER ............................................. 883
F IGURE 7-129: R ESIZABLE BAR C APABILITY R EGISTER ............................................................. 884
F IGURE 7-130: R ESIZABLE BAR C ONTROL R EGISTER ................................................................ 885
F IGURE 7-131: ARI C APABILITY ................................................................................................. 887
F IGURE 7-132: ARI C APABILITY H EADER .................................................................................. 888
F IGURE 7-133: ARI C APABILITY R EGISTER ................................................................................ 888
F IGURE 7-134: ARI C ONTROL R EGISTER .................................................................................... 889
F IGURE 7-135: PASID E XTENDED C APABILITY S TRUCTURE ...................................................... 890
F IGURE 7-136: PASID E XTENDED C APABILITY H EADER ............................................................ 890
F IGURE 7-137: PASID C APABILITY R EGISTER ............................................................................ 891
F IGURE 7-138: PASID C ONTROL R EGISTER ............................................................................... 892
F IGURE 7-139: FRS E XTENDED C APABILITY .............................................................................. 893
F IGURE 7-140: FRS Q UEUING E XTENDED C APABILITY H EADER ................................................ 893
F IGURE 7-141: FRS Q UEUING C APABILITY R EGISTER ................................................................ 894
F IGURE 7-142: FRS Q UEUEING S TATUS R EGISTER ..................................................................... 895
F IGURE 7-143: FRS Q UEUEING C ONTROL R EGISTER .................................................................. 895
F IGURE 7-144: FRS M ESSAGE Q UEUE R EGISTER ......................................................................... 896
F IGURE 7-145: FPB C APABILITY S TRUCTURE ............................................................................. 897
PCI Express Base Specification, Rev. 4.0 Version 1.0
25
F IGURE 7-146: FPB C APABILITY H EADER .................................................................................. 897
F IGURE 7-147: FPB C APABILITIES R EGISTER .............................................................................. 898
F IGURE 7-148: FPB RID V ECTOR C ONTROL 1 R EGISTER ........................................................... 900
F IGURE 7-149: FPB RID V ECTOR C ONTROL 2 R EGISTER ........................................................... 901
F IGURE 7-150: FPB MEM L OW V ECTOR C ONTROL R EGISTER ................................................... 902
F IGURE 7-151: FPB MEM H IGH V ECTOR C ONTROL 1 R EGISTER ............................................... 904
F IGURE 7-152: FPB MEM H IGH V ECTOR C ONTROL 2 R EGISTER ............................................... 905
F IGURE 7-153: FPB V ECTOR A CCESS C ONTROL R EGISTER ........................................................ 906
F IGURE 7-154: FPB V ECTOR A CCESS D ATA R EGISTER ............................................................... 908
F IGURE 7-155: PCI E XPRESS V IRTUAL C HANNEL C APABILITY S TRUCTURE ............................... 909
F IGURE 7-156: V IRTUAL C HANNEL E XTENDED C APABILITY H EADER ........................................ 910
F IGURE 7-157: P ORT VC C APABILITY R EGISTER 1 ..................................................................... 911
F IGURE 7-158: P ORT VC C APABILITY R EGISTER 2 ..................................................................... 912
F IGURE 7-159: P ORT VC C ONTROL R EGISTER ............................................................................ 913
F IGURE 7-160: P ORT VC S TATUS R EGISTER ............................................................................... 914
F IGURE 7-161: VC R ESOURCE C APABILITY R EGISTER ................................................................ 915
F IGURE 7-162: VC R ESOURCE C ONTROL R EGISTER .................................................................... 917
F IGURE 7-163: VC R ESOURCE S TATUS R EGISTER ....................................................................... 919
F IGURE 7-164: E XAMPLE VC A RBITRATION T ABLE WITH 32 P HASES ......................................... 921
F IGURE 7-165: E XAMPLE P ORT A RBITRATION T ABLE WITH 128 P HASES AND 2- BIT T ABLE E NTRIES
............................................................................................................................................. 922
F IGURE 7-166: PCI E XPRESS MFVC C APABILITY S TRUCTURE ................................................... 924
F IGURE 7-167: MFVC E XTENDED C APABILITY H EADER ............................................................ 925
F IGURE 7-168: P ORT VC C APABILITY R EGISTER 1 ..................................................................... 926
F IGURE 7-169: P ORT VC C APABILITY R EGISTER 2 ..................................................................... 927
F IGURE 7-170: P ORT VC C ONTROL R EGISTER ............................................................................ 928
F IGURE 7-171: P ORT VC S TATUS R EGISTER ............................................................................... 929
F IGURE 7-172: VC R ESOURCE C APABILITY R EGISTER ................................................................ 929
F IGURE 7-173: VC R ESOURCE C ONTROL R EGISTER .................................................................... 931
F IGURE 7-174: VC R ESOURCE S TATUS R EGISTER ....................................................................... 933
F IGURE 7-175: PCI E XPRESS D EVICE S ERIAL N UMBER C APABILITY S TRUCTURE ....................... 936
F IGURE 7-176: D EVICE S ERIAL N UMBER E XTENDED C APABILITY H EADER ................................ 936
F IGURE 7-177: S ERIAL N UMBER R EGISTER ................................................................................. 937
F IGURE 7-178: V ENDOR -S PECIFIC C APABILITY .......................................................................... 938
F IGURE 7-179: PCI E XPRESS VSEC S TRUCTURE ........................................................................ 939
F IGURE 7-180: V ENDOR -S PECIFIC E XTENDED C APABILITY H EADER .......................................... 939
F IGURE 7-181: V ENDOR -S PECIFIC H EADER ................................................................................ 940
F IGURE 7-182: D ESIGNATED V ENDOR -S PECIFIC E XTENDED C APABILITY .................................... 941
F IGURE 7-183: D ESIGNATED V ENDOR -S PECIFIC E XTENDED C APABILITY H EADER ..................... 941
F IGURE 7-184: D ESIGNATED V ENDOR -S PECIFIC H EADER 1 ......................................................... 942
F IGURE 7-185: D ESIGNATED V ENDOR -S PECIFIC H EADER 2 ......................................................... 943
F IGURE 7-186: R OOT C OMPLEX F EATURES C APABILITY S TRUCTURE ......................................... 943
F IGURE 7-187: RCRB H EADER E XTENDED C APABILITY H EADER .............................................. 944
F IGURE 7-188: V ENDOR ID AND D EVICE ID ............................................................................... 944
F IGURE 7-189: RCRB C APABILITIES .......................................................................................... 945
F IGURE 7-190: RCRB C ONTROL ................................................................................................. 945
PCI Express Base Specification, Rev. 4.0 Version 1.0
26
F IGURE 7-191: PCI E XPRESS R OOT C OMPLEX L INK D ECLARATION C APABILITY ....................... 947
F IGURE 7-192: R OOT C OMPLEX L INK D ECLARATION E XTENDED C APABILITY H EADER ............. 947
F IGURE 7-193: E LEMENT S ELF D ESCRIPTION R EGISTER ............................................................. 948
F IGURE 7-194: L INK E NTRY ........................................................................................................ 949
F IGURE 7-195: L INK D ESCRIPTION R EGISTER ............................................................................. 949
F IGURE 7-196: L INK A DDRESS FOR L INK T YPE 0 ........................................................................ 951
F IGURE 7-197: L INK A DDRESS FOR L INK T YPE 1 ........................................................................ 952
F IGURE 7-198: R OOT C OMPLEX I NTERNAL L INK C ONTROL C APABILITY .................................... 952
F IGURE 7-199: R OOT I NTERNAL L INK C ONTROL E XTENDED C APABILITY H EADER .................... 953
F IGURE 7-200: R OOT C OMPLEX L INK C APABILITIES R EGISTER .................................................. 954
F IGURE 7-201: R OOT C OMPLEX L INK C ONTROL R EGISTER ......................................................... 957
F IGURE 7-202: R OOT C OMPLEX L INK S TATUS R EGISTER ............................................................ 959
F IGURE 7-203: R OOT C OMPLEX E VENT C OLLECTOR E NDPOINT A SSOCIATION C APABILITY ....... 960
F IGURE 7-204: R OOT C OMPLEX E VENT C OLLECTOR E NDPOINT A SSOCIATION E XTENDED
C APABILITY H EADER ........................................................................................................... 961
F IGURE 7-205: M ULTICAST E XTENDED C APABILITY S TRUCTURE ............................................... 962
F IGURE 7-206: M ULTICAST E XTENDED C APABILITY H EADER .................................................... 962
F IGURE 7-207: M ULTICAST C APABILITY R EGISTER .................................................................... 963
F IGURE 7-208: M ULTICAST C ONTROL R EGISTER ........................................................................ 964
F IGURE 7-209: MC_B ASE _A DDRESS R EGISTER ......................................................................... 965
F IGURE 7-210: MC_R ECEIVE R EGISTER ..................................................................................... 965
F IGURE 7-211: MC_B LOCK _A LL R EGISTER ............................................................................... 966
F IGURE 7-212: MC_B LOCK _U NTRANSLATED R EGISTER ............................................................ 966
F IGURE 7-213: MC_O VERLAY _BAR .......................................................................................... 967
F IGURE 7-214: D YNAMIC P OWER A LLOCATION C APABILITY S TRUCTURE .................................. 968
F IGURE 7-215: DPA E XTENDED C APABILITY H EADER ............................................................... 968
F IGURE 7-216: DPA C APABILITY R EGISTER ............................................................................... 969
F IGURE 7-217: DPA L ATENCY I NDICATOR R EGISTER ................................................................. 970
F IGURE 7-218: DPA S TATUS R EGISTER ...................................................................................... 970
F IGURE 7-219: DPA C ONTROL R EGISTER ................................................................................... 971
F IGURE 7-220: DPA P OWER A LLOCATION A RRAY ..................................................................... 971
F IGURE 7-221: TPH E XTENDED C APABILITY S TRUCTURE .......................................................... 972
F IGURE 7-222: TPH R EQUESTER E XTENDED C APABILITY H EADER ............................................ 972
F IGURE 7-223: TPH R EQUESTER C APABILITY R EGISTER ............................................................ 973
F IGURE 7-224: TPH R EQUESTER C ONTROL R EGISTER ................................................................ 974
F IGURE 7-225: TPH ST T ABLE ................................................................................................... 975
F IGURE 7-226: LNR E XTENDED C APABILITY .............................................................................. 976
F IGURE 7-227: LNR E XTENDED C APABILITY H EADER ................................................................ 976
F IGURE 7-228: LNR C APABILITY R EGISTER ................................................................................ 977
F IGURE 7-229: LNR C ONTROL R EGISTER .................................................................................... 977
F IGURE 7-230: DPC E XTENDED C APABILITY .............................................................................. 979
F IGURE 7-231: DPC E XTENDED C APABILITY H EADER ................................................................ 979
F IGURE 7-232: DPC C APABILITY R EGISTER ................................................................................ 980
F IGURE 7-233: DPC C ONTROL R EGISTER ................................................................................... 981
F IGURE 7-234: DPC S TATUS R EGISTER ...................................................................................... 983
F IGURE 7-235: DPC E RROR S OURCE ID R EGISTER ..................................................................... 985
PCI Express Base Specification, Rev. 4.0 Version 1.0
27
F IGURE 7-236: RP PIO S TATUS R EGISTER .................................................................................. 985
F IGURE 7-237: RP PIO M ASK R EGISTER ..................................................................................... 986
F IGURE 7-238: RP PIO S EVERITY R EGISTER ............................................................................... 987
F IGURE 7-239: RP PIO S YS E RROR R EGISTER .............................................................................. 988
F IGURE 7-240: RP PIO E XCEPTION R EGISTER ............................................................................. 989
F IGURE 7-241: RP PIO H EADER L OG R EGISTER .......................................................................... 990
F IGURE 7-242: RP PIO I MP S PEC L OG R EGISTER ......................................................................... 991
F IGURE 7-243: RP PIO TLP P REFIX L OG R EGISTER .................................................................... 991
F IGURE 7-244: PTM E XTENDED C APABILITY S TRUCTURE .......................................................... 992
F IGURE 7-245: PTM E XTENDED C APABILITY H EADER ................................................................ 992
F IGURE 7-246: PTM C APABILITY R EGISTER ................................................................................ 993
F IGURE 7-247: PTM C ONTROL R EGISTER .................................................................................... 994
F IGURE 7-248: R EADINESS T IME R EPORTING E XTENDED C APABILITY ....................................... 996
F IGURE 7-249: R EADINESS T IME E NCODING ............................................................................... 997
F IGURE 7-250: R EADINESS T IME R EPORTING E XTENDED C APABILITY H EADER .......................... 997
F IGURE 7-251: R EADINESS T IME R EPORTING 1 R EGISTER ........................................................... 998
F IGURE 7-252: R EADINESS T IME R EPORTING 2 R EGISTER ........................................................... 999
F IGURE 7-253: H IERARCHY ID E XTENDED C APABILITY ........................................................... 1001
F IGURE 7-254: H IERARCHY ID E XTENDED C APABILITY H EADER ............................................. 1001
F IGURE 7-255: H IERARCHY ID S TATUS R EGISTER .................................................................... 1002
F IGURE 7-256: H IERARCHY ID D ATA R EGISTER ....................................................................... 1004
F IGURE 7-257: H IERARCHY ID GUID 1 R EGISTER .................................................................... 1005
F IGURE 7-258: H IERARCHY ID GUID 2 R EGISTER .................................................................... 1005
F IGURE 7-259: H IERARCHY ID GUID 3 R EGISTER .................................................................... 1006
F IGURE 7-260: H IERARCHY ID GUID 4 R EGISTER .................................................................... 1007
F IGURE 7-261: H IERARCHY ID GUID 5 R EGISTER .................................................................... 1007
F IGURE 7-262: VPD C APABILITY S TRUCTURE ........................................................................... 1008
F IGURE 7-263: NPEM E XTENDED C APABILITY ........................................................................ 1010
F IGURE 7-264: NPEM E XTENDED C APABILITY H EADER .......................................................... 1010
F IGURE 7-265: NPEM C APABILITY R EGISTER .......................................................................... 1011
F IGURE 7-266: NPEM C APABILITY R EGISTER .......................................................................... 1011
F IGURE 7-267: NPEM C ONTROL R EGISTER .............................................................................. 1013
F IGURE 7-268: NPEM S TATUS R EGISTER ................................................................................. 1015
F IGURE 8-1: T X T EST B OARD FOR N ON -E MBEDDED R EFCLK .................................................... 1017
F IGURE 8-2: T X T EST BOARD FOR E MBEDDED R EFCLK .............................................................. 1018
F IGURE 8-3: S INGLE - ENDED AND D IFFERENTIAL L EVELS .......................................................... 1019
F IGURE 8-4: T X E QUALIZATION FIR R EPRESENTATION ............................................................ 1021
F IGURE 8-5: D EFINITION OF T X V OLTAGE L EVELS AND E QUALIZATION R ATIOS ...................... 1022
F IGURE 8-6: W AVEFORM M EASUREMENT P OINTS FOR P RE - SHOOT ........................................... 1023
F IGURE 8-7: W AVEFORM M EASUREMENT P OINTS FOR D E - EMPHASIS ........................................ 1023
F IGURE 8-8: V TX-DIFF-PP AND V TX-DIFF-PP-LOW M EASUREMENT .................................................. 1025
F IGURE 8-9: M EASURING V TX-EIEOS-FS AND V TX-EIEOS-RS AT 8.0 GT/ S ........................................ 1027
F IGURE 8-10: C OMPLIANCE P ATTERN AND R ESULTING P ACKAGE L OSS T EST W AVEFORM ...... 1028
F IGURE 8-11: 2.5 AND 5.0 GT/ S T RANSMITTER M ARGINING V OLTAGE L EVELS AND C ODES .... 1029
F IGURE 8-12: F IRST O RDER CC B EHAVIORAL CDR T RANSFER F UNCTIONS .............................. 1032
PCI Express Base Specification, Rev. 4.0 Version 1.0
28
F IGURE 8-13: 2 ND O RDER B EHAVIORAL SRIS CDR T RANSFER F UNCTIONS FOR 2.5 GT/ S AND
5.0 GT/ S ............................................................................................................................ 1032
F IGURE 8-14: B EHAVIORAL SRIS CDR F UNCTIONS FOR 8.0 AND 16.0 GT/ S ............................ 1033
F IGURE 8-15: R ELATION B ETWEEN D ATA E DGE PDF S AND R ECOVERED D ATA C LOCK ........... 1035
F IGURE 8-16: D ERIVATION OF T TX-UTJ AND T TX-UDJDD .............................................................. 1035
F IGURE 8-17: PWJ R ELATIVE TO C ONSECUTIVE E DGES 1 UI A PART ........................................ 1036
F IGURE 8-18: D EFINITION OF T TX-UPW-DJDD AND T TX-UPW-TJ D ATA R ATE D EPENDENT T RANSMITTER
P ARAMETERS ..................................................................................................................... 1037
F IGURE 8-19: T X , R X D IFFERENTIAL R ETURN L OSS M ASK ....................................................... 1040
F IGURE 8-20: T X , R X C OMMON M ODE R ETURN L OSS M ASK .................................................... 1041
F IGURE 8-21: R X T ESTBOARD T OPOLOGY FOR 16.0 GT/ S ......................................................... 1044
F IGURE 8-22: C ALIBRATION C HANNEL IL M ASK E XCLUDING R X P ACKAGE ............................. 1045
F IGURE 8-23: E XAMPLE 16 GT/ S C ALIBRATION C HANNEL ....................................................... 1047
F IGURE 8-24: S TACKUP FOR E XAMPLE 16 GT/ S C ALIBRATION C HANNEL ................................. 1048
F IGURE 8-25: CEM C ONNECTOR D RILL H OLE P AD S TACK ....................................................... 1048
F IGURE 8-26: P AD S TACK FOR SMA D RILL H OLES ................................................................... 1049
F IGURE 8-27: T RANSFER F UNCTION FOR 8.0 GT/ S B EHAVIORAL CTLE ................................... 1051
F IGURE 8-28: L OSS C URVES FOR 8.0 GT/ S B EHAVIORAL CTLE ............................................... 1051
F IGURE 8-29: L OSS C URVES FOR 16.0 GT/ S B EHAVIORAL CTLE ............................................. 1052
F IGURE 8-30: V ARIABLES D EFINITION AND D IAGRAM FOR 1- TAP DFE ..................................... 1053
F IGURE 8-31: D IAGRAM FOR 2- TAP DFE ................................................................................... 1053
F IGURE 8-32: L AYOUT FOR C ALIBRATING THE S TRESSED J ITTER E YE AT 8.0 GT/ S .................. 1055
F IGURE 8-33: L AYOUT FOR C ALIBRATING THE S TRESSED J ITTER E YE AT 16.0 GT/ S ................ 1056
F IGURE 8-34: S J M ASK FOR R ECEIVERS O PERATING IN IR MODE AT 8.0 GT/ S .......................... 1059
F IGURE 8-35: S J M ASK FOR R ECEIVERS O PERATING IN IR MODE AT 16.0 GT/ S ......................... 1059
F IGURE 8-36: S J M ASKS FOR R ECEIVERS O PERATING IN CC M ODE AT 8.0 GT/ S AND 16.0 GT/ S
........................................................................................................................................... 1060
F IGURE 8-37: L AYOUT FOR J ITTER T ESTING C OMMON R EFCLK R X AT 16.0 GT/ S .................... 1061
F IGURE 8-38: L AYOUT FOR J ITTER T ESTING FOR I NDEPENDENT R EFCLK R X AT 16.0 GT/ S ...... 1061
F IGURE 8-39: E XIT FROM I DLE V OLTAGE AND T IME M ARGINS ................................................. 1064
F IGURE 8-40: A LLOWED R ANGES FOR M AXIMUM T IMING AND V OLTAGE M ARGINS ................ 1065
F IGURE 8-41 : F LOW D IAGRAM FOR C HANNEL T OLERANCING AT 2.5 AND 5.0 GT/ S ................ 1070
F IGURE 8-42: F LOW D IAGRAM FOR C HANNEL T OLERANCING AT 8.0 AND 16.0 GT/ S ................ 1071
F IGURE 8-43: T X /R X B EHAVIORAL P ACKAGE M ODELS ............................................................ 1072
F IGURE 8-44: B EHAVIORAL T X AND R X S-P ORT D ESIGNATION ................................................ 1072
F IGURE 8-45: SDD21 P LOTS FOR R OOT AND N ON -R OOT P ACKAGES ........................................ 1073
F IGURE 8-46: D ERIVATION OF 8.0 GT/ S J ITTER P ARAMETERS FOR T ABLE 8-14 ........................ 1075
F IGURE 8-47: EH, EW M ASK .................................................................................................... 1077
F IGURE 8-48: R EFCLK T EST S ETUP ............................................................................................ 1080
F IGURE 8-49: S INGLE -E NDED M EASUREMENT P OINTS FOR A BSOLUTE C ROSS P OINT AND S WING
........................................................................................................................................... 1081
F IGURE 8-50: S INGLE -E NDED M EASUREMENT P OINTS FOR D ELTA C ROSS P OINT ..................... 1082
F IGURE 8-51: S INGLE -E NDED M EASUREMENT P OINTS FOR R ISE AND F ALL T IME M ATCHING .. 1082
F IGURE 8-52: D IFFERENTIAL M EASUREMENT P OINTS FOR D UTY C YCLE AND P ERIOD .............. 1082
F IGURE 8-53: D IFFERENTIAL M EASUREMENT P OINTS FOR R ISE AND F ALL T IME ...................... 1082
F IGURE 8-54: D IFFERENTIAL M EASUREMENT P OINTS FOR R INGBACK ...................................... 1083
PCI Express Base Specification, Rev. 4.0 Version 1.0
29
F IGURE 8-55: L IMITS FOR PHASE JITTER FROM THE R EFERENCE ................................................. 1084
F IGURE 8-56: 5 MH Z PLL T RANSFER F UNCTION E XAMPLE ...................................................... 1085
F IGURE 8-57: C OMMON R EFCLK R X A RCHITECTURE ................................................................ 1086
F IGURE 9-1: G ENERIC P LATFORM C ONFIGURATION .................................................................. 1090
F IGURE 9-2: G ENERIC P LATFORM C ONFIGURATION WITH A VI AND M ULTIPLE SI .................... 1091
F IGURE 9-3: G ENERIC P LATFORM C ONFIGURATION WITH SR-IOV AND IOV E NABLERS .......... 1093
F IGURE 9-4: E XAMPLE M ULTI -F UNCTION D EVICE .................................................................... 1095
F IGURE 9-5: E XAMPLE SR-IOV S INGLE PF C APABLE D EVICE .................................................. 1096
F IGURE 9-6: E XAMPLE SR-IOV M ULTI -PF C APABLE D EVICE .................................................. 1098
F IGURE 9-7: E XAMPLE SR-IOV D EVICE WITH M ULTIPLE B US N UMBERS ................................. 1100
F IGURE 9-8: E XAMPLE SR-IOV D EVICE WITH A M IXTURE OF F UNCTION T YPES ...................... 1101
F IGURE 9-9: I/O V IRTUALIZATION I NTEROPERABILITY ............................................................. 1102
F IGURE 9-10: BAR S PACE E XAMPLE FOR S INGLE BAR D EVICE ............................................... 1104
F IGURE 9-11: I NITIAL VF M IGRATION S TATE A RRAY ............................................................... 1109
F IGURE 9-12: VF M IGRATION S TATE D IAGRAM ....................................................................... 1110
F IGURE 9-13: SR-IOV E XTENDED C APABILITY ........................................................................ 1113
F IGURE 9-14: T YPE 0 C ONFIGURATION S PACE H EADER ............................................................ 1131
F IGURE 9-15: L INK C ONTROL R EGISTER ................................................................................... 1137
F IGURE 9-16: VF R ESIZABLE BAR C APABILITY ....................................................................... 1145
F IGURE 9-17: VF R ESIZABLE BAR E XTENDED C APABILITY H EADER ....................................... 1146
F IGURE 9-18: VF R ESIZABLE BAR C ONTROL R EGISTER .......................................................... 1147
F IGURE 9-19: MSI-X C APABILITY ............................................................................................ 1159
F IGURE 10-1: E XAMPLE I LLUSTRATING A P LATFORM WITH TA, ATPT, AND ATC E LEMENTS . 1164
F IGURE 10-2: E XAMPLE ATS T RANSLATION R EQUEST /C OMPLETION E XCHANGE .................... 1165
F IGURE 10-3: E XAMPLE M ULTI -F UNCTION D EVICE WITH ATC PER F UNCTION ........................ 1168
F IGURE 10-4: I NVALIDATION P ROTOCOL WITH A S INGLE I NVALIDATION R EQUEST AND
C OMPLETION ...................................................................................................................... 1169
F IGURE 10-5: S INGLE I NVALIDATE R EQUEST WITH M ULTIPLE I NVALIDATE C OMPLETIONS ...... 1170
F IGURE 10-6: M EMORY R EQUEST H EADER WITH 64- BIT A DDRESS ........................................... 1173
F IGURE 10-7: M EMORY R EQUEST H EADER WITH 32- BIT A DDRESS ........................................... 1173
F IGURE 10-8: 64- BIT T RANSLATION R EQUEST H EADER ............................................................ 1174
F IGURE 10-9: 32- BIT T RANSLATION R EQUEST H EADER ............................................................ 1175
F IGURE 10-10: T RANSLATION C OMPLETION WITH N O D ATA .................................................... 1177
F IGURE 10-11: S UCCESSFUL T RANSLATION C OMPLETION ........................................................ 1178
F IGURE 10-12: T RANSLATION C OMPLETION D ATA E NTRY ....................................................... 1179
F IGURE 10-13: I NVALIDATE R EQUEST M ESSAGE ...................................................................... 1187
F IGURE 10-14: I NVALIDATE R EQUEST M ESSAGE B ODY ............................................................ 1188
F IGURE 10-15: I NVALIDATE C OMPLETION M ESSAGE F ORMAT .................................................. 1189
F IGURE 10-16: P AGE R EQUEST M ESSAGE .................................................................................. 1196
F IGURE 10-17: S TOP M ARKER M ESSAGE .................................................................................. 1199
F IGURE 10-18: PRG R ESPONSE M ESSAGE ................................................................................. 1201
F IGURE 10-19: ATS E XTENDED C APABILITY S TRUCTURE ........................................................ 1203
F IGURE 10-20: ATS E XTENDED C APABILITY H EADER .............................................................. 1203
F IGURE 10-21: ATS C APABILITY R EGISTER .............................................................................. 1204
F IGURE 10-22: ATS C ONTROL R EGISTER ................................................................................. 1204
F IGURE 10-23: P AGE R EQUEST E XTENDED C APABILITY S TRUCTURE ....................................... 1205
PCI Express Base Specification, Rev. 4.0 Version 1.0
30
F IGURE 10-24: P AGE R EQUEST E XTENDED C APABILITY H EADER .............................................. 1206
F IGURE 10-25: P AGE R EQUEST C ONTROL R EGISTER ................................................................. 1206
F IGURE 10-26: P AGE R EQUEST S TATUS R EGISTER .................................................................... 1207
F IGURE A-1: A N E XAMPLE S HOWING E NDPOINT - TO -R OOT -C OMPLEX AND P EER - TO -P EER
C OMMUNICATION M ODELS ................................................................................................ 1213
F IGURE A-2: T WO B ASIC B ANDWIDTH R ESOURCING P ROBLEMS : O VER -S UBSCRIPTION AND
C ONGESTION ...................................................................................................................... 1214
F IGURE A-3: A S IMPLIFIED E XAMPLE I LLUSTRATING PCI E XPRESS I SOCHRONOUS P ARAMETERS
........................................................................................................................................... 1219
F IGURE C-1: S CRAMBLING S PECTRUM AT 2.5 GT/ S FOR D ATA V ALUE OF 0 ............................. 1238
F IGURE E-1: R EFERENCE T OPOLOGY FOR IDO U SE .................................................................. 1245
F IGURE G-1: D EVICE AND P ROCESSOR C ONNECTED U SING A PMUX L INK .............................. 1253
F IGURE G-2: PMUX L INK ........................................................................................................ 1254
F IGURE G-3: PMUX P ACKET F LOW T HROUGH THE L AYERS .................................................... 1255
F IGURE G-4: PMUX P ACKET .................................................................................................... 1261
F IGURE G-5: TLP AND PMUX P ACKET F RAMING (8 B /10 B E NCODING ) .................................... 1262
F IGURE G-6: TLP AND PMUX P ACKET F RAMING (128 B /130 B E NCODING ) .............................. 1264
F IGURE G-7: PMUX E XTENDED C APABILITY ........................................................................... 1268
F IGURE G-8: PMUX E XTENDED C APABILITY H EADER ............................................................. 1268
F IGURE G-9: PMUX C APABILITY R EGISTER ............................................................................. 1269
F IGURE G-10: PMUX C ONTROL R EGISTER ............................................................................... 1271
F IGURE G-11: PMUX S TATUS R EGISTER .................................................................................. 1272
F IGURE G-12: PMUX P ROTOCOL A RRAY E NTRY ..................................................................... 1275
PCI Express Base Specification, Rev. 4.0 Version 1.0
31
Tables
T ABLE 2-1: T RANSACTION T YPES FOR D IFFERENT A DDRESS S PACES ........................................... 70
T ABLE 2-2: F MT [2:0] F IELD V ALUES ............................................................................................ 75
T ABLE 2-3: F MT [2:0] AND T YPE [4:0] F IELD E NCODINGS .............................................................. 75
T ABLE 2-4: L ENGTH [9:0] F IELD E NCODING .................................................................................. 77
T ABLE 2-5: A DDRESS F IELD M APPING .......................................................................................... 82
T ABLE 2-6: H EADER F IELD L OCATIONS FOR NON -ARI ID R OUTING ............................................. 83
T ABLE 2-7: H EADER F IELD L OCATIONS FOR ARI ID R OUTING ..................................................... 84
T ABLE 2-8: B YTE E NABLES L OCATION AND C ORRESPONDENCE ................................................... 86
T ABLE 2-9: O RDERING A TTRIBUTES ............................................................................................. 95
T ABLE 2-10: C ACHE C OHERENCY M ANAGEMENT A TTRIBUTE ...................................................... 96
T ABLE 2-11: D EFINITION OF TC F IELD E NCODINGS ...................................................................... 96
T ABLE 2-12: L ENGTH F IELD V ALUES FOR A TOMIC O P R EQUESTS ................................................. 97
T ABLE 2-13: TPH TLP P REFIX B IT M APPING ............................................................................. 101
T ABLE 2-14: L OCATION OF PH[1:0] IN TLP H EADER .................................................................. 102
T ABLE 2-15: P ROCESSING H INT E NCODING ................................................................................ 102
T ABLE 2-16: L OCATION OF ST[7:0] IN TLP H EADERS ................................................................ 103
T ABLE 2-17: M ESSAGE R OUTING ................................................................................................ 105
T ABLE 2-18: INT X M ECHANISM M ESSAGES ............................................................................... 107
T ABLE 2-19: B RIDGE M APPING FOR INT X V IRTUAL W IRES ....................................................... 109
T ABLE 2-20: P OWER M ANAGEMENT M ESSAGES ......................................................................... 111
T ABLE 2-21: E RROR S IGNALING M ESSAGES ............................................................................... 112
T ABLE 2-22: U NLOCK M ESSAGE ................................................................................................. 112
T ABLE 2-23: S ET _S LOT _P OWER _L IMIT M ESSAGE ..................................................................... 113
T ABLE 2-24: V ENDOR _D EFINED M ESSAGES ............................................................................... 114
T ABLE 2-25: N OTIFICATION R EASON (NR) F IELD E NCODINGS .................................................... 117
T ABLE 2-26: LN M ESSAGES ........................................................................................................ 117
T ABLE 2-27: DRS M ESSAGE ....................................................................................................... 118
T ABLE 2-28: FRS M ESSAGE ........................................................................................................ 120
T ABLE 2-29: H IERARCHY ID M ESSAGE ....................................................................................... 121
T ABLE 2-30: I GNORED M ESSAGES .............................................................................................. 122
T ABLE 2-31: LTR M ESSAGE ....................................................................................................... 122
T ABLE 2-32: OBFF M ESSAGE ..................................................................................................... 123
T ABLE 2-33: P RECISION T IME M EASUREMENT M ESSAGES .......................................................... 124
T ABLE 2-34: C OMPLETION S TATUS F IELD V ALUES ..................................................................... 126
T ABLE 2-35: L OCAL TLP P REFIX T YPES ..................................................................................... 129
T ABLE 2-36: E ND -E ND TLP P REFIX T YPES ................................................................................. 130
T ABLE 2-37: C ALCULATING B YTE C OUNT FROM L ENGTH AND B YTE E NABLES .......................... 145
T ABLE 2-38: C ALCULATING L OWER A DDRESS FROM 1 ST DW BE ............................................... 146
T ABLE 2-39: O RDERING R ULES S UMMARY ................................................................................. 151
T ABLE 2-40: TC TO VC M APPING E XAMPLE .............................................................................. 158
T ABLE 2-41: F LOW C ONTROL C REDIT T YPES ............................................................................. 162
T ABLE 2-42: TLP F LOW C ONTROL C REDIT C ONSUMPTION ........................................................ 162
T ABLE 2-43: M INIMUM I NITIAL F LOW C ONTROL A DVERTISEMENTS .......................................... 164
PCI Express Base Specification, Rev. 4.0 Version 1.0
32
T ABLE 2-44: [F IELD S IZE ] V ALUES ............................................................................................. 166
T ABLE 2-45: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 2.5 GT/ S
(S YMBOL T IMES ) ................................................................................................................. 172
T ABLE 2-46: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 5.0 GT/ S
(S YMBOL T IMES ) ................................................................................................................. 172
T ABLE 2-47: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 8.0 GT/ S (S YMBOL
T IMES ) ................................................................................................................................. 173
T ABLE 2-48: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 16.0 GT/ S
(S YMBOL T IMES ) ................................................................................................................. 173
T ABLE 2-49: M APPING OF B ITS INTO ECRC F IELD ..................................................................... 175
T ABLE 3-1: D ATA L INK F EATURE S UPPORTED B IT D EFINITION .................................................. 193
T ABLE 3-2: S CALED F LOW C ONTROL S CALING F ACTORS ........................................................... 198
T ABLE 3-3: DLLP T YPE E NCODINGS .......................................................................................... 199
T ABLE 3-4: H DR S CALE AND D ATA S CALE E NCODINGS ............................................................... 200
T ABLE 3-5: M APPING OF B ITS INTO CRC F IELD .......................................................................... 203
T ABLE 3-6: M APPING OF B ITS INTO LCRC F IELD ....................................................................... 207
T ABLE 3-7: M AXIMUM A CK L ATENCY L IMITS FOR 2.5 GT/ S (S YMBOL T IMES ) .......................... 222
T ABLE 3-8: M AXIMUM A CK L ATENCY L IMITS FOR 5.0 GT/ S (S YMBOL T IMES ) .......................... 222
T ABLE 3-9: M AXIMIM A CK L ATENCY L IMITS FOR 8.0 GT/ S (S YMBOL T IMES ) ........................... 222
T ABLE 3-10: M AXIMUM A CK L ATENCY L IMITS FOR 16.0 GT/ S (S YMBOL T IMES ) ....................... 223
T ABLE 4-1: S PECIAL S YMBOLS ................................................................................................... 228
T ABLE 4-2: F RAMING T OKEN E NCODING ................................................................................... 238
T ABLE 4-3: T RANSMITTER P RESET E NCODING ............................................................................ 263
T ABLE 4-4: R ECEIVER P RESET H INT E NCODING FOR 8.0 GT/ S .................................................... 263
T ABLE 4-5: TS1 O RDERED S ET ................................................................................................... 266
T ABLE 4-6: TS2 O RDERED S ET ................................................................................................... 269
T ABLE 4-7: E LECTRICAL I DLE O RDERED S ET (EIOS) FOR 2.5 GT/ S AND 5.0 GT/ S D ATA R ATES 272
T ABLE 4-8: E LECTRICAL I DLE O RDERED S ET (EIOS) FOR 8.0 GT/ S AND A BOVE D ATA R ATES .. 272
T ABLE 4-9: E LECTRICAL I DLE E XIT O RDERED S ET (EIEOS) FOR 5.0 GT/ S D ATA R ATE ............. 272
T ABLE 4-10: E LECTRICAL I DLE E XIT O RDERED S ET (EIEOS) FOR 8.0 GT/ S D ATA R ATES ......... 272
T ABLE 4-11: E LECTRICAL I DLE E XIT O RDERED S ET (EIEOS) FOR 16.0 GT/ S D ATA R ATE ......... 272
T ABLE 4-12: E LECTRICAL I DLE I NFERENCE C ONDITIONS ............................................................ 275
T ABLE 4-13: FTS FOR 8.0 GT/ S AND A BOVE D ATA R ATES ......................................................... 278
T ABLE 4-14: SDS O RDERED S ET ( FOR 8.0 GT/ S AND A BOVE D ATA R ATE ) ................................ 279
T ABLE 4-15: L INK S TATUS M APPED TO THE LTSSM ................................................................. 287
T ABLE 4-16: S TANDARD SKP O RDERED S ET WITH 128 B /130 B E NCODING ................................. 364
T ABLE 4-17: C ONTROL SKP O RDERED S ET WITH 128 B /130 B E NCODING ................................... 364
T ABLE 4-18: M ARGIN C OMMAND R ELATED F IELDS IN THE C ONTROL SKP O RDERED S ET ......... 375
T ABLE 4-19: M ARGIN C OMMANDS AND C ORRESPONDING R ESPONSES ....................................... 377
T ABLE 4-20: M AXIMUM R ETIMER E XIT L ATENCY ...................................................................... 396
T ABLE 4-21: I NFERRING E LECTRICAL I DLE ................................................................................. 397
T ABLE 4-22. R ETIMER L ATENCY L IMIT NOT SRIS (S YMBOL TIMES )........................................... 416
T ABLE 4-23: R ETIMER L ATENCY L IMIT SRIS (S YMBOL TIMES ) .................................................. 417
T ABLE 5-1: S UMMARY OF PCI E XPRESS L INK P OWER M ANAGEMENT S TATES ........................... 430
T ABLE 5-2: R ELATION B ETWEEN P OWER M ANAGEMENT S TATES OF L INK AND C OMPONENTS .. 436
T ABLE 5-3: E NCODING OF THE ASPM S UPPORT F IELD ............................................................... 464
PCI Express Base Specification, Rev. 4.0 Version 1.0
33
T ABLE 5-4: D ESCRIPTION OF THE S LOT C LOCK C ONFIGURATION B IT ......................................... 464
T ABLE 5-5: D ESCRIPTION OF THE C OMMON C LOCK C ONFIGURATION B IT .................................. 464
T ABLE 5-6: E NCODING OF THE L0 S E XIT L ATENCY F IELD .......................................................... 465
T ABLE 5-7: E NCODING OF THE L1 E XIT L ATENCY F IELD ............................................................ 465
T ABLE 5-8: E NCODING OF THE E NDPOINT L0 S A CCEPTABLE L ATENCY F IELD ............................ 465
T ABLE 5-9: E NCODING OF THE E NDPOINT L1 A CCEPTABLE L ATENCY F IELD .............................. 465
T ABLE 5-10: E NCODING OF THE ASPM C ONTROL F IELD ............................................................ 466
T ABLE 5-11: T IMING P ARAMETERS .............................................................................................. 478
T ABLE 5-12: P OWER M ANAGEMENT S YSTEM M ESSAGES AND DLLP S ....................................... 479
T ABLE 5-13: D0 P OWER M ANAGEMENT P OLICIES ...................................................................... 482
T ABLE 5-14: D1 P OWER M ANAGEMENT P OLICIES ...................................................................... 482
T ABLE 5-15: D2 P OWER M ANAGEMENT P OLICIES ...................................................................... 483
T ABLE 5-16: D3 HOT P OWER M ANAGEMENT P OLICIES .................................................................. 484
T ABLE 5-17: D3 COLD P OWER M ANAGEMENT P OLICIES ................................................................ 485
T ABLE 5-18: PCI F UNCTION S TATE T RANSITION D ELAYS .......................................................... 485
T ABLE 6-1: E RROR M ESSAGES .................................................................................................... 504
T ABLE 6-2: G ENERAL PCI E XPRESS E RROR L IST ........................................................................ 520
T ABLE 6-3: P HYSICAL L AYER E RROR L IST ................................................................................. 520
T ABLE 6-4: D ATA L INK L AYER E RROR L IST ............................................................................... 521
T ABLE 6-5: T RANSACTION L AYER E RROR L IST .......................................................................... 521
T ABLE 6-6: E LEMENTS OF H OT -P LUG ......................................................................................... 562
T ABLE 6-7: A TTENTION I NDICATOR S TATES ............................................................................... 563
T ABLE 6-8: P OWER I NDICATOR S TATES ...................................................................................... 564
T ABLE 6-9: ACS P2P R EQUEST R EDIRECT AND ACS P2P E GRESS C ONTROL I NTERACTIONS ..... 588
T ABLE 6-10: ECRC R ULES FOR MC_O VERLAY ......................................................................... 601
T ABLE 6-11: P ROCESSING H INT M APPING .................................................................................. 610
T ABLE 6-12: ST M ODES OF O PERATION ...................................................................................... 612
T ABLE 6-13: PASID TLP P REFIX ............................................................................................... 625
T ABLE 6-14: E MERGENCY P OWER R EDUCTION S UPPORTED V ALUES .......................................... 649
T ABLE 6-15: S YSTEM GUID A UTHORITY ID E NCODING ............................................................. 653
T ABLE 6-16: S MALL R ESOURCE D ATA T YPE T AG B IT D EFINITIONS ........................................... 666
T ABLE 6-17: L ARGE R ESOURCE D ATA T YPE T AG B IT D EFINITIONS ........................................... 666
T ABLE 6-18: R ESOURCE D ATA T YPE F LAGS FOR A T YPICAL VPD .............................................. 667
T ABLE 6-19: E XAMPLE OF A DD - IN S ERIAL C ARD N UMBER ........................................................ 668
T ABLE 6-20: VPD L ARGE AND S MALL R ESOURCE D ATA T AGS ................................................... 668
T ABLE 6-21: VPD R EAD -O NLY F IELDS ....................................................................................... 669
T ABLE 6-22: VPD R EAD /W RITE F IELDS ...................................................................................... 670
T ABLE 6-23: VPD E XAMPLE ........................................................................................................ 670
T ABLE 6-24: NPEM S TATES ....................................................................................................... 674
T ABLE 7-1: E NHANCED C ONFIGURATION A DDRESS M APPING .................................................... 679
T ABLE 7-2: R EGISTER AND R EGISTER B IT -F IELD T YPES ............................................................. 685
T ABLE 7-3: C OMMAND R EGISTER ............................................................................................... 689
T ABLE 7-4: S TATUS R EGISTER .................................................................................................... 693
T ABLE 7-5: H EADER T YPE R EGISTER .......................................................................................... 696
T ABLE 7-6: H EADER T YPE R EGISTER .......................................................................................... 697
T ABLE 7-7: BIST R EGISTER ........................................................................................................ 698
PCI Express Base Specification, Rev. 4.0 Version 1.0
34
T ABLE 7-8: M EMORY B ASE A DDRESS R EGISTER B ITS 2:1 E NCODING ........................................ 702
T ABLE 7-9: I/O A DDRESSING C APABILITY .................................................................................. 710
T ABLE 7-10: S ECONDARY S TATUS R EGISTER ............................................................................. 711
T ABLE 7-11: B RIDGE C ONTROL R EGISTER .................................................................................. 715
T ABLE 7-12: P OWER M ANAGEMENT C APABILITIES R EGISTER .................................................... 718
T ABLE 7-13: P OWER M ANAGEMENT C ONTROL /S TATUS R EGISTER R EQUIREMENTS ................... 721
T ABLE 7-14: D ATA R EGISTER ..................................................................................................... 723
T ABLE 7-15: P OWER C ONSUMPTION /D ISSIPATION R EPORTING ................................................... 723
T ABLE 7-16: PCI E XPRESS C APABILITY L IST R EGISTER ............................................................. 726
T ABLE 7-17: PCI E XPRESS C APABILITIES R EGISTER ................................................................... 727
T ABLE 7-18: D EVICE C APABILITIES R EGISTER ............................................................................ 729
T ABLE 7-19: D EVICE C ONTROL R EGISTER .................................................................................. 733
T ABLE 7-20: D EVICE S TATUS R EGISTER ..................................................................................... 740
T ABLE 7-21: L INK C APABILITIES R EGISTER ................................................................................ 743
T ABLE 7-22: L INK C ONTROL R EGISTER ...................................................................................... 749
T ABLE 7-23: L INK S TATUS R EGISTER ......................................................................................... 757
T ABLE 7-24: S LOT C APABILITIES R EGISTER ............................................................................... 760
T ABLE 7-25: S LOT C ONTROL R EGISTER ...................................................................................... 762
T ABLE 7-26: S LOT S TATUS R EGISTER ......................................................................................... 765
T ABLE 7-27: R OOT C ONTROL R EGISTER ..................................................................................... 767
T ABLE 7-28: R OOT C APABILITIES R EGISTER ............................................................................... 769
T ABLE 7-29: R OOT S TATUS R EGISTER ........................................................................................ 769
T ABLE 7-30: D EVICE C APABILITIES 2 R EGISTER ......................................................................... 771
T ABLE 7-31: D EVICE C ONTROL 2 R EGISTER ................................................................................ 778
T ABLE 7-32: L INK C APABILITIES 2 R EGISTER ............................................................................. 783
T ABLE 7-33: L INK C ONTROL 2 R EGISTER ................................................................................... 787
T ABLE 7-34: L INK S TATUS 2 R EGISTER ...................................................................................... 792
T ABLE 7-35: PCI E XPRESS E XTENDED C APABILITY H EADER ..................................................... 797
T ABLE 7-36: MSI C APABILITY H EADER ..................................................................................... 800
T ABLE 7-37: M ESSAGE C ONTROL R EGISTER FOR MSI ................................................................ 801
T ABLE 7-38: M ESSAGE A DDRESS R EGISTER FOR MSI ................................................................ 803
T ABLE 7-39: M ESSAGE U PPER A DDRESS R EGISTER FOR MSI ..................................................... 803
T ABLE 7-40: M ESSAGE D ATA R EGISTER FOR MSI ...................................................................... 804
T ABLE 7-41: E XTENDED M ESSAGE D ATA R EGISTER FOR MSI .................................................... 805
T ABLE 7-42: M ASK B ITS R EGISTER FOR MSI .............................................................................. 805
T ABLE 7-43: P ENDING B ITS R EGISTER FOR MSI ......................................................................... 806
T ABLE 7-44: MSI-X C APABILITY H EADER ................................................................................. 809
T ABLE 7-45: M ESSAGE C ONTROL R EGISTER FOR MSI-X ............................................................ 810
T ABLE 7-46: T ABLE O FFSET /T ABLE BIR R EGISTER FOR MSI-X ................................................. 811
T ABLE 7-47: PBA O FFSET /PBA BIR R EGISTER FOR MSI-X ...................................................... 812
T ABLE 7-48: M ESSAGE A DDRESS R EGISTER FOR MSI-X T ABLE E NTRIES .................................. 812
T ABLE 7-49: M ESSAGE U PPER A DDRESS R EGISTER FOR MSI-X T ABLE E NTRIES ....................... 813
T ABLE 7-50: M ESSAGE D ATA R EGISTER FOR MSI-X T ABLE E NTRIES ........................................ 813
T ABLE 7-51: V ECTOR C ONTROL R EGISTER FOR MSI-X T ABLE E NTRIES .................................... 814
T ABLE 7-52: P ENDING B ITS R EGISTER FOR MSI-X PBA E NTRIES .............................................. 815
T ABLE 7-53: S ECONDARY PCI E XPRESS E XTENDED C APABILITY H EADER ................................. 816
PCI Express Base Specification, Rev. 4.0 Version 1.0
35
T ABLE 7-54: L INK C ONTROL 3 R EGISTER ................................................................................... 817
T ABLE 7-55: L ANE E RROR S TATUS R EGISTER ............................................................................ 818
T ABLE 7-56: L ANE E QUALIZATION C ONTROL R EGISTER E NTRY ................................................. 819
T ABLE 7-57: D ATA L INK F EATURE E XTENDED C APABILITY H EADER ......................................... 822
T ABLE 7-58: D ATA L INK F EATURE C APABILITIES R EGISTER ...................................................... 823
T ABLE 7-59: D ATA L INK F EATURE S TATUS R EGISTER ................................................................ 824
T ABLE 7-60: P HYSICAL L AYER 16.0 GT/ S E XTENDED C APABILITY H EADER .............................. 825
T ABLE 7-61: 16.0 GT/ S C APABILITIES R EGISTER ........................................................................ 826
T ABLE 7-62: 16.0 GT/ S C ONTROL R EGISTER .............................................................................. 826
T ABLE 7-63: 16.0 GT/ S S TATUS R EGISTER ................................................................................. 827
T ABLE 7-64: 16.0 GT/ S L OCAL D ATA P ARITY M ISMATCH S TATUS R EGISTER ............................ 828
T ABLE 7-65: 16.0 GT/ S F IRST R ETIMER D ATA P ARITY M ISMATCH S TATUS R EGISTER ............... 829
T ABLE 7-66: 16.0 GT/ S S ECOND R ETIMER D ATA P ARITY M ISMATCH S TATUS R EGISTER ........... 829
T ABLE 7-67: 16.0 GT/ S L ANE ((M AXIMUM L INK W IDTH – 1):0) E QUALIZATION C ONTROL
R EGISTER E NTRY ................................................................................................................. 830
T ABLE 7-68: P HYSICAL L AYER 16.0 GT/ S M ARGINING E XTENDED C APABILITY H EADER .......... 833
T ABLE 7-69: M ARGINING P ORT C APABILITIES R EGISTER ........................................................... 834
T ABLE 7-70: M ARGINING P ORT S TATUS R EGISTER ..................................................................... 834
T ABLE 7-71: L ANE N: M ARGINING L ANE S TATUS R EGISTER E NTRY .......................................... 836
T ABLE 7-72: ACS E XTENDED C APABILITY H EADER ................................................................... 837
T ABLE 7-73: ACS C APABILITY R EGISTER ................................................................................... 838
T ABLE 7-74: ACS C ONTROL R EGISTER ...................................................................................... 839
T ABLE 7-75: E GRESS C ONTROL V ECTOR .................................................................................... 841
T ABLE 7-76: P OWER B UDGETING E XTENDED C APABILITY H EADER ........................................... 843
T ABLE 7-77: P OWER B UDGETING D ATA R EGISTER ..................................................................... 844
T ABLE 7-78: P OWER B UDGET C APABILITY R EGISTER ................................................................. 847
T ABLE 7-79: LTR E XTENDED C APABILITY H EADER ................................................................... 848
T ABLE 7-80: M AX S NOOP L ATENCY R EGISTER ........................................................................... 849
T ABLE 7-81: M AX N O -S NOOP L ATENCY R EGISTER .................................................................... 849
T ABLE 7-82: L1 PM S UBSTATES E XTENDED C APABILITY H EADER ............................................ 851
T ABLE 7-83: L1 PM S UBSTATES C APABILITIES R EGISTER ........................................................... 851
T ABLE 7-84: L1 PM S UBSTATES C ONTROL 1 R EGISTER .............................................................. 853
T ABLE 7-85: L1 PM S UBSTATES C ONTROL 2 R EGISTER .............................................................. 855
T ABLE 7-86: A DVANCED E RROR R EPORTING E XTENDED C APABILITY H EADER ......................... 858
T ABLE 7-87: U NCORRECTABLE E RROR S TATUS R EGISTER ......................................................... 859
T ABLE 7-88: U NCORRECTABLE E RROR M ASK R EGISTER ............................................................ 861
T ABLE 7-89: U NCORRECTABLE E RROR S EVERITY R EGISTER ...................................................... 863
T ABLE 7-90: C ORRECTABLE E RROR S TATUS R EGISTER .............................................................. 865
T ABLE 7-91: C ORRECTABLE E RROR M ASK R EGISTER ................................................................. 866
T ABLE 7-92: A DVANCED E RROR C APABILITIES AND C ONTROL R EGISTER .................................. 867
T ABLE 7-93: H EADER L OG R EGISTER ......................................................................................... 869
T ABLE 7-94: R OOT E RROR C OMMAND R EGISTER ....................................................................... 869
T ABLE 7-95: R OOT E RROR S TATUS R EGISTER ............................................................................ 871
T ABLE 7-96: E RROR S OURCE I DENTIFICATION R EGISTER ........................................................... 873
T ABLE 7-97: TLP P REFIX L OG R EGISTER ................................................................................... 874
T ABLE 7-98: F IRST DW OF E NHANCED A LLOCATION C APABILITY ............................................. 874
PCI Express Base Specification, Rev. 4.0 Version 1.0
36
T ABLE 7-99: F IRST DW OF E ACH E NTRY FOR E NHANCED A LLOCATION C APABILITY ................ 875
T ABLE 7-100: E NHANCED A LLOCATION E NTRY F IELD V ALUE D EFINITIONS FOR BOTH THE
P RIMARY P ROPERTIES AND S ECONDARY P ROPERTIES F IELDS .............................................. 879
T ABLE 7-101: R ESIZABLE BAR E XTENDED C APABILITY H EADER .............................................. 883
T ABLE 7-102: R ESIZABLE BAR C APABILITY R EGISTER .............................................................. 884
T ABLE 7-103: R ESIZABLE BAR C ONTROL R EGISTER .................................................................. 885
T ABLE 7-104: ARI C APABILITY H EADER .................................................................................... 888
T ABLE 7-105: ARI C APABILITY R EGISTER ................................................................................. 888
T ABLE 7-106: ARI C ONTROL R EGISTER ..................................................................................... 889
T ABLE 7-107: PASID E XTENDED C APABILITY H EADER ............................................................. 890
T ABLE 7-108: PASID C APABILITY R EGISTER ............................................................................. 891
T ABLE 7-109: PASID C ONTROL R EGISTER ................................................................................. 892
T ABLE 7-110: FRS Q UEUING E XTENDED C APABILITY H EADER ................................................. 893
T ABLE 7-111: FRS Q UEUING C APABILITY R EGISTER ................................................................. 894
T ABLE 7-112: FRS Q UEUING S TATUS R EGISTER ........................................................................ 895
T ABLE 7-113: FRS Q UEUING C ONTROL R EGISTER ..................................................................... 896
T ABLE 7-114: FRS M ESSAGE Q UEUE R EGISTER .......................................................................... 896
T ABLE 7-115: FPB C APABILITY H EADER ................................................................................... 897
T ABLE 7-116: FPB C APABILITIES R EGISTER ............................................................................... 898
T ABLE 7-117: FPB RID V ECTOR C ONTROL 1 R EGISTER ............................................................. 900
T ABLE 7-118: FPB RID V ECTOR C ONTROL 2 R EGISTER ............................................................. 902
T ABLE 7-119: FPB MEM L OW V ECTOR C ONTROL R EGISTER .................................................... 902
T ABLE 7-120: FPB MEM H IGH V ECTOR C ONTROL 1 R EGISTER ................................................. 904
T ABLE 7-121: FPB MEM H IGH V ECTOR C ONTROL 2 R EGISTER ................................................. 906
T ABLE 7-122: FPB V ECTOR A CCESS C ONTROL R EGISTER .......................................................... 907
T ABLE 7-123: FPB V ECTOR A CCESS D ATA R EGISTER ................................................................ 908
T ABLE 7-124: V IRTUAL C HANNEL E XTENDED C APABILITY H EADER ......................................... 910
T ABLE 7-125: P ORT VC C APABILITY R EGISTER 1 ....................................................................... 911
T ABLE 7-126: P ORT VC C APABILITY R EGISTER 2 ....................................................................... 913
T ABLE 7-127: P ORT VC C ONTROL R EGISTER ............................................................................. 914
T ABLE 7-128: P ORT VC S TATUS R EGISTER ................................................................................ 915
T ABLE 7-129: VC R ESOURCE C APABILITY R EGISTER ................................................................. 916
T ABLE 7-130: VC R ESOURCE C ONTROL R EGISTER ..................................................................... 917
T ABLE 7-131: VC R ESOURCE S TATUS R EGISTER ........................................................................ 920
T ABLE 7-132: D EFINITION OF THE 4- BIT E NTRIES IN THE VC A RBITRATION T ABLE ................... 921
T ABLE 7-133: L ENGTH OF THE VC A RBITRATION T ABLE ........................................................... 921
T ABLE 7-134: L ENGTH OF P ORT A RBITRATION T ABLE ............................................................... 923
T ABLE 7-135: MFVC E XTENDED C APABILITY H EADER ............................................................. 925
T ABLE 7-136: P ORT VC C APABILITY R EGISTER 1 ....................................................................... 926
T ABLE 7-137: P ORT VC C APABILITY R EGISTER 2 ....................................................................... 927
T ABLE 7-138: P ORT VC C ONTROL R EGISTER ............................................................................. 928
T ABLE 7-139: P ORT VC S TATUS R EGISTER ................................................................................ 929
T ABLE 7-140: VC R ESOURCE C APABILITY R EGISTER ................................................................. 930
T ABLE 7-141: VC R ESOURCE C ONTROL R EGISTER ..................................................................... 931
T ABLE 7-142: VC R ESOURCE S TATUS R EGISTER ........................................................................ 933
T ABLE 7-143: L ENGTH OF F UNCTION A RBITRATION T ABLE ....................................................... 935
PCI Express Base Specification, Rev. 4.0 Version 1.0
37
T ABLE 7-144: D EVICE S ERIAL N UMBER E XTENDED C APABILITY H EADER ................................. 936
T ABLE 7-145: S ERIAL N UMBER R EGISTER .................................................................................. 937
T ABLE 7-146: V ENDOR -S PECIFIC C APABILITY ............................................................................ 938
T ABLE 7-147: V ENDOR -S PECIFIC E XTENDED C APABILITY H EADER ........................................... 939
T ABLE 7-148: V ENDOR -S PECIFIC H EADER .................................................................................. 940
T ABLE 7-149: D ESIGNATED V ENDOR -S PECIFIC E XTENDED C APABILITY H EADER ...................... 942
T ABLE 7-150: D ESIGNATED V ENDOR -S PECIFIC H EADER 1 .......................................................... 942
T ABLE 7-151: D ESIGNATED V ENDOR -S PECIFIC H EADER 2 .......................................................... 943
T ABLE 7-152: RCRB H EADER E XTENDED C APABILITY H EADER ............................................... 944
T ABLE 7-153: V ENDOR ID AND D EVICE ID ................................................................................ 944
T ABLE 7-154: RCRB C APABILITIES ............................................................................................ 945
T ABLE 7-155: RCRB C ONTROL .................................................................................................. 945
T ABLE 7-156: R OOT C OMPLEX L INK D ECLARATION E XTENDED C APABILITY H EADER .............. 947
T ABLE 7-157: E LEMENT S ELF D ESCRIPTION R EGISTER ............................................................... 948
T ABLE 7-158: L INK D ESCRIPTION R EGISTER .............................................................................. 950
T ABLE 7-159: L INK A DDRESS FOR L INK T YPE 1 ......................................................................... 952
T ABLE 7-160: R OOT C OMPLEX I NTERNAL L INK C ONTROL E XTENDED C APABILITY H EADER ..... 953
T ABLE 7-161: R OOT C OMPLEX L INK C APABILITIES R EGISTER ................................................... 954
T ABLE 7-162: R OOT C OMPLEX L INK C ONTROL R EGISTER .......................................................... 958
T ABLE 7-163: R OOT C OMPLEX L INK S TATUS R EGISTER ............................................................. 959
T ABLE 7-164: R OOT C OMPLEX E VENT C OLLECTOR E NDPOINT A SSOCIATION E XTENDED
C APABILITY H EADER ........................................................................................................... 961
T ABLE 7-165: M ULTICAST E XTENDED C APABILITY H EADER ..................................................... 963
T ABLE 7-166: M ULTICAST C APABILITY R EGISTER ..................................................................... 963
T ABLE 7-167: M ULTICAST C ONTROL R EGISTER ......................................................................... 964
T ABLE 7-168: MC_B ASE A DDRESS R EGISTER ............................................................................ 965
T ABLE 7-169: MC_R ECEIVE R EGISTER ...................................................................................... 965
T ABLE 7-170: MC_B LOCK _A LL R EGISTER ................................................................................ 966
T ABLE 7-171: MC_B LOCK _U NTRANSLATED R EGISTER ............................................................. 967
T ABLE 7-172: MC_O VERLAY BAR ............................................................................................ 967
T ABLE 7-173: DPA E XTENDED C APABILITY H EADER ................................................................ 968
T ABLE 7-174: DPA C APABILITY R EGISTER ................................................................................ 969
T ABLE 7-175: DPA L ATENCY I NDICATOR R EGISTER .................................................................. 970
T ABLE 7-176: DPA S TATUS R EGISTER ....................................................................................... 970
T ABLE 7-177: DPA C ONTROL R EGISTER .................................................................................... 971
T ABLE 7-178: S UBSTATE P OWER A LLOCATION R EGISTER (0 TO S UBSTATE _M AX ) .................... 971
T ABLE 7-179: TPH R EQUESTER E XTENDED C APABILITY H EADER ............................................. 972
T ABLE 7-180: TPH R EQUESTER C APABILITY R EGISTER ............................................................. 973
T ABLE 7-181: TPH R EQUESTER C ONTROL R EGISTER ................................................................. 974
T ABLE 7-182: TPH ST T ABLE .................................................................................................... 975
T ABLE 7-183: LNR E XTENDED C APABILITY H EADER ................................................................. 976
T ABLE 7-184: LNR C APABILITY R EGISTER ................................................................................. 977
T ABLE 7-185: LNR C ONTROL R EGISTER ..................................................................................... 978
T ABLE 7-186: DPC E XTENDED C APABILITY H EADER ................................................................. 979
T ABLE 7-187: DPC C APABILITY R EGISTER ................................................................................. 980
T ABLE 7-188: DPC C ONTROL R EGISTER .................................................................................... 982
PCI Express Base Specification, Rev. 4.0 Version 1.0
38
T ABLE 7-189: DPC S TATUS R EGISTER ....................................................................................... 983
T ABLE 7-190: DPC E RROR S OURCE ID R EGISTER ...................................................................... 985
T ABLE 7-191: RP PIO S TATUS R EGISTER ................................................................................... 986
T ABLE 7-192: RP PIO M ASK R EGISTER ...................................................................................... 987
T ABLE 7-193: RP PIO S EVERITY R EGISTER ................................................................................. 988
T ABLE 7-194: RP PIO S YS E RROR R EGISTER ............................................................................... 988
T ABLE 7-195: RP PIO E XCEPTION R EGISTER .............................................................................. 990
T ABLE 7-196: RP PIO H EADER L OG R EGISTER ........................................................................... 990
T ABLE 7-197: RP PIO I MP S PEC L OG R EGISTER ........................................................................... 991
T ABLE 7-198: RP PIO TLP P REFIX L OG R EGISTER ..................................................................... 992
T ABLE 7-199: PTM E XTENDED C APABILITY H EADER ................................................................. 993
T ABLE 7-200: PTM C APABILITY R EGISTER ................................................................................. 993
T ABLE 7-201: PTM C ONTROL R EGISTER ..................................................................................... 994
T ABLE 7-202: R EADINESS T IME R EPORTING E XTENDED C APABILITY H EADER ........................... 997
T ABLE 7-203: R EADINESS T IME R EPORTING 1 R EGISTER ............................................................ 998
T ABLE 7-204: R EADINESS T IME R EPORTING 2 R EGISTER ............................................................ 999
T ABLE 7-205: H IERARCHY ID E XTENDED C APABILITY H EADER .............................................. 1001
T ABLE 7-206: H IERARCHY ID S TATUS R EGISTER ..................................................................... 1002
T ABLE 7-207: H IERARCHY ID D ATA R EGISTER ........................................................................ 1004
T ABLE 7-208: H IERARCHY ID GUID 1 R EGISTER ..................................................................... 1005
T ABLE 7-209: H IERARCHY ID GUID 2 R EGISTER ..................................................................... 1006
T ABLE 7-210: H IERARCHY ID GUID 3 R EGISTER ..................................................................... 1006
T ABLE 7-211: H IERARCHY ID GUID 4 R EGISTER ..................................................................... 1007
T ABLE 7-212: H IERARCHY ID GUID 5 R EGISTER ..................................................................... 1008
T ABLE 7-213: VPD R EGISTER F IELDS ....................................................................................... 1009
T ABLE 7-214: NPEM E XTENDED C APABILITY H EADER ........................................................... 1010
T ABLE 7-215: NPEM C ONTROL R EGISTER ............................................................................... 1013
T ABLE 7-216: NPEM S TATUS R EGISTER .................................................................................. 1015
T ABLE 8-1. T X P RESET R ATIOS AND C ORRESPONDING C OEFFICIENT V ALUES .......................... 1022
T ABLE 8-2. P RESET M EASUREMENT C ROSS R EFERENCE T ABLE ............................................... 1024
T ABLE 8-3: T RANSMIT E QUALIZATION C OEFFICIENT S PACE T RIANGULAR M ATRIX E XAMPLE . 1026
T ABLE 8-4. C ASES THAT THE R EFERENCE P ACKAGES AND PS 21TX P ARAMETER ARE N ORMATIVE
........................................................................................................................................... 1028
T ABLE 8-5: R ECOMMENDED D E - EMBEDDING C UTOFF F REQUENCY .......................................... 1030
T ABLE 8-6: T X M EASUREMENT AND P OST P ROCESSING F OR D IFFERENT R EFCLKS ................... 1031
T ABLE 8-7: D ATA R ATE D EPENDENT T RANSMITTER P ARAMETERS .......................................... 1038
T ABLE 8-8: D ATA R ATE I NDEPENDENT T X P ARAMETERS .......................................................... 1042
T ABLE 8-9: C ALIBRATION C HANNEL IL L IMITS ......................................................................... 1045
T ABLE 8-10: S TRESSED J ITTER E YE P ARAMETERS .................................................................... 1057
T ABLE 8-11: C OMMON R ECEIVER P ARAMETERS ........................................................................ 1062
T ABLE 8-12: L ANE M ARGINING T IMING ................................................................................... 1066
T ABLE 8-13: P ACKAGE M ODEL C APACITANCE V ALUES ........................................................... 1072
T ABLE 8-14: J ITTER /V OLTAGE P ARAMETERS FOR C HANNEL T OLERANCING ............................ 1076
T ABLE 8-15: C HANNEL T OLERANCING E YE M ASK V ALUES ..................................................... 1078
T ABLE 8-16: EIEOS S IGNALING P ARAMETERS ......................................................................... 1079
T ABLE 8-17: REFCLK DC S PECIFICATIONS AND AC T IMING R EQUIREMENTS ........................ 1080
PCI Express Base Specification, Rev. 4.0 Version 1.0
39
T ABLE 8-18: D ATA R ATE I NDEPENDENT R EFCLK P ARAMETERS ................................................ 1083
T ABLE 8-19: C OMMON R EFCLK PLL AND CDR C HARACTERISTICS FOR 2.5 GT/ S ..................... 1087
T ABLE 8-20: C OMMON R EFCLK PLL AND CDR C HARACTERISTICS FOR 5.0 GT/ S ..................... 1087
T ABLE 8-21: C OMMON R EFCLK PLL AND CDR C HARACTERISTICS FOR 8.0 AND 16.0 GT/ S ..... 1088
T ABLE 8-22: J ITTER L IMITS FOR CC A RCHITECTURE ................................................................. 1088
T ABLE 8-23: F ORM F ACTOR C LOCKING A RCHITECTURE R EQUIREMENTS ................................. 1089
T ABLE 8-24: C OMMON C LOCK A RCHITECTURE D ETAILS .......................................................... 1089
T ABLE 8-25: F ORM F ACTOR C LOCKING A RCHITECTURE R EQUIREMENTS E XAMPLE ................. 1089
T ABLE 8-26: C OMMON C LOCK A RCHITECTURE D ETAILS E XAMPLE ......................................... 1089
T ABLE 9-1: VF R OUTING ID A LGORITHM ................................................................................. 1105
T ABLE 9-2: SR-IOV VF M IGRATION S TATE T ABLE ................................................................. 1111
T ABLE 9-3: SR-IOV E XTENDED C APABILITY H EADER ............................................................. 1113
T ABLE 9-4: SR-IOV C APABILITIES ........................................................................................... 1114
T ABLE 9-5: SR-IOV C ONTROL ................................................................................................. 1117
T ABLE 9-6: SR-IOV S TATUS .................................................................................................... 1121
T ABLE 9-7: BAR O FFSETS ........................................................................................................ 1127
T ABLE 9-8: VF M IGRATION S TATE A RRAY O FFSET .................................................................. 1128
T ABLE 9-9: VF M IGRATION S TATE E NTRY ............................................................................... 1129
T ABLE 9-10: VF M IGRATION S TATE D ESCRIPTIONS ................................................................. 1129
T ABLE 9-11: SR-PCIM I NITIATED VF M IGRATION S TATE T RANSITIONS ................................. 1129
T ABLE 9-12: MR-PCIM I NITIATED VF M IGRATION S TATE T RANSITIONS ................................ 1130
T ABLE 9-13: C OMMAND R EGISTER ........................................................................................... 1132
T ABLE 9-14: S TATUS R EGISTER ................................................................................................ 1133
T ABLE 9-15: D EVICE C APABILITIES R EGISTER ......................................................................... 1135
T ABLE 9-16: D EVICE C ONTROL R EGISTER ................................................................................ 1136
T ABLE 9-17: D EVICE S TATUS R EGISTER ................................................................................... 1136
T ABLE 9-18: L INK C ONTROL R EGISTER .................................................................................... 1137
T ABLE 9-19: D EVICE C APABILITIES 2 R EGISTER ....................................................................... 1138
T ABLE 9-20: D EVICE C ONTROL 2 R EGISTER ............................................................................. 1139
T ABLE 9-21. L INK S TATUS 2 R EGISTER ..................................................................................... 1140
T ABLE 9-22: SR-IOV U SAGE OF PCI S TANDARD C APABILITIES ............................................... 1140
T ABLE 9-23: SR-IOV U SAGE OF PCI E XPRESS E XTENDED C APABILITIES ................................ 1141
T ABLE 9-24: VF R ESIZABLE BAR E XTENDED C APABILITY H EADER ........................................ 1146
T ABLE 9-25: VF R ESIZABLE BAR C ONTROL R EGISTER ............................................................ 1147
T ABLE 9-26: ACS C APABILITY R EGISTER ................................................................................ 1148
T ABLE 9-27: ARI C APABILITY R EGISTER ................................................................................. 1149
T ABLE 9-28: ATS C APABILITY R EGISTER ................................................................................. 1150
T ABLE 9-29: ATS C ONTROL R EGISTER .................................................................................... 1150
T ABLE 9-30: M ULTICAST C APABILITY R EGISTER ..................................................................... 1150
T ABLE 9-31: M ULTICAST C ONTROL R EGISTER ......................................................................... 1151
T ABLE 9-32: M ULTICAST B ASE A DDRESS R EGISTER ................................................................ 1151
T ABLE 9-33: U NCORRECTABLE E RROR S TATUS R EGISTER ....................................................... 1154
T ABLE 9-34: U NCORRECTABLE E RROR M ASK R EGISTER .......................................................... 1154
T ABLE 9-35: U NCORRECTABLE E RROR S EVERITY R EGISTER .................................................... 1155
T ABLE 9-36: C ORRECTABLE E RROR S TATUS R EGISTER ............................................................ 1156
T ABLE 9-37: C ORRECTABLE E RROR M ASK R EGISTER .............................................................. 1156
PCI Express Base Specification, Rev. 4.0 Version 1.0
40
T ABLE 9-38: A DVANCED E RROR C APABILITIES AND C ONTROL R EGISTER ............................... 1156
T ABLE 9-39: H EADER L OG R EGISTER ....................................................................................... 1157
T ABLE 9-40: MSI C APABILITY : M ESSAGE C ONTROL ................................................................ 1159
T ABLE 9-41: P OWER M ANAGEMENT C ONTROL /S TATUS (PMCSR) .......................................... 1161
T ABLE 9-42: P OWER M ANAGEMENT D ATA R EGISTER .............................................................. 1162
T ABLE 10-1: A DDRESS T YPE (AT) F IELD E NCODINGS .............................................................. 1174
T ABLE 10-2: T RANSLATION C OMPLETION WITH N O D ATA S TATUS C ODES .............................. 1177
T ABLE 10-3: T RANSLATION C OMPLETION D ATA F IELDS .......................................................... 1179
T ABLE 10-4: E XAMPLES OF T RANSLATION S IZE U SING S F IELD ............................................... 1181
T ABLE 10-5: P AGE R EQUEST M ESSAGE D ATA F IELDS .............................................................. 1196
T ABLE 10-6: PRG R ESPONSE M ESSAGE D ATA F IELDS .............................................................. 1201
T ABLE 10-7: R ESPONSE C ODES ................................................................................................. 1202
T ABLE 10-8: ATS E XTENDED C APABILITY H EADER ................................................................. 1203
T ABLE 10-9: ATS C APABILITY R EGISTER ................................................................................. 1204
T ABLE 10-10: ATS C ONTROL R EGISTER ................................................................................... 1205
T ABLE 10-11: P AGE R EQUEST E XTENDED C APABILITY H EADER .............................................. 1206
T ABLE 10-12: P AGE R EQUEST C ONTROL R EGISTER .................................................................. 1207
T ABLE 10-13: P AGE R EQUEST S TATUS R EGISTER ..................................................................... 1208
T ABLE A-1: I SOCHRONOUS B ANDWIDTH R ANGES AND G RANULARITIES .................................. 1216
T ABLE B-1: 8 B /10 B D ATA S YMBOL C ODES ............................................................................... 1224
T ABLE B-2: 8 B /10 B S PECIAL C HARACTER S YMBOL C ODES ...................................................... 1232
T ABLE F-1: M ESSAGE C ODE U SAGE ......................................................................................... 1251
T ABLE F-2: PCI-SIG-D EFINED VDM S UBTYPE U SAGE ............................................................. 1252
T ABLE G-1: PCI E XPRESS A TTRIBUTE I MPACT ON P ROTOCOL M ULTIPLEXING ......................... 1256
T ABLE G-2: PMUX A TTRIBUTE I MPACT ON PCI E XPRESS ....................................................... 1259
T ABLE G-3: PMUX P ACKET L AYOUT (8 B /10 B E NCODING ) ...................................................... 1263
T ABLE G-4: PMUX P ACKET L AYOUT (128 B /130 B E NCODING ) ................................................ 1265
T ABLE G-5: S YMBOL 1 B ITS [6:3] ............................................................................................. 1266
T ABLE G-6: PMUX E XTENDED C APABILITY H EADER .............................................................. 1268
T ABLE G-7: PMUX C APABILITY R EGISTER .............................................................................. 1269
T ABLE G-8: PMUX C ONTROL R EGISTER .................................................................................. 1271
T ABLE G-9: PMUX S TATUS R EGISTER ..................................................................................... 1273
T ABLE G-10: PMUX P ROTOCOL A RRAY E NTRY ...................................................................... 1275
T ABLE H-1: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 2.5 GT/ S M ODE
O PERATION BY L INK W IDTH AND M AX P AYLOAD (S YMBOL T IMES ) ................................. 1278
T ABLE H-2: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 5.0 GT/ S M ODE
O PERATION BY L INK W IDTH AND M AX P AYLOAD (S YMBOL T IMES ) ................................. 1278
T ABLE H-3: M AXIMUM U PDATE FC T RANSMISSION L ATENCY G UIDELINES FOR 8.0 GT/ S
O PERATION BY L INK W IDTH AND M AX P AYLOAD (S YMBOL T IMES ) ................................. 1279
T ABLE H-4: M AXIMUM A CK L ATENCY L IMIT AND A CK F ACTOR FOR 2.5 GT/ S (S YMBOL T IMES )
........................................................................................................................................... 1280
T ABLE H-5: M AXIMUM A CK T RANSMISSION L ATENCY L IMIT AND A CK F ACTOR FOR 5.0 GT/ S
(S YMBOL T IMES ) ............................................................................................................... 1281
T ABLE H-6: M AXIMUM A CK T RANSMISSION L ATENCY L IMIT AND A CK F ACTOR FOR 8.0 GT/ S
(S YMBOL T IMES ) ............................................................................................................... 1281